IncompatiblePciDeviceSupport.c 16 KB

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  1. /** @file
  2. A simple DXE_DRIVER that causes the PCI Bus UEFI_DRIVER to allocate 64-bit
  3. MMIO BARs above 4 GB, regardless of option ROM availability (as long as a CSM
  4. is not present), conserving 32-bit MMIO aperture for 32-bit BARs.
  5. Copyright (C) 2016, Red Hat, Inc.
  6. Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
  7. SPDX-License-Identifier: BSD-2-Clause-Patent
  8. **/
  9. #include <Library/BaseLib.h>
  10. #include <Library/BaseMemoryLib.h>
  11. #include <IndustryStandard/Acpi10.h>
  12. #include <IndustryStandard/Pci22.h>
  13. #include <Library/DebugLib.h>
  14. #include <Library/MemoryAllocationLib.h>
  15. #include <Library/PcdLib.h>
  16. #include <Library/UefiBootServicesTableLib.h>
  17. #include <Library/CcProbeLib.h>
  18. #include <Protocol/IncompatiblePciDeviceSupport.h>
  19. #include <Protocol/LegacyBios.h>
  20. //
  21. // The Legacy BIOS protocol has been located.
  22. //
  23. STATIC BOOLEAN mLegacyBiosInstalled;
  24. //
  25. // The protocol interface this driver produces.
  26. //
  27. STATIC EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL
  28. mIncompatiblePciDeviceSupport;
  29. //
  30. // Configuration template for the CheckDevice() protocol member function.
  31. //
  32. // Refer to Table 20 "ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage" in
  33. // the Platform Init 1.4a Spec, Volume 5.
  34. //
  35. // This structure is interpreted by the UpdatePciInfo() function in the edk2
  36. // PCI Bus UEFI_DRIVER.
  37. //
  38. // This structure looks like:
  39. // AddressDesc-1 + AddressDesc-2 + ... + AddressDesc-n + EndDesc
  40. //
  41. STATIC CONST EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR mMmio64Configuration = {
  42. ACPI_ADDRESS_SPACE_DESCRIPTOR, // Desc
  43. (UINT16)( // Len
  44. sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) -
  45. OFFSET_OF (
  46. EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR,
  47. ResType
  48. )
  49. ),
  50. ACPI_ADDRESS_SPACE_TYPE_MEM, // ResType
  51. 0, // GenFlag
  52. 0, // SpecificFlag
  53. 64, // AddrSpaceGranularity:
  54. // aperture selection hint
  55. // for BAR allocation
  56. 0, // AddrRangeMin
  57. 0, // AddrRangeMax:
  58. // no special alignment
  59. // for affected BARs
  60. MAX_UINT64, // AddrTranslationOffset:
  61. // hint covers all
  62. // eligible BARs
  63. 0 // AddrLen:
  64. // use probed BAR size
  65. };
  66. //
  67. // mOptionRomConfiguration is present only in Td guest.
  68. // Host VMM can inject option ROM which is untrusted in Td guest,
  69. // so PCI option ROM needs to be ignored.
  70. // According to "Table 20. ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage"
  71. // PI spec 1.7, type-specific flags can be set to 0 when
  72. // Address Translation Offset == 6 to skip device option ROM.
  73. //
  74. STATIC CONST EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR mOptionRomConfiguration = {
  75. ACPI_ADDRESS_SPACE_DESCRIPTOR, // Desc
  76. (UINT16)( // Len
  77. sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) -
  78. OFFSET_OF (
  79. EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR,
  80. ResType
  81. )
  82. ),
  83. ACPI_ADDRESS_SPACE_TYPE_MEM, // ResType
  84. 0, // GenFlag
  85. 0, // Disable option roms SpecificFlag
  86. 64, // AddrSpaceGranularity:
  87. // aperture selection hint
  88. // for BAR allocation
  89. MAX_UINT64, // AddrRangeMin
  90. MAX_UINT64, // AddrRangeMax:
  91. // no special alignment
  92. // for affected BARs
  93. 6, // AddrTranslationOffset:
  94. // hint covers all
  95. // eligible BARs
  96. 0 // AddrLen:
  97. // use probed BAR size
  98. };
  99. STATIC CONST EFI_ACPI_END_TAG_DESCRIPTOR mEndDesc = {
  100. ACPI_END_TAG_DESCRIPTOR, // Desc
  101. 0 // Checksum: to be ignored
  102. };
  103. //
  104. // The CheckDevice() member function has been called.
  105. //
  106. STATIC BOOLEAN mCheckDeviceCalled;
  107. /**
  108. Notification callback for Legacy BIOS protocol installation.
  109. @param[in] Event Event whose notification function is being invoked.
  110. @param[in] Context The pointer to the notification function's context, which
  111. is implementation-dependent.
  112. **/
  113. STATIC
  114. VOID
  115. EFIAPI
  116. LegacyBiosInstalled (
  117. IN EFI_EVENT Event,
  118. IN VOID *Context
  119. )
  120. {
  121. EFI_STATUS Status;
  122. EFI_LEGACY_BIOS_PROTOCOL *LegacyBios;
  123. ASSERT (!mCheckDeviceCalled);
  124. Status = gBS->LocateProtocol (
  125. &gEfiLegacyBiosProtocolGuid,
  126. NULL /* Registration */,
  127. (VOID **)&LegacyBios
  128. );
  129. if (EFI_ERROR (Status)) {
  130. return;
  131. }
  132. mLegacyBiosInstalled = TRUE;
  133. //
  134. // Close the event and deregister this callback.
  135. //
  136. Status = gBS->CloseEvent (Event);
  137. ASSERT_EFI_ERROR (Status);
  138. }
  139. /**
  140. Returns a list of ACPI resource descriptors that detail the special resource
  141. configuration requirements for an incompatible PCI device.
  142. Prior to bus enumeration, the PCI bus driver will look for the presence of
  143. the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL. Only one instance of this
  144. protocol can be present in the system. For each PCI device that the PCI bus
  145. driver discovers, the PCI bus driver calls this function with the device's
  146. vendor ID, device ID, revision ID, subsystem vendor ID, and subsystem device
  147. ID. If the VendorId, DeviceId, RevisionId, SubsystemVendorId, or
  148. SubsystemDeviceId value is set to (UINTN)-1, that field will be ignored. The
  149. ID values that are not (UINTN)-1 will be used to identify the current device.
  150. This function will only return EFI_SUCCESS. However, if the device is an
  151. incompatible PCI device, a list of ACPI resource descriptors will be returned
  152. in Configuration. Otherwise, NULL will be returned in Configuration instead.
  153. The PCI bus driver does not need to allocate memory for Configuration.
  154. However, it is the PCI bus driver's responsibility to free it. The PCI bus
  155. driver then can configure this device with the information that is derived
  156. from this list of resource nodes, rather than the result of BAR probing.
  157. Only the following two resource descriptor types from the ACPI Specification
  158. may be used to describe the incompatible PCI device resource requirements:
  159. - QWORD Address Space Descriptor (ACPI 2.0, section 6.4.3.5.1; also ACPI 3.0)
  160. - End Tag (ACPI 2.0, section 6.4.2.8; also ACPI 3.0)
  161. The QWORD Address Space Descriptor can describe memory, I/O, and bus number
  162. ranges for dynamic or fixed resources. The configuration of a PCI root bridge
  163. is described with one or more QWORD Address Space Descriptors, followed by an
  164. End Tag. See the ACPI Specification for details on the field values.
  165. @param[in] This Pointer to the
  166. EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL
  167. instance.
  168. @param[in] VendorId A unique ID to identify the manufacturer of
  169. the PCI device. See the Conventional PCI
  170. Specification 3.0 for details.
  171. @param[in] DeviceId A unique ID to identify the particular PCI
  172. device. See the Conventional PCI
  173. Specification 3.0 for details.
  174. @param[in] RevisionId A PCI device-specific revision identifier.
  175. See the Conventional PCI Specification 3.0
  176. for details.
  177. @param[in] SubsystemVendorId Specifies the subsystem vendor ID. See the
  178. Conventional PCI Specification 3.0 for
  179. details.
  180. @param[in] SubsystemDeviceId Specifies the subsystem device ID. See the
  181. Conventional PCI Specification 3.0 for
  182. details.
  183. @param[out] Configuration A list of ACPI resource descriptors that
  184. detail the configuration requirement.
  185. @retval EFI_SUCCESS The function always returns EFI_SUCCESS.
  186. **/
  187. STATIC
  188. EFI_STATUS
  189. EFIAPI
  190. CheckDevice (
  191. IN EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *This,
  192. IN UINTN VendorId,
  193. IN UINTN DeviceId,
  194. IN UINTN RevisionId,
  195. IN UINTN SubsystemVendorId,
  196. IN UINTN SubsystemDeviceId,
  197. OUT VOID **Configuration
  198. )
  199. {
  200. mCheckDeviceCalled = TRUE;
  201. UINTN Length;
  202. UINT8 *Ptr;
  203. //
  204. // Unlike the general description of this protocol member suggests, there is
  205. // nothing incompatible about the PCI devices that we'll match here. We'll
  206. // match all PCI devices, and generate exactly one QWORD Address Space
  207. // Descriptor for each. That descriptor will instruct the PCI Bus UEFI_DRIVER
  208. // not to degrade 64-bit MMIO BARs for the device, even if a PCI option ROM
  209. // BAR is present on the device.
  210. //
  211. // The concern captured in the PCI Bus UEFI_DRIVER is that a legacy BIOS boot
  212. // (via a CSM) could dispatch a legacy option ROM on the device, which might
  213. // have trouble with MMIO BARs that have been allocated outside of the 32-bit
  214. // address space. But, if we don't support legacy option ROMs at all, then
  215. // this problem cannot arise.
  216. //
  217. if (mLegacyBiosInstalled) {
  218. //
  219. // Don't interfere with resource degradation.
  220. //
  221. *Configuration = NULL;
  222. return EFI_SUCCESS;
  223. }
  224. //
  225. // This member function is mis-specified actually: it is supposed to allocate
  226. // memory, but as specified, it could not return an error status. Thankfully,
  227. // the edk2 PCI Bus UEFI_DRIVER actually handles error codes; see the
  228. // UpdatePciInfo() function.
  229. //
  230. Length = sizeof mMmio64Configuration + sizeof mEndDesc;
  231. //
  232. // In Td guest OptionRom is not allowed.
  233. //
  234. if (CcProbe ()) {
  235. Length += sizeof mOptionRomConfiguration;
  236. }
  237. *Configuration = AllocateZeroPool (Length);
  238. if (*Configuration == NULL) {
  239. DEBUG ((
  240. DEBUG_WARN,
  241. "%a: 64-bit MMIO BARs may be degraded for PCI 0x%04x:0x%04x (rev %d)\n",
  242. __FUNCTION__,
  243. (UINT32)VendorId,
  244. (UINT32)DeviceId,
  245. (UINT8)RevisionId
  246. ));
  247. return EFI_OUT_OF_RESOURCES;
  248. }
  249. Ptr = (UINT8 *)(UINTN)*Configuration;
  250. CopyMem (Ptr, &mMmio64Configuration, sizeof mMmio64Configuration);
  251. Length = sizeof mMmio64Configuration;
  252. if (CcProbe ()) {
  253. CopyMem (Ptr + Length, &mOptionRomConfiguration, sizeof mOptionRomConfiguration);
  254. Length += sizeof mOptionRomConfiguration;
  255. }
  256. CopyMem (Ptr + Length, &mEndDesc, sizeof mEndDesc);
  257. return EFI_SUCCESS;
  258. }
  259. /**
  260. Entry point for this driver.
  261. @param[in] ImageHandle Image handle of this driver.
  262. @param[in] SystemTable Pointer to SystemTable.
  263. @retval EFI_SUCESS Driver has loaded successfully.
  264. @retval EFI_UNSUPPORTED PCI resource allocation has been disabled.
  265. @retval EFI_UNSUPPORTED There is no 64-bit PCI MMIO aperture.
  266. @return Error codes from lower level functions.
  267. **/
  268. EFI_STATUS
  269. EFIAPI
  270. DriverInitialize (
  271. IN EFI_HANDLE ImageHandle,
  272. IN EFI_SYSTEM_TABLE *SystemTable
  273. )
  274. {
  275. EFI_STATUS Status;
  276. EFI_EVENT Event;
  277. VOID *Registration;
  278. //
  279. // If there is no 64-bit PCI MMIO aperture, then 64-bit MMIO BARs have to be
  280. // allocated under 4 GB unconditionally.
  281. //
  282. if (PcdGet64 (PcdPciMmio64Size) == 0) {
  283. return EFI_UNSUPPORTED;
  284. }
  285. //
  286. // Otherwise, create a protocol notify to see if a CSM is present. (With the
  287. // CSM absent, the PCI Bus driver won't have to worry about allocating 64-bit
  288. // MMIO BARs in the 32-bit MMIO aperture, for the sake of a legacy BIOS.)
  289. //
  290. // If the Legacy BIOS Protocol is present at the time of this driver starting
  291. // up, we can mark immediately that the PCI Bus driver should perform the
  292. // usual 64-bit MMIO BAR degradation.
  293. //
  294. // Otherwise, if the Legacy BIOS Protocol is absent at startup, it may be
  295. // installed later. However, if it doesn't show up until the first
  296. // EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL.CheckDevice() call from the
  297. // PCI Bus driver, then it never will:
  298. //
  299. // 1. The following drivers are dispatched in some unspecified order:
  300. // - PCI Host Bridge DXE_DRIVER,
  301. // - PCI Bus UEFI_DRIVER,
  302. // - this DXE_DRIVER,
  303. // - Legacy BIOS DXE_DRIVER.
  304. //
  305. // 2. The DXE_CORE enters BDS.
  306. //
  307. // 3. The platform BDS connects the PCI Root Bridge IO instances (produced by
  308. // the PCI Host Bridge DXE_DRIVER).
  309. //
  310. // 4. The PCI Bus UEFI_DRIVER enumerates resources and calls into this
  311. // DXE_DRIVER (CheckDevice()).
  312. //
  313. // 5. This driver remembers if EFI_LEGACY_BIOS_PROTOCOL has been installed
  314. // sometime during step 1 (produced by the Legacy BIOS DXE_DRIVER).
  315. //
  316. // For breaking this order, the Legacy BIOS DXE_DRIVER would have to install
  317. // its protocol after the firmware enters BDS, which cannot happen.
  318. //
  319. Status = gBS->CreateEvent (
  320. EVT_NOTIFY_SIGNAL,
  321. TPL_CALLBACK,
  322. LegacyBiosInstalled,
  323. NULL /* Context */,
  324. &Event
  325. );
  326. if (EFI_ERROR (Status)) {
  327. return Status;
  328. }
  329. Status = gBS->RegisterProtocolNotify (
  330. &gEfiLegacyBiosProtocolGuid,
  331. Event,
  332. &Registration
  333. );
  334. if (EFI_ERROR (Status)) {
  335. goto CloseEvent;
  336. }
  337. Status = gBS->SignalEvent (Event);
  338. ASSERT_EFI_ERROR (Status);
  339. mIncompatiblePciDeviceSupport.CheckDevice = CheckDevice;
  340. Status = gBS->InstallMultipleProtocolInterfaces (
  341. &ImageHandle,
  342. &gEfiIncompatiblePciDeviceSupportProtocolGuid,
  343. &mIncompatiblePciDeviceSupport,
  344. NULL
  345. );
  346. if (EFI_ERROR (Status)) {
  347. goto CloseEvent;
  348. }
  349. return EFI_SUCCESS;
  350. CloseEvent:
  351. if (!mLegacyBiosInstalled) {
  352. EFI_STATUS CloseStatus;
  353. CloseStatus = gBS->CloseEvent (Event);
  354. ASSERT_EFI_ERROR (CloseStatus);
  355. }
  356. return Status;
  357. }