ArmNameSpaceObjects.h 41 KB

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  1. /** @file
  2. Copyright (c) 2017 - 2022, Arm Limited. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. @par Glossary:
  5. - Cm or CM - Configuration Manager
  6. - Obj or OBJ - Object
  7. - Std or STD - Standard
  8. **/
  9. #ifndef ARM_NAMESPACE_OBJECTS_H_
  10. #define ARM_NAMESPACE_OBJECTS_H_
  11. #include <AmlCpcInfo.h>
  12. #include <StandardNameSpaceObjects.h>
  13. #pragma pack(1)
  14. /** The EARM_OBJECT_ID enum describes the Object IDs
  15. in the ARM Namespace
  16. */
  17. typedef enum ArmObjectID {
  18. EArmObjReserved, ///< 0 - Reserved
  19. EArmObjBootArchInfo, ///< 1 - Boot Architecture Info
  20. EArmObjCpuInfo, ///< 2 - CPU Info
  21. EArmObjPowerManagementProfileInfo, ///< 3 - Power Management Profile Info
  22. EArmObjGicCInfo, ///< 4 - GIC CPU Interface Info
  23. EArmObjGicDInfo, ///< 5 - GIC Distributor Info
  24. EArmObjGicMsiFrameInfo, ///< 6 - GIC MSI Frame Info
  25. EArmObjGicRedistributorInfo, ///< 7 - GIC Redistributor Info
  26. EArmObjGicItsInfo, ///< 8 - GIC ITS Info
  27. EArmObjSerialConsolePortInfo, ///< 9 - Serial Console Port Info
  28. EArmObjSerialDebugPortInfo, ///< 10 - Serial Debug Port Info
  29. EArmObjGenericTimerInfo, ///< 11 - Generic Timer Info
  30. EArmObjPlatformGTBlockInfo, ///< 12 - Platform GT Block Info
  31. EArmObjGTBlockTimerFrameInfo, ///< 13 - Generic Timer Block Frame Info
  32. EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog
  33. EArmObjPciConfigSpaceInfo, ///< 15 - PCI Configuration Space Info
  34. EArmObjHypervisorVendorIdentity, ///< 16 - Hypervisor Vendor Id
  35. EArmObjFixedFeatureFlags, ///< 17 - Fixed feature flags for FADT
  36. EArmObjItsGroup, ///< 18 - ITS Group
  37. EArmObjNamedComponent, ///< 19 - Named Component
  38. EArmObjRootComplex, ///< 20 - Root Complex
  39. EArmObjSmmuV1SmmuV2, ///< 21 - SMMUv1 or SMMUv2
  40. EArmObjSmmuV3, ///< 22 - SMMUv3
  41. EArmObjPmcg, ///< 23 - PMCG
  42. EArmObjGicItsIdentifierArray, ///< 24 - GIC ITS Identifier Array
  43. EArmObjIdMappingArray, ///< 25 - ID Mapping Array
  44. EArmObjSmmuInterruptArray, ///< 26 - SMMU Interrupt Array
  45. EArmObjProcHierarchyInfo, ///< 27 - Processor Hierarchy Info
  46. EArmObjCacheInfo, ///< 28 - Cache Info
  47. EArmObjReserved29, ///< 29 - Reserved
  48. EArmObjCmRef, ///< 30 - CM Object Reference
  49. EArmObjMemoryAffinityInfo, ///< 31 - Memory Affinity Info
  50. EArmObjDeviceHandleAcpi, ///< 32 - Device Handle Acpi
  51. EArmObjDeviceHandlePci, ///< 33 - Device Handle Pci
  52. EArmObjGenericInitiatorAffinityInfo, ///< 34 - Generic Initiator Affinity
  53. EArmObjSerialPortInfo, ///< 35 - Generic Serial Port Info
  54. EArmObjCmn600Info, ///< 36 - CMN-600 Info
  55. EArmObjLpiInfo, ///< 37 - Lpi Info
  56. EArmObjPciAddressMapInfo, ///< 38 - Pci Address Map Info
  57. EArmObjPciInterruptMapInfo, ///< 39 - Pci Interrupt Map Info
  58. EArmObjRmr, ///< 40 - Reserved Memory Range Node
  59. EArmObjMemoryRangeDescriptor, ///< 41 - Memory Range Descriptor
  60. EArmObjCpcInfo, ///< 42 - Continuous Performance Control Info
  61. EArmObjPccSubspaceType0Info, ///< 43 - Pcc Subspace Type 0 Info
  62. EArmObjPccSubspaceType1Info, ///< 44 - Pcc Subspace Type 2 Info
  63. EArmObjPccSubspaceType2Info, ///< 45 - Pcc Subspace Type 2 Info
  64. EArmObjPccSubspaceType3Info, ///< 46 - Pcc Subspace Type 3 Info
  65. EArmObjPccSubspaceType4Info, ///< 47 - Pcc Subspace Type 4 Info
  66. EArmObjPccSubspaceType5Info, ///< 48 - Pcc Subspace Type 5 Info
  67. EArmObjMax
  68. } EARM_OBJECT_ID;
  69. /** A structure that describes the
  70. ARM Boot Architecture flags.
  71. ID: EArmObjBootArchInfo
  72. */
  73. typedef struct CmArmBootArchInfo {
  74. /** This is the ARM_BOOT_ARCH flags field of the FADT Table
  75. described in the ACPI Table Specification.
  76. */
  77. UINT16 BootArchFlags;
  78. } CM_ARM_BOOT_ARCH_INFO;
  79. /** A structure that describes the
  80. Power Management Profile Information for the Platform.
  81. ID: EArmObjPowerManagementProfileInfo
  82. */
  83. typedef struct CmArmPowerManagementProfileInfo {
  84. /** This is the Preferred_PM_Profile field of the FADT Table
  85. described in the ACPI Specification
  86. */
  87. UINT8 PowerManagementProfile;
  88. } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;
  89. /** A structure that describes the
  90. GIC CPU Interface for the Platform.
  91. ID: EArmObjGicCInfo
  92. */
  93. typedef struct CmArmGicCInfo {
  94. /// The GIC CPU Interface number.
  95. UINT32 CPUInterfaceNumber;
  96. /** The ACPI Processor UID. This must match the
  97. _UID of the CPU Device object information described
  98. in the DSDT/SSDT for the CPU.
  99. */
  100. UINT32 AcpiProcessorUid;
  101. /** The flags field as described by the GICC structure
  102. in the ACPI Specification.
  103. */
  104. UINT32 Flags;
  105. /** The parking protocol version field as described by
  106. the GICC structure in the ACPI Specification.
  107. */
  108. UINT32 ParkingProtocolVersion;
  109. /** The Performance Interrupt field as described by
  110. the GICC structure in the ACPI Specification.
  111. */
  112. UINT32 PerformanceInterruptGsiv;
  113. /** The CPU Parked address field as described by
  114. the GICC structure in the ACPI Specification.
  115. */
  116. UINT64 ParkedAddress;
  117. /** The base address for the GIC CPU Interface
  118. as described by the GICC structure in the
  119. ACPI Specification.
  120. */
  121. UINT64 PhysicalBaseAddress;
  122. /** The base address for GICV interface
  123. as described by the GICC structure in the
  124. ACPI Specification.
  125. */
  126. UINT64 GICV;
  127. /** The base address for GICH interface
  128. as described by the GICC structure in the
  129. ACPI Specification.
  130. */
  131. UINT64 GICH;
  132. /** The GICV maintenance interrupt
  133. as described by the GICC structure in the
  134. ACPI Specification.
  135. */
  136. UINT32 VGICMaintenanceInterrupt;
  137. /** The base address for GICR interface
  138. as described by the GICC structure in the
  139. ACPI Specification.
  140. */
  141. UINT64 GICRBaseAddress;
  142. /** The MPIDR for the CPU
  143. as described by the GICC structure in the
  144. ACPI Specification.
  145. */
  146. UINT64 MPIDR;
  147. /** The Processor Power Efficiency class
  148. as described by the GICC structure in the
  149. ACPI Specification.
  150. */
  151. UINT8 ProcessorPowerEfficiencyClass;
  152. /** Statistical Profiling Extension buffer overflow GSIV. Zero if
  153. unsupported by this processor. This field was introduced in
  154. ACPI 6.3 (MADT revision 5) and is therefore ignored when
  155. generating MADT revision 4 or lower.
  156. */
  157. UINT16 SpeOverflowInterrupt;
  158. /** The proximity domain to which the logical processor belongs.
  159. This field is used to populate the GICC affinity structure
  160. in the SRAT table.
  161. */
  162. UINT32 ProximityDomain;
  163. /** The clock domain to which the logical processor belongs.
  164. This field is used to populate the GICC affinity structure
  165. in the SRAT table.
  166. */
  167. UINT32 ClockDomain;
  168. /** The GICC Affinity flags field as described by the GICC Affinity structure
  169. in the SRAT table.
  170. */
  171. UINT32 AffinityFlags;
  172. /** Optional field: Reference Token for the Cpc info of this processor.
  173. i.e. a token referencing a CM_ARM_CPC_INFO object.
  174. */
  175. CM_OBJECT_TOKEN CpcToken;
  176. } CM_ARM_GICC_INFO;
  177. /** A structure that describes the
  178. GIC Distributor information for the Platform.
  179. ID: EArmObjGicDInfo
  180. */
  181. typedef struct CmArmGicDInfo {
  182. /// The Physical Base address for the GIC Distributor.
  183. UINT64 PhysicalBaseAddress;
  184. /** The global system interrupt
  185. number where this GIC Distributor's
  186. interrupt inputs start.
  187. */
  188. UINT32 SystemVectorBase;
  189. /** The GIC version as described
  190. by the GICD structure in the
  191. ACPI Specification.
  192. */
  193. UINT8 GicVersion;
  194. } CM_ARM_GICD_INFO;
  195. /** A structure that describes the
  196. GIC MSI Frame information for the Platform.
  197. ID: EArmObjGicMsiFrameInfo
  198. */
  199. typedef struct CmArmGicMsiFrameInfo {
  200. /// The GIC MSI Frame ID
  201. UINT32 GicMsiFrameId;
  202. /// The Physical base address for the MSI Frame
  203. UINT64 PhysicalBaseAddress;
  204. /** The GIC MSI Frame flags
  205. as described by the GIC MSI frame
  206. structure in the ACPI Specification.
  207. */
  208. UINT32 Flags;
  209. /// SPI Count used by this frame
  210. UINT16 SPICount;
  211. /// SPI Base used by this frame
  212. UINT16 SPIBase;
  213. } CM_ARM_GIC_MSI_FRAME_INFO;
  214. /** A structure that describes the
  215. GIC Redistributor information for the Platform.
  216. ID: EArmObjGicRedistributorInfo
  217. */
  218. typedef struct CmArmGicRedistInfo {
  219. /** The physical address of a page range
  220. containing all GIC Redistributors.
  221. */
  222. UINT64 DiscoveryRangeBaseAddress;
  223. /// Length of the GIC Redistributor Discovery page range
  224. UINT32 DiscoveryRangeLength;
  225. } CM_ARM_GIC_REDIST_INFO;
  226. /** A structure that describes the
  227. GIC Interrupt Translation Service information for the Platform.
  228. ID: EArmObjGicItsInfo
  229. */
  230. typedef struct CmArmGicItsInfo {
  231. /// The GIC ITS ID
  232. UINT32 GicItsId;
  233. /// The physical address for the Interrupt Translation Service
  234. UINT64 PhysicalBaseAddress;
  235. /** The proximity domain to which the logical processor belongs.
  236. This field is used to populate the GIC ITS affinity structure
  237. in the SRAT table.
  238. */
  239. UINT32 ProximityDomain;
  240. } CM_ARM_GIC_ITS_INFO;
  241. /** A structure that describes the
  242. Serial Port information for the Platform.
  243. ID: EArmObjSerialConsolePortInfo or
  244. EArmObjSerialDebugPortInfo or
  245. EArmObjSerialPortInfo
  246. */
  247. typedef struct CmArmSerialPortInfo {
  248. /// The physical base address for the serial port
  249. UINT64 BaseAddress;
  250. /// The serial port interrupt
  251. UINT32 Interrupt;
  252. /// The serial port baud rate
  253. UINT64 BaudRate;
  254. /// The serial port clock
  255. UINT32 Clock;
  256. /// Serial Port subtype
  257. UINT16 PortSubtype;
  258. /// The Base address length
  259. UINT64 BaseAddressLength;
  260. /// The access size
  261. UINT8 AccessSize;
  262. } CM_ARM_SERIAL_PORT_INFO;
  263. /** A structure that describes the
  264. Generic Timer information for the Platform.
  265. ID: EArmObjGenericTimerInfo
  266. */
  267. typedef struct CmArmGenericTimerInfo {
  268. /// The physical base address for the counter control frame
  269. UINT64 CounterControlBaseAddress;
  270. /// The physical base address for the counter read frame
  271. UINT64 CounterReadBaseAddress;
  272. /// The secure PL1 timer interrupt
  273. UINT32 SecurePL1TimerGSIV;
  274. /// The secure PL1 timer flags
  275. UINT32 SecurePL1TimerFlags;
  276. /// The non-secure PL1 timer interrupt
  277. UINT32 NonSecurePL1TimerGSIV;
  278. /// The non-secure PL1 timer flags
  279. UINT32 NonSecurePL1TimerFlags;
  280. /// The virtual timer interrupt
  281. UINT32 VirtualTimerGSIV;
  282. /// The virtual timer flags
  283. UINT32 VirtualTimerFlags;
  284. /// The non-secure PL2 timer interrupt
  285. UINT32 NonSecurePL2TimerGSIV;
  286. /// The non-secure PL2 timer flags
  287. UINT32 NonSecurePL2TimerFlags;
  288. /// GSIV for the virtual EL2 timer
  289. UINT32 VirtualPL2TimerGSIV;
  290. /// Flags for the virtual EL2 timer
  291. UINT32 VirtualPL2TimerFlags;
  292. } CM_ARM_GENERIC_TIMER_INFO;
  293. /** A structure that describes the
  294. Platform Generic Block Timer information for the Platform.
  295. ID: EArmObjPlatformGTBlockInfo
  296. */
  297. typedef struct CmArmGTBlockInfo {
  298. /// The physical base address for the GT Block Timer structure
  299. UINT64 GTBlockPhysicalAddress;
  300. /// The number of timer frames implemented in the GT Block
  301. UINT32 GTBlockTimerFrameCount;
  302. /// Reference token for the GT Block timer frame list
  303. CM_OBJECT_TOKEN GTBlockTimerFrameToken;
  304. } CM_ARM_GTBLOCK_INFO;
  305. /** A structure that describes the
  306. Platform Generic Block Timer Frame information for the Platform.
  307. ID: EArmObjGTBlockTimerFrameInfo
  308. */
  309. typedef struct CmArmGTBlockTimerFrameInfo {
  310. /// The Generic Timer frame number
  311. UINT8 FrameNumber;
  312. /// The physical base address for the CntBase block
  313. UINT64 PhysicalAddressCntBase;
  314. /// The physical base address for the CntEL0Base block
  315. UINT64 PhysicalAddressCntEL0Base;
  316. /// The physical timer interrupt
  317. UINT32 PhysicalTimerGSIV;
  318. /** The physical timer flags as described by the GT Block
  319. Timer frame Structure in the ACPI Specification.
  320. */
  321. UINT32 PhysicalTimerFlags;
  322. /// The virtual timer interrupt
  323. UINT32 VirtualTimerGSIV;
  324. /** The virtual timer flags as described by the GT Block
  325. Timer frame Structure in the ACPI Specification.
  326. */
  327. UINT32 VirtualTimerFlags;
  328. /** The common timer flags as described by the GT Block
  329. Timer frame Structure in the ACPI Specification.
  330. */
  331. UINT32 CommonFlags;
  332. } CM_ARM_GTBLOCK_TIMER_FRAME_INFO;
  333. /** A structure that describes the
  334. Arm Generic Watchdog information for the Platform.
  335. ID: EArmObjPlatformGenericWatchdogInfo
  336. */
  337. typedef struct CmArmGenericWatchdogInfo {
  338. /// The physical base address of the Arm Watchdog control frame
  339. UINT64 ControlFrameAddress;
  340. /// The physical base address of the Arm Watchdog refresh frame
  341. UINT64 RefreshFrameAddress;
  342. /// The watchdog interrupt
  343. UINT32 TimerGSIV;
  344. /** The flags for the watchdog as described by the Arm watchdog
  345. structure in the ACPI specification.
  346. */
  347. UINT32 Flags;
  348. } CM_ARM_GENERIC_WATCHDOG_INFO;
  349. /** A structure that describes the
  350. PCI Configuration Space information for the Platform.
  351. ID: EArmObjPciConfigSpaceInfo
  352. */
  353. typedef struct CmArmPciConfigSpaceInfo {
  354. /// The physical base address for the PCI segment
  355. UINT64 BaseAddress;
  356. /// The PCI segment group number
  357. UINT16 PciSegmentGroupNumber;
  358. /// The start bus number
  359. UINT8 StartBusNumber;
  360. /// The end bus number
  361. UINT8 EndBusNumber;
  362. /// Optional field: Reference Token for address mapping.
  363. /// Token identifying a CM_ARM_OBJ_REF structure.
  364. CM_OBJECT_TOKEN AddressMapToken;
  365. /// Optional field: Reference Token for interrupt mapping.
  366. /// Token identifying a CM_ARM_OBJ_REF structure.
  367. CM_OBJECT_TOKEN InterruptMapToken;
  368. } CM_ARM_PCI_CONFIG_SPACE_INFO;
  369. /** A structure that describes the
  370. Hypervisor Vendor ID information for the Platform.
  371. ID: EArmObjHypervisorVendorIdentity
  372. */
  373. typedef struct CmArmHypervisorVendorId {
  374. /// The hypervisor Vendor ID
  375. UINT64 HypervisorVendorId;
  376. } CM_ARM_HYPERVISOR_VENDOR_ID;
  377. /** A structure that describes the
  378. Fixed feature flags for the Platform.
  379. ID: EArmObjFixedFeatureFlags
  380. */
  381. typedef struct CmArmFixedFeatureFlags {
  382. /// The Fixed feature flags
  383. UINT32 Flags;
  384. } CM_ARM_FIXED_FEATURE_FLAGS;
  385. /** A structure that describes the
  386. ITS Group node for the Platform.
  387. ID: EArmObjItsGroup
  388. */
  389. typedef struct CmArmItsGroupNode {
  390. /// An unique token used to identify this object
  391. CM_OBJECT_TOKEN Token;
  392. /// The number of ITS identifiers in the ITS node
  393. UINT32 ItsIdCount;
  394. /// Reference token for the ITS identifier array
  395. CM_OBJECT_TOKEN ItsIdToken;
  396. /// Unique identifier for this node.
  397. UINT32 Identifier;
  398. } CM_ARM_ITS_GROUP_NODE;
  399. /** A structure that describes the
  400. Named component node for the Platform.
  401. ID: EArmObjNamedComponent
  402. */
  403. typedef struct CmArmNamedComponentNode {
  404. /// An unique token used to identify this object
  405. CM_OBJECT_TOKEN Token;
  406. /// Number of ID mappings
  407. UINT32 IdMappingCount;
  408. /// Reference token for the ID mapping array
  409. CM_OBJECT_TOKEN IdMappingToken;
  410. /// Flags for the named component
  411. UINT32 Flags;
  412. /// Memory access properties : Cache coherent attributes
  413. UINT32 CacheCoherent;
  414. /// Memory access properties : Allocation hints
  415. UINT8 AllocationHints;
  416. /// Memory access properties : Memory access flags
  417. UINT8 MemoryAccessFlags;
  418. /// Memory access properties : Address size limit
  419. UINT8 AddressSizeLimit;
  420. /** ASCII Null terminated string with the full path to
  421. the entry in the namespace for this object.
  422. */
  423. CHAR8 *ObjectName;
  424. /// Unique identifier for this node.
  425. UINT32 Identifier;
  426. } CM_ARM_NAMED_COMPONENT_NODE;
  427. /** A structure that describes the
  428. Root complex node for the Platform.
  429. ID: EArmObjRootComplex
  430. */
  431. typedef struct CmArmRootComplexNode {
  432. /// An unique token used to identify this object
  433. CM_OBJECT_TOKEN Token;
  434. /// Number of ID mappings
  435. UINT32 IdMappingCount;
  436. /// Reference token for the ID mapping array
  437. CM_OBJECT_TOKEN IdMappingToken;
  438. /// Memory access properties : Cache coherent attributes
  439. UINT32 CacheCoherent;
  440. /// Memory access properties : Allocation hints
  441. UINT8 AllocationHints;
  442. /// Memory access properties : Memory access flags
  443. UINT8 MemoryAccessFlags;
  444. /// ATS attributes
  445. UINT32 AtsAttribute;
  446. /// PCI segment number
  447. UINT32 PciSegmentNumber;
  448. /// Memory address size limit
  449. UINT8 MemoryAddressSize;
  450. /// PASID capabilities
  451. UINT16 PasidCapabilities;
  452. /// Flags
  453. UINT32 Flags;
  454. /// Unique identifier for this node.
  455. UINT32 Identifier;
  456. } CM_ARM_ROOT_COMPLEX_NODE;
  457. /** A structure that describes the
  458. SMMUv1 or SMMUv2 node for the Platform.
  459. ID: EArmObjSmmuV1SmmuV2
  460. */
  461. typedef struct CmArmSmmuV1SmmuV2Node {
  462. /// An unique token used to identify this object
  463. CM_OBJECT_TOKEN Token;
  464. /// Number of ID mappings
  465. UINT32 IdMappingCount;
  466. /// Reference token for the ID mapping array
  467. CM_OBJECT_TOKEN IdMappingToken;
  468. /// SMMU Base Address
  469. UINT64 BaseAddress;
  470. /// Length of the memory range covered by the SMMU
  471. UINT64 Span;
  472. /// SMMU Model
  473. UINT32 Model;
  474. /// SMMU flags
  475. UINT32 Flags;
  476. /// Number of context interrupts
  477. UINT32 ContextInterruptCount;
  478. /// Reference token for the context interrupt array
  479. CM_OBJECT_TOKEN ContextInterruptToken;
  480. /// Number of PMU interrupts
  481. UINT32 PmuInterruptCount;
  482. /// Reference token for the PMU interrupt array
  483. CM_OBJECT_TOKEN PmuInterruptToken;
  484. /// GSIV of the SMMU_NSgIrpt interrupt
  485. UINT32 SMMU_NSgIrpt;
  486. /// SMMU_NSgIrpt interrupt flags
  487. UINT32 SMMU_NSgIrptFlags;
  488. /// GSIV of the SMMU_NSgCfgIrpt interrupt
  489. UINT32 SMMU_NSgCfgIrpt;
  490. /// SMMU_NSgCfgIrpt interrupt flags
  491. UINT32 SMMU_NSgCfgIrptFlags;
  492. /// Unique identifier for this node.
  493. UINT32 Identifier;
  494. } CM_ARM_SMMUV1_SMMUV2_NODE;
  495. /** A structure that describes the
  496. SMMUv3 node for the Platform.
  497. ID: EArmObjSmmuV3
  498. */
  499. typedef struct CmArmSmmuV3Node {
  500. /// An unique token used to identify this object
  501. CM_OBJECT_TOKEN Token;
  502. /// Number of ID mappings
  503. UINT32 IdMappingCount;
  504. /// Reference token for the ID mapping array
  505. CM_OBJECT_TOKEN IdMappingToken;
  506. /// SMMU Base Address
  507. UINT64 BaseAddress;
  508. /// SMMU flags
  509. UINT32 Flags;
  510. /// VATOS address
  511. UINT64 VatosAddress;
  512. /// Model
  513. UINT32 Model;
  514. /// GSIV of the Event interrupt if SPI based
  515. UINT32 EventInterrupt;
  516. /// PRI Interrupt if SPI based
  517. UINT32 PriInterrupt;
  518. /// GERR interrupt if GSIV based
  519. UINT32 GerrInterrupt;
  520. /// Sync interrupt if GSIV based
  521. UINT32 SyncInterrupt;
  522. /// Proximity domain flag
  523. UINT32 ProximityDomain;
  524. /// Index into the array of ID mapping
  525. UINT32 DeviceIdMappingIndex;
  526. /// Unique identifier for this node.
  527. UINT32 Identifier;
  528. } CM_ARM_SMMUV3_NODE;
  529. /** A structure that describes the
  530. PMCG node for the Platform.
  531. ID: EArmObjPmcg
  532. */
  533. typedef struct CmArmPmcgNode {
  534. /// An unique token used to identify this object
  535. CM_OBJECT_TOKEN Token;
  536. /// Number of ID mappings
  537. UINT32 IdMappingCount;
  538. /// Reference token for the ID mapping array
  539. CM_OBJECT_TOKEN IdMappingToken;
  540. /// Base Address for performance monitor counter group
  541. UINT64 BaseAddress;
  542. /// GSIV for the Overflow interrupt
  543. UINT32 OverflowInterrupt;
  544. /// Page 1 Base address
  545. UINT64 Page1BaseAddress;
  546. /// Reference token for the IORT node associated with this node
  547. CM_OBJECT_TOKEN ReferenceToken;
  548. /// Unique identifier for this node.
  549. UINT32 Identifier;
  550. } CM_ARM_PMCG_NODE;
  551. /** A structure that describes the
  552. GIC ITS Identifiers for an ITS Group node.
  553. ID: EArmObjGicItsIdentifierArray
  554. */
  555. typedef struct CmArmGicItsIdentifier {
  556. /// The ITS Identifier
  557. UINT32 ItsId;
  558. } CM_ARM_ITS_IDENTIFIER;
  559. /** A structure that describes the
  560. ID Mappings for the Platform.
  561. ID: EArmObjIdMappingArray
  562. */
  563. typedef struct CmArmIdMapping {
  564. /// Input base
  565. UINT32 InputBase;
  566. /// Number of input IDs
  567. UINT32 NumIds;
  568. /// Output Base
  569. UINT32 OutputBase;
  570. /// Reference token for the output node
  571. CM_OBJECT_TOKEN OutputReferenceToken;
  572. /// Flags
  573. UINT32 Flags;
  574. } CM_ARM_ID_MAPPING;
  575. /** A structure that describes the Arm
  576. Generic Interrupts.
  577. */
  578. typedef struct CmArmGenericInterrupt {
  579. /// Interrupt number
  580. UINT32 Interrupt;
  581. /// Flags
  582. /// BIT0: 0: Interrupt is Level triggered
  583. /// 1: Interrupt is Edge triggered
  584. /// BIT1: 0: Interrupt is Active high
  585. /// 1: Interrupt is Active low
  586. UINT32 Flags;
  587. } CM_ARM_GENERIC_INTERRUPT;
  588. /** A structure that describes the SMMU interrupts for the Platform.
  589. Interrupt Interrupt number.
  590. Flags Interrupt flags as defined for SMMU node.
  591. ID: EArmObjSmmuInterruptArray
  592. */
  593. typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_SMMU_INTERRUPT;
  594. /** A structure that describes the AML Extended Interrupts.
  595. Interrupt Interrupt number.
  596. Flags Interrupt flags as defined by the Interrupt
  597. Vector Flags (Byte 3) of the Extended Interrupt
  598. resource descriptor.
  599. See EFI_ACPI_EXTENDED_INTERRUPT_FLAG_xxx in Acpi10.h
  600. */
  601. typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_EXTENDED_INTERRUPT;
  602. /** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT
  603. ID: EArmObjProcHierarchyInfo
  604. */
  605. typedef struct CmArmProcHierarchyInfo {
  606. /// A unique token used to identify this object
  607. CM_OBJECT_TOKEN Token;
  608. /// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)
  609. UINT32 Flags;
  610. /// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor
  611. /// topology. A value of CM_NULL_TOKEN means this node has no parent.
  612. CM_OBJECT_TOKEN ParentToken;
  613. /// Token of the associated CM_ARM_GICC_INFO object which has the
  614. /// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this
  615. /// node represents a group of associated processors and it does not have an
  616. /// associated GIC CPU interface.
  617. CM_OBJECT_TOKEN GicCToken;
  618. /// Number of resources private to this Node
  619. UINT32 NoOfPrivateResources;
  620. /// Token of the array which contains references to the resources private to
  621. /// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if
  622. /// the NoOfPrivateResources is 0, in which case it is recommended to set
  623. /// this field to CM_NULL_TOKEN.
  624. CM_OBJECT_TOKEN PrivateResourcesArrayToken;
  625. /// Optional field: Reference Token for the Lpi state of this processor.
  626. /// Token identifying a CM_ARM_OBJ_REF structure, itself referencing
  627. /// CM_ARM_LPI_INFO objects.
  628. CM_OBJECT_TOKEN LpiToken;
  629. /// Set to TRUE if UID should override index for name and _UID
  630. /// for processor container nodes and name of processors.
  631. /// This should be consistently set for containers or processors to avoid
  632. /// duplicate values
  633. BOOLEAN OverrideNameUidEnabled;
  634. /// If OverrideNameUidEnabled is TRUE then this value will be used for name of
  635. /// processors and processor containers.
  636. UINT16 OverrideName;
  637. /// If OverrideNameUidEnabled is TRUE then this value will be used for
  638. /// the UID of processor containers.
  639. UINT32 OverrideUid;
  640. } CM_ARM_PROC_HIERARCHY_INFO;
  641. /** A structure that describes the Cache Type Structure (Type 1) in PPTT
  642. ID: EArmObjCacheInfo
  643. */
  644. typedef struct CmArmCacheInfo {
  645. /// A unique token used to identify this object
  646. CM_OBJECT_TOKEN Token;
  647. /// Reference token for the next level of cache that is private to the same
  648. /// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this
  649. /// entry represents the last cache level appropriate to the processor
  650. /// hierarchy node structures using this entry.
  651. CM_OBJECT_TOKEN NextLevelOfCacheToken;
  652. /// Size of the cache in bytes
  653. UINT32 Size;
  654. /// Number of sets in the cache
  655. UINT32 NumberOfSets;
  656. /// Integer number of ways. The maximum associativity supported by
  657. /// ACPI Cache type structure is limited to MAX_UINT8. However,
  658. /// the maximum number of ways supported by the architecture is
  659. /// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field
  660. /// is 32-bit wide.
  661. UINT32 Associativity;
  662. /// Cache attributes (ACPI 6.4 - January 2021, PPTT, Table 5.140)
  663. UINT8 Attributes;
  664. /// Line size in bytes
  665. UINT16 LineSize;
  666. /// Unique ID for the cache
  667. UINT32 CacheId;
  668. } CM_ARM_CACHE_INFO;
  669. /** A structure that describes a reference to another Configuration Manager
  670. object.
  671. This is useful for creating an array of reference tokens. The framework
  672. can then query the configuration manager for these arrays using the
  673. object ID EArmObjCmRef.
  674. This can be used is to represent one-to-many relationships between objects.
  675. ID: EArmObjCmRef
  676. */
  677. typedef struct CmArmObjRef {
  678. /// Token of the CM object being referenced
  679. CM_OBJECT_TOKEN ReferenceToken;
  680. } CM_ARM_OBJ_REF;
  681. /** A structure that describes the Memory Affinity Structure (Type 1) in SRAT
  682. ID: EArmObjMemoryAffinityInfo
  683. */
  684. typedef struct CmArmMemoryAffinityInfo {
  685. /// The proximity domain to which the "range of memory" belongs.
  686. UINT32 ProximityDomain;
  687. /// Base Address
  688. UINT64 BaseAddress;
  689. /// Length
  690. UINT64 Length;
  691. /// Flags
  692. UINT32 Flags;
  693. } CM_ARM_MEMORY_AFFINITY_INFO;
  694. /** A structure that describes the ACPI Device Handle (Type 0) in the
  695. Generic Initiator Affinity structure in SRAT
  696. ID: EArmObjDeviceHandleAcpi
  697. */
  698. typedef struct CmArmDeviceHandleAcpi {
  699. /// Hardware ID
  700. UINT64 Hid;
  701. /// Unique Id
  702. UINT32 Uid;
  703. } CM_ARM_DEVICE_HANDLE_ACPI;
  704. /** A structure that describes the PCI Device Handle (Type 1) in the
  705. Generic Initiator Affinity structure in SRAT
  706. ID: EArmObjDeviceHandlePci
  707. */
  708. typedef struct CmArmDeviceHandlePci {
  709. /// PCI Segment Number
  710. UINT16 SegmentNumber;
  711. /// PCI Bus Number - Max 256 busses (Bits 15:8 of BDF)
  712. UINT8 BusNumber;
  713. /// PCI Device Number - Max 32 devices (Bits 7:3 of BDF)
  714. UINT8 DeviceNumber;
  715. /// PCI Function Number - Max 8 functions (Bits 2:0 of BDF)
  716. UINT8 FunctionNumber;
  717. } CM_ARM_DEVICE_HANDLE_PCI;
  718. /** A structure that describes the Generic Initiator Affinity structure in SRAT
  719. ID: EArmObjGenericInitiatorAffinityInfo
  720. */
  721. typedef struct CmArmGenericInitiatorAffinityInfo {
  722. /// The proximity domain to which the generic initiator belongs.
  723. UINT32 ProximityDomain;
  724. /// Flags
  725. UINT32 Flags;
  726. /// Device Handle Type
  727. UINT8 DeviceHandleType;
  728. /// Reference Token for the Device Handle
  729. CM_OBJECT_TOKEN DeviceHandleToken;
  730. } CM_ARM_GENERIC_INITIATOR_AFFINITY_INFO;
  731. /** A structure that describes the CMN-600 hardware.
  732. ID: EArmObjCmn600Info
  733. */
  734. typedef struct CmArmCmn600Info {
  735. /// The PERIPHBASE address.
  736. /// Corresponds to the Configuration Node Region (CFGR) base address.
  737. UINT64 PeriphBaseAddress;
  738. /// The PERIPHBASE address length.
  739. /// Corresponds to the CFGR base address length.
  740. UINT64 PeriphBaseAddressLength;
  741. /// The ROOTNODEBASE address.
  742. /// Corresponds to the Root node (ROOT) base address.
  743. UINT64 RootNodeBaseAddress;
  744. /// The Debug and Trace Logic Controller (DTC) count.
  745. /// CMN-600 can have maximum 4 DTCs.
  746. UINT8 DtcCount;
  747. /// DTC Interrupt list.
  748. /// The first interrupt resource descriptor pertains to
  749. /// DTC[0], the second to DTC[1] and so on.
  750. /// DtcCount determines the number of DTC Interrupts that
  751. /// are populated. If DTC count is 2 then DtcInterrupt[2]
  752. /// and DtcInterrupt[3] are ignored.
  753. /// Note: The size of CM_ARM_CMN_600_INFO structure remains
  754. /// constant and does not vary with the DTC count.
  755. CM_ARM_EXTENDED_INTERRUPT DtcInterrupt[4];
  756. } CM_ARM_CMN_600_INFO;
  757. /** A structure that describes the Lpi information.
  758. The Low Power Idle states are described in DSDT/SSDT and associated
  759. to cpus/clusters in the cpu topology.
  760. ID: EArmObjLpiInfo
  761. */
  762. typedef struct CmArmLpiInfo {
  763. /** Minimum Residency. Time in microseconds after which a
  764. state becomes more energy efficient than any shallower state.
  765. */
  766. UINT32 MinResidency;
  767. /** Worst case time in microseconds from a wake interrupt
  768. being asserted to the return to a running state
  769. */
  770. UINT32 WorstCaseWakeLatency;
  771. /** Flags.
  772. */
  773. UINT32 Flags;
  774. /** Architecture specific context loss flags.
  775. */
  776. UINT32 ArchFlags;
  777. /** Residency counter frequency in cycles-per-second (Hz).
  778. */
  779. UINT32 ResCntFreq;
  780. /** Every shallower power state in the parent is also enabled.
  781. */
  782. UINT32 EnableParentState;
  783. /** The EntryMethod _LPI field can be described as an integer
  784. or in a Register resource data descriptor.
  785. If IsInteger is TRUE, the IntegerEntryMethod field is used.
  786. If IsInteger is FALSE, the RegisterEntryMethod field is used.
  787. */
  788. BOOLEAN IsInteger;
  789. /** EntryMethod described as an Integer.
  790. */
  791. UINT64 IntegerEntryMethod;
  792. /** EntryMethod described as a EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR.
  793. */
  794. EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterEntryMethod;
  795. /** Residency counter register.
  796. */
  797. EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResidencyCounterRegister;
  798. /** Usage counter register.
  799. */
  800. EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE UsageCounterRegister;
  801. /** String representing the Lpi state
  802. */
  803. CHAR8 StateName[16];
  804. } CM_ARM_LPI_INFO;
  805. /** A structure that describes a PCI Address Map.
  806. The memory-ranges used by the PCI bus are described by this object.
  807. ID: EArmObjPciAddressMapInfo
  808. */
  809. typedef struct CmArmPciAddressMapInfo {
  810. /** Pci address space code
  811. Available values are:
  812. - 0: Configuration Space
  813. - 1: I/O Space
  814. - 2: 32-bit-address Memory Space
  815. - 3: 64-bit-address Memory Space
  816. */
  817. UINT8 SpaceCode;
  818. /// PCI address
  819. UINT64 PciAddress;
  820. /// Cpu address
  821. UINT64 CpuAddress;
  822. /// Address size
  823. UINT64 AddressSize;
  824. } CM_ARM_PCI_ADDRESS_MAP_INFO;
  825. /** A structure that describes a PCI Interrupt Map.
  826. The legacy PCI interrupts used by PCI devices are described by this object.
  827. Cf Devicetree Specification - Release v0.3
  828. s2.4.3 "Interrupt Nexus Properties"
  829. ID: EArmObjPciInterruptMapInfo
  830. */
  831. typedef struct CmArmPciInterruptMapInfo {
  832. /// Pci Bus.
  833. /// Value on 8 bits (max 255).
  834. UINT8 PciBus;
  835. /// Pci Device.
  836. /// Value on 5 bits (max 31).
  837. UINT8 PciDevice;
  838. /** PCI interrupt
  839. ACPI bindings are used:
  840. Cf. ACPI 6.4, s6.2.13 _PRT (PCI Routing Table):
  841. "0-INTA, 1-INTB, 2-INTC, 3-INTD"
  842. Device-tree bindings are shifted by 1:
  843. "INTA=1, INTB=2, INTC=3, INTD=4"
  844. */
  845. UINT8 PciInterrupt;
  846. /** Interrupt controller interrupt.
  847. Cf Devicetree Specification - Release v0.3
  848. s2.4.3 "Interrupt Nexus Properties": "parent interrupt specifier"
  849. */
  850. CM_ARM_GENERIC_INTERRUPT IntcInterrupt;
  851. } CM_ARM_PCI_INTERRUPT_MAP_INFO;
  852. /** A structure that describes the
  853. RMR node for the Platform.
  854. ID: EArmObjRmr
  855. */
  856. typedef struct CmArmRmrNode {
  857. /// An unique token used to identify this object
  858. CM_OBJECT_TOKEN Token;
  859. /// Number of ID mappings
  860. UINT32 IdMappingCount;
  861. /// Reference token for the ID mapping array
  862. CM_OBJECT_TOKEN IdMappingToken;
  863. /// Unique identifier for this node.
  864. UINT32 Identifier;
  865. /// Reserved Memory Range flags.
  866. UINT32 Flags;
  867. /// Memory range descriptor count.
  868. UINT32 MemRangeDescCount;
  869. /// Reference token for the Memory Range descriptor array
  870. CM_OBJECT_TOKEN MemRangeDescToken;
  871. } CM_ARM_RMR_NODE;
  872. /** A structure that describes the
  873. Memory Range descriptor.
  874. ID: EArmObjMemoryRangeDescriptor
  875. */
  876. typedef struct CmArmRmrDescriptor {
  877. /// Base address of Reserved Memory Range,
  878. /// aligned to a page size of 64K.
  879. UINT64 BaseAddress;
  880. /// Length of the Reserved Memory range.
  881. /// Must be a multiple of the page size of 64K.
  882. UINT64 Length;
  883. } CM_ARM_MEMORY_RANGE_DESCRIPTOR;
  884. /** A structure that describes the Cpc information.
  885. Continuous Performance Control is described in DSDT/SSDT and associated
  886. to cpus/clusters in the cpu topology.
  887. Unsupported Optional registers should be encoded with NULL resource
  888. Register {(SystemMemory, 0, 0, 0, 0)}
  889. For values that support Integer or Buffer, integer will be used
  890. if buffer is NULL resource.
  891. If resource is not NULL then Integer must be 0
  892. Cf. ACPI 6.4, s8.4.7.1 _CPC (Continuous Performance Control)
  893. ID: EArmObjCpcInfo
  894. */
  895. typedef AML_CPC_INFO CM_ARM_CPC_INFO;
  896. /** A structure that describes a
  897. PCC Mailbox Register.
  898. */
  899. typedef struct PccMailboxRegisterInfo {
  900. /// GAS describing the Register.
  901. EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE Register;
  902. /** Mask of bits to preserve when writing.
  903. This mask is also used for registers. The Register is only read
  904. and there is no write mask required. E.g.:
  905. - Error Status mask (Cf. PCC Subspace types 3/4/5).
  906. - Command Complete Check mask (Cf. PCC Subspace types 3/4/5).
  907. */
  908. UINT64 PreserveMask;
  909. /// Mask of bits to set when writing.
  910. UINT64 WriteMask;
  911. } PCC_MAILBOX_REGISTER_INFO;
  912. /** A structure that describes the
  913. PCC Subspace CHannel Timings.
  914. */
  915. typedef struct PccSubspaceChannelTimingInfo {
  916. /// Expected latency to process a command, in microseconds.
  917. UINT32 NominalLatency;
  918. /** Maximum number of periodic requests that the subspace channel can
  919. support, reported in commands per minute. 0 indicates no limitation.
  920. This field is ignored for the PCC Subspace type 5 (HW Registers based).
  921. */
  922. UINT32 MaxPeriodicAccessRate;
  923. /** Minimum amount of time that OSPM must wait after the completion
  924. of a command before issuing the next command, in microseconds.
  925. */
  926. UINT16 MinRequestTurnaroundTime;
  927. } PCC_SUBSPACE_CHANNEL_TIMING_INFO;
  928. /** A structure that describes a
  929. Generic PCC Subspace (Type 0).
  930. */
  931. typedef struct CmArmPccSubspaceGenericInfo {
  932. /** Subspace Id.
  933. Cf. ACPI 6.4, s14.7 Referencing the PCC address space
  934. Cf. s14.1.2 Platform Communications Channel Subspace Structures
  935. The subspace ID of a PCC subspace is its index in the array of
  936. subspace structures, starting with subspace 0.
  937. At most 256 subspaces are supported.
  938. */
  939. UINT8 SubspaceId;
  940. /// Table type (or subspace).
  941. UINT8 Type;
  942. /// Base address of the shared memory range.
  943. /// This field is ignored for the PCC Subspace type 5 (HW Registers based).
  944. UINT64 BaseAddress;
  945. /// Address length.
  946. UINT64 AddressLength;
  947. /// Doorbell Register.
  948. PCC_MAILBOX_REGISTER_INFO DoorbellReg;
  949. /// Mailbox Timings.
  950. PCC_SUBSPACE_CHANNEL_TIMING_INFO ChannelTiming;
  951. } PCC_SUBSPACE_GENERIC_INFO;
  952. /** A structure that describes a
  953. PCC Subspace of type 0 (Generic).
  954. ID: EArmObjPccSubspaceType0Info
  955. */
  956. typedef PCC_SUBSPACE_GENERIC_INFO CM_ARM_PCC_SUBSPACE_TYPE0_INFO;
  957. /** A structure that describes a
  958. PCC Subspace of type 1 (HW-Reduced).
  959. ID: EArmObjPccSubspaceType1Info
  960. */
  961. typedef struct CmArmPccSubspaceType1Info {
  962. /** Generic Pcc information.
  963. The Subspace of Type0 contains information that can be re-used
  964. in other Subspace types.
  965. */
  966. PCC_SUBSPACE_GENERIC_INFO GenericPccInfo;
  967. /// Platform Interrupt.
  968. CM_ARM_GENERIC_INTERRUPT PlatIrq;
  969. } CM_ARM_PCC_SUBSPACE_TYPE1_INFO;
  970. /** A structure that describes a
  971. PCC Subspace of type 2 (HW-Reduced).
  972. ID: EArmObjPccSubspaceType2Info
  973. */
  974. typedef struct CmArmPccSubspaceType2Info {
  975. /** Generic Pcc information.
  976. The Subspace of Type0 contains information that can be re-used
  977. in other Subspace types.
  978. */
  979. PCC_SUBSPACE_GENERIC_INFO GenericPccInfo;
  980. /// Platform Interrupt.
  981. CM_ARM_GENERIC_INTERRUPT PlatIrq;
  982. /// Platform Interrupt Register.
  983. PCC_MAILBOX_REGISTER_INFO PlatIrqAckReg;
  984. } CM_ARM_PCC_SUBSPACE_TYPE2_INFO;
  985. /** A structure that describes a
  986. PCC Subspace of type 3 (Extended)
  987. ID: EArmObjPccSubspaceType3Info
  988. */
  989. typedef struct CmArmPccSubspaceType3Info {
  990. /** Generic Pcc information.
  991. The Subspace of Type0 contains information that can be re-used
  992. in other Subspace types.
  993. */
  994. PCC_SUBSPACE_GENERIC_INFO GenericPccInfo;
  995. /// Platform Interrupt.
  996. CM_ARM_GENERIC_INTERRUPT PlatIrq;
  997. /// Platform Interrupt Register.
  998. PCC_MAILBOX_REGISTER_INFO PlatIrqAckReg;
  999. /// Command Complete Check Register.
  1000. /// The WriteMask field is not used.
  1001. PCC_MAILBOX_REGISTER_INFO CmdCompleteCheckReg;
  1002. /// Command Complete Update Register.
  1003. PCC_MAILBOX_REGISTER_INFO CmdCompleteUpdateReg;
  1004. /// Error Status Register.
  1005. /// The WriteMask field is not used.
  1006. PCC_MAILBOX_REGISTER_INFO ErrorStatusReg;
  1007. } CM_ARM_PCC_SUBSPACE_TYPE3_INFO;
  1008. /** A structure that describes a
  1009. PCC Subspace of type 4 (Extended)
  1010. ID: EArmObjPccSubspaceType4Info
  1011. */
  1012. typedef CM_ARM_PCC_SUBSPACE_TYPE3_INFO CM_ARM_PCC_SUBSPACE_TYPE4_INFO;
  1013. /** A structure that describes a
  1014. PCC Subspace of type 5 (HW-Registers).
  1015. ID: EArmObjPccSubspaceType5Info
  1016. */
  1017. typedef struct CmArmPccSubspaceType5Info {
  1018. /** Generic Pcc information.
  1019. The Subspace of Type0 contains information that can be re-used
  1020. in other Subspace types.
  1021. MaximumPeriodicAccessRate doesn't need to be populated for
  1022. this structure.
  1023. */
  1024. PCC_SUBSPACE_GENERIC_INFO GenericPccInfo;
  1025. /// Version.
  1026. UINT16 Version;
  1027. /// Platform Interrupt.
  1028. CM_ARM_GENERIC_INTERRUPT PlatIrq;
  1029. /// Command Complete Check Register.
  1030. /// The WriteMask field is not used.
  1031. PCC_MAILBOX_REGISTER_INFO CmdCompleteCheckReg;
  1032. /// Error Status Register.
  1033. /// The WriteMask field is not used.
  1034. PCC_MAILBOX_REGISTER_INFO ErrorStatusReg;
  1035. } CM_ARM_PCC_SUBSPACE_TYPE5_INFO;
  1036. #pragma pack()
  1037. #endif // ARM_NAMESPACE_OBJECTS_H_