ArmPkg.dec 16 KB

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  1. #/** @file
  2. # ARM processor package.
  3. #
  4. # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
  5. # Copyright (c) 2011 - 2022, ARM Limited. All rights reserved.
  6. # Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
  7. #
  8. # SPDX-License-Identifier: BSD-2-Clause-Patent
  9. #
  10. #**/
  11. [Defines]
  12. DEC_SPECIFICATION = 0x00010005
  13. PACKAGE_NAME = ArmPkg
  14. PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
  15. PACKAGE_VERSION = 0.1
  16. ################################################################################
  17. #
  18. # Include Section - list of Include Paths that are provided by this package.
  19. # Comments are used for Keywords and Module Types.
  20. #
  21. # Supported Module Types:
  22. # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
  23. #
  24. ################################################################################
  25. [Includes.common]
  26. Include # Root include for the package
  27. [LibraryClasses.common]
  28. ## @libraryclass Convert Arm instructions to a human readable format.
  29. #
  30. ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
  31. ## @libraryclass Provides an interface to Arm generic counters.
  32. #
  33. ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h
  34. ## @libraryclass Provides an interface to initialize a
  35. # Generic Interrupt Controller (GIC).
  36. #
  37. ArmGicArchLib|Include/Library/ArmGicArchLib.h
  38. ## @libraryclass Provides a Generic Interrupt Controller (GIC)
  39. # configuration interface.
  40. #
  41. ArmGicLib|Include/Library/ArmGicLib.h
  42. ## @libraryclass Provides a HyperVisor Call (HVC) interface.
  43. #
  44. ArmHvcLib|Include/Library/ArmHvcLib.h
  45. ## @libraryclass Provides an interface to Arm registers.
  46. #
  47. ArmLib|Include/Library/ArmLib.h
  48. ## @libraryclass Provides a Mmu interface.
  49. #
  50. ArmMmuLib|Include/Library/ArmMmuLib.h
  51. ## @libraryclass Provides a Mailbox Transport Layer (MTL) interface
  52. # for the System Control and Management Interface (SCMI).
  53. #
  54. ArmMtlLib|Include/Library/ArmMtlLib.h
  55. ## @libraryclass Provides a System Monitor Call (SMC) interface.
  56. #
  57. ArmSmcLib|Include/Library/ArmSmcLib.h
  58. ## @libraryclass Provides a SuperVisor Call (SVC) interface.
  59. #
  60. ArmSvcLib|Include/Library/ArmSvcLib.h
  61. ## @libraryclass Provides a Monitor Call interface that will use the
  62. # default conduit (HVC or SMC).
  63. #
  64. ArmMonitorLib|Include/Library/ArmMonitorLib.h
  65. ## @libraryclass Provides a default exception handler.
  66. #
  67. DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
  68. ## @libraryclass Provides an interface to query miscellaneous OEM
  69. # information.
  70. #
  71. OemMiscLib|Include/Library/OemMiscLib.h
  72. ## @libraryclass Provides an OpTee interface.
  73. #
  74. OpteeLib|Include/Library/OpteeLib.h
  75. ## @libraryclass Provides a semihosting interface.
  76. #
  77. SemihostLib|Include/Library/SemihostLib.h
  78. ## @libraryclass Provides an interface for a StandaloneMm Mmu.
  79. #
  80. StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
  81. [Guids.common]
  82. gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
  83. ## ARM MPCore table
  84. # Include/Guid/ArmMpCoreInfo.h
  85. gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
  86. gArmMmuReplaceLiveTranslationEntryFuncGuid = { 0xa8b50ff3, 0x08ec, 0x4dd3, {0xbf, 0x04, 0x28, 0xbf, 0x71, 0x75, 0xc7, 0x4a} }
  87. [Protocols.common]
  88. ## Arm System Control and Management Interface(SCMI) Base protocol
  89. ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h
  90. gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }
  91. ## Arm System Control and Management Interface(SCMI) Clock management protocol
  92. ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
  93. gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }
  94. gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }
  95. ## Arm System Control and Management Interface(SCMI) Clock management protocol
  96. ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h
  97. gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }
  98. [Ppis]
  99. ## Include/Ppi/ArmMpCoreInfo.h
  100. gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
  101. [PcdsFeatureFlag.common]
  102. gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
  103. # On ARM Architecture with the Security Extension, the address for the
  104. # Vector Table can be mapped anywhere in the memory map. It means we can
  105. # point the Exception Vector Table to its location in CpuDxe.
  106. # By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)
  107. gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
  108. # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
  109. # it has been configured by the CPU DXE
  110. gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
  111. # Define if the GICv3 controller should use the GICv2 legacy
  112. gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
  113. ## Define the conduit to use for monitor calls.
  114. # Default PcdMonitorConduitHvc = FALSE, conduit = SMC
  115. # If PcdMonitorConduitHvc = TRUE, conduit = HVC
  116. gArmTokenSpaceGuid.PcdMonitorConduitHvc|FALSE|BOOLEAN|0x00000047
  117. [PcdsFeatureFlag.ARM]
  118. # Whether to map normal memory as non-shareable. FALSE is the safe choice, but
  119. # TRUE may be appropriate to fix performance problems if you don't care about
  120. # hardware coherency (i.e., no virtualization or cache coherent DMA)
  121. gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
  122. [PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.ARM]
  123. ## Used to select method for requesting services from S-EL1.<BR><BR>
  124. # TRUE - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>
  125. # FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>
  126. # @Prompt Enable FF-A support.
  127. gArmTokenSpaceGuid.PcdFfaEnable|FALSE|BOOLEAN|0x0000005B
  128. [PcdsFixedAtBuild.common]
  129. gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
  130. # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
  131. # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
  132. gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
  133. gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
  134. gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
  135. #
  136. # ARM Secure Firmware PCDs
  137. #
  138. gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
  139. gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
  140. gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
  141. gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
  142. #
  143. # ARM Hypervisor Firmware PCDs
  144. #
  145. gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
  146. gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
  147. gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
  148. gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
  149. # Use ClusterId + CoreId to identify the PrimaryCore
  150. gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
  151. # The Primary Core is ClusterId[0] & CoreId[0]
  152. gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
  153. #
  154. # SMBIOS PCDs
  155. #
  156. gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053
  157. gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054
  158. gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055
  159. gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056
  160. gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057
  161. gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071
  162. gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072
  163. gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073
  164. gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074
  165. gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075
  166. #
  167. # ARM L2x0 PCDs
  168. #
  169. gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
  170. #
  171. # ARM Normal (or Non Secure) Firmware PCDs
  172. #
  173. gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
  174. gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
  175. #
  176. # Value to add to a host address to obtain a device address, using
  177. # unsigned 64-bit integer arithmetic on both ARM and AArch64. This
  178. # means we can rely on truncation on overflow to specify negative
  179. # offsets.
  180. #
  181. gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044
  182. [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
  183. gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
  184. gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
  185. [PcdsFixedAtBuild.ARM]
  186. #
  187. # ARM Security Extension
  188. #
  189. # Secure Configuration Register
  190. # - BIT0 : NS - Non Secure bit
  191. # - BIT1 : IRQ Handler
  192. # - BIT2 : FIQ Handler
  193. # - BIT3 : EA - External Abort
  194. # - BIT4 : FW - F bit writable
  195. # - BIT5 : AW - A bit writable
  196. # - BIT6 : nET - Not Early Termination
  197. # - BIT7 : SCD - Secure Monitor Call Disable
  198. # - BIT8 : HCE - Hyp Call enable
  199. # - BIT9 : SIF - Secure Instruction Fetch
  200. # 0x31 = NS | EA | FW
  201. gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
  202. # By default we do not do a transition to non-secure mode
  203. gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
  204. # Non Secure Access Control Register
  205. # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
  206. # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
  207. # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
  208. # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
  209. # 0xC00 = cp10 | cp11
  210. gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
  211. [PcdsFixedAtBuild.AARCH64]
  212. #
  213. # AArch64 Security Extension
  214. #
  215. # Secure Configuration Register
  216. # - BIT0 : NS - Non Secure bit
  217. # - BIT1 : IRQ Handler
  218. # - BIT2 : FIQ Handler
  219. # - BIT3 : EA - External Abort
  220. # - BIT4 : FW - F bit writable
  221. # - BIT5 : AW - A bit writable
  222. # - BIT6 : nET - Not Early Termination
  223. # - BIT7 : SCD - Secure Monitor Call Disable
  224. # - BIT8 : HCE - Hyp Call enable
  225. # - BIT9 : SIF - Secure Instruction Fetch
  226. # - BIT10: RW - Register width control for lower exception levels
  227. # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
  228. # - BIT12: TWI - Trap WFI
  229. # - BIT13: TWE - Trap WFE
  230. # 0x501 = NS | HCE | RW
  231. gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
  232. # By default we do transition to EL2 non-secure mode with Stack for EL2.
  233. # Mode Description Bits
  234. # NS EL2 SP2 all interrupts disabled = 0x3c9
  235. # NS EL1 SP1 all interrupts disabled = 0x3c5
  236. # Other modes include using SP0 or switching to Aarch32, but these are
  237. # not currently supported.
  238. gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
  239. #
  240. # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
  241. # redefined when using UEFI in a context of virtual machine.
  242. #
  243. [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
  244. # System Memory (DRAM): These PCDs define the region of in-built system memory
  245. # Some platforms can get DRAM extensions, these additional regions may be
  246. # declared to UEFI using separate resource descriptor HOBs
  247. gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
  248. gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
  249. gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045
  250. gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046
  251. gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058
  252. gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059
  253. [PcdsFixedAtBuild.common, PcdsDynamic.common]
  254. #
  255. # ARM Architectural Timer
  256. #
  257. gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
  258. # ARM Architectural Timer Interrupt(GIC PPI) numbers
  259. gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
  260. gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
  261. gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
  262. gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
  263. #
  264. # ARM Generic Watchdog
  265. #
  266. gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007
  267. gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008
  268. gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
  269. #
  270. # ARM Generic Interrupt Controller
  271. #
  272. gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
  273. # Base address for the GIC Redistributor region that contains the boot CPU
  274. gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
  275. gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
  276. gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
  277. #
  278. # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
  279. # Note that "IO" is just another MMIO range that simulates IO space; there
  280. # are no special instructions to access it.
  281. #
  282. # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
  283. # specific to their containing address spaces. In order to get the physical
  284. # address for the CPU, for a given access, the respective translation value
  285. # has to be added.
  286. #
  287. # The translations always have to be initialized like this, using UINT64:
  288. #
  289. # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space
  290. # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
  291. # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
  292. #
  293. # gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
  294. # gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
  295. # gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
  296. #
  297. # because (a) the target address space (ie. the cpu-physical space) is
  298. # 64-bit, and (b) the translation values are meant as offsets for *modular*
  299. # arithmetic.
  300. #
  301. # Accordingly, the translation itself needs to be implemented as:
  302. #
  303. # UINT64 UntranslatedIoAddress; // input parameter
  304. # UINT32 UntranslatedMmio32Address; // input parameter
  305. # UINT64 UntranslatedMmio64Address; // input parameter
  306. #
  307. # UINT64 TranslatedIoAddress; // output parameter
  308. # UINT64 TranslatedMmio32Address; // output parameter
  309. # UINT64 TranslatedMmio64Address; // output parameter
  310. #
  311. # TranslatedIoAddress = UntranslatedIoAddress +
  312. # gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation;
  313. # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
  314. # gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation;
  315. # TranslatedMmio64Address = UntranslatedMmio64Address +
  316. # gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation;
  317. #
  318. # The modular arithmetic performed in UINT64 ensures that the translation
  319. # works correctly regardless of the relation between IoCpuBase and
  320. # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
  321. # PcdPciMmio64Base.
  322. #
  323. gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
  324. gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
  325. gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
  326. gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
  327. gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
  328. gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
  329. #
  330. # Inclusive range of allowed PCI buses.
  331. #
  332. gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
  333. gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A
  334. [PcdsDynamicEx]
  335. #
  336. # This dynamic PCD hold the GUID of a firmware FFS which contains
  337. # the LinuxBoot payload.
  338. #
  339. gArmTokenSpaceGuid.PcdLinuxBootFileGuid|{0x0}|VOID*|0x0000005C