SmramInternal.c 6.2 KB

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  1. /** @file
  2. Functions and types shared by the SMM accessor PEI and DXE modules.
  3. Copyright (C) 2015, Red Hat, Inc.
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <Guid/AcpiS3Context.h>
  7. #include <IndustryStandard/Q35MchIch9.h>
  8. #include <Library/DebugLib.h>
  9. #include <Library/PcdLib.h>
  10. #include <Library/PciLib.h>
  11. #include "SmramInternal.h"
  12. //
  13. // The value of PcdQ35TsegMbytes is saved into this variable at module startup.
  14. //
  15. UINT16 mQ35TsegMbytes;
  16. //
  17. // The value of PcdQ35SmramAtDefaultSmbase is saved into this variable at
  18. // module startup.
  19. //
  20. STATIC BOOLEAN mQ35SmramAtDefaultSmbase;
  21. /**
  22. Save PcdQ35TsegMbytes into mQ35TsegMbytes.
  23. **/
  24. VOID
  25. InitQ35TsegMbytes (
  26. VOID
  27. )
  28. {
  29. mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);
  30. }
  31. /**
  32. Save PcdQ35SmramAtDefaultSmbase into mQ35SmramAtDefaultSmbase.
  33. **/
  34. VOID
  35. InitQ35SmramAtDefaultSmbase (
  36. VOID
  37. )
  38. {
  39. mQ35SmramAtDefaultSmbase = PcdGetBool (PcdQ35SmramAtDefaultSmbase);
  40. }
  41. /**
  42. Read the MCH_SMRAM and ESMRAMC registers, and update the LockState and
  43. OpenState fields in the PEI_SMM_ACCESS_PPI / EFI_SMM_ACCESS2_PROTOCOL object,
  44. from the D_LCK and T_EN bits.
  45. PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL member functions can rely on
  46. the LockState and OpenState fields being up-to-date on entry, and they need
  47. to restore the same invariant on exit, if they touch the bits in question.
  48. @param[out] LockState Reflects the D_LCK bit on output; TRUE iff SMRAM is
  49. locked.
  50. @param[out] OpenState Reflects the inverse of the T_EN bit on output; TRUE
  51. iff SMRAM is open.
  52. **/
  53. VOID
  54. GetStates (
  55. OUT BOOLEAN *LockState,
  56. OUT BOOLEAN *OpenState
  57. )
  58. {
  59. UINT8 SmramVal, EsmramcVal;
  60. SmramVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_SMRAM));
  61. EsmramcVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC));
  62. *LockState = !!(SmramVal & MCH_SMRAM_D_LCK);
  63. *OpenState = !(EsmramcVal & MCH_ESMRAMC_T_EN);
  64. }
  65. //
  66. // The functions below follow the PEI_SMM_ACCESS_PPI and
  67. // EFI_SMM_ACCESS2_PROTOCOL member declarations. The PeiServices and This
  68. // pointers are removed (TSEG doesn't depend on them), and so is the
  69. // DescriptorIndex parameter (TSEG doesn't support range-wise locking).
  70. //
  71. // The LockState and OpenState members that are common to both
  72. // PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL are taken and updated in
  73. // isolation from the rest of the (non-shared) members.
  74. //
  75. EFI_STATUS
  76. SmramAccessOpen (
  77. OUT BOOLEAN *LockState,
  78. OUT BOOLEAN *OpenState
  79. )
  80. {
  81. //
  82. // Open TSEG by clearing T_EN.
  83. //
  84. PciAnd8 (
  85. DRAMC_REGISTER_Q35 (MCH_ESMRAMC),
  86. (UINT8)((~(UINT32)MCH_ESMRAMC_T_EN) & 0xff)
  87. );
  88. GetStates (LockState, OpenState);
  89. if (!*OpenState) {
  90. return EFI_DEVICE_ERROR;
  91. }
  92. return EFI_SUCCESS;
  93. }
  94. EFI_STATUS
  95. SmramAccessClose (
  96. OUT BOOLEAN *LockState,
  97. OUT BOOLEAN *OpenState
  98. )
  99. {
  100. //
  101. // Close TSEG by setting T_EN.
  102. //
  103. PciOr8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), MCH_ESMRAMC_T_EN);
  104. GetStates (LockState, OpenState);
  105. if (*OpenState) {
  106. return EFI_DEVICE_ERROR;
  107. }
  108. return EFI_SUCCESS;
  109. }
  110. EFI_STATUS
  111. SmramAccessLock (
  112. OUT BOOLEAN *LockState,
  113. IN OUT BOOLEAN *OpenState
  114. )
  115. {
  116. if (*OpenState) {
  117. return EFI_DEVICE_ERROR;
  118. }
  119. //
  120. // Close & lock TSEG by setting T_EN and D_LCK.
  121. //
  122. PciOr8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), MCH_ESMRAMC_T_EN);
  123. PciOr8 (DRAMC_REGISTER_Q35 (MCH_SMRAM), MCH_SMRAM_D_LCK);
  124. //
  125. // Close & lock the SMRAM at the default SMBASE, if it exists.
  126. //
  127. if (mQ35SmramAtDefaultSmbase) {
  128. PciWrite8 (
  129. DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL),
  130. MCH_DEFAULT_SMBASE_LCK
  131. );
  132. }
  133. GetStates (LockState, OpenState);
  134. if (*OpenState || !*LockState) {
  135. return EFI_DEVICE_ERROR;
  136. }
  137. return EFI_SUCCESS;
  138. }
  139. EFI_STATUS
  140. SmramAccessGetCapabilities (
  141. IN BOOLEAN LockState,
  142. IN BOOLEAN OpenState,
  143. IN OUT UINTN *SmramMapSize,
  144. IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
  145. )
  146. {
  147. UINTN OriginalSize;
  148. UINT32 TsegMemoryBaseMb, TsegMemoryBase;
  149. UINT64 CommonRegionState;
  150. UINT8 TsegSizeBits;
  151. OriginalSize = *SmramMapSize;
  152. *SmramMapSize = DescIdxCount * sizeof *SmramMap;
  153. if (OriginalSize < *SmramMapSize) {
  154. return EFI_BUFFER_TOO_SMALL;
  155. }
  156. //
  157. // Read the TSEG Memory Base register.
  158. //
  159. TsegMemoryBaseMb = PciRead32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB));
  160. TsegMemoryBase = (TsegMemoryBaseMb >> MCH_TSEGMB_MB_SHIFT) << 20;
  161. //
  162. // Precompute the region state bits that will be set for all regions.
  163. //
  164. CommonRegionState = (OpenState ? EFI_SMRAM_OPEN : EFI_SMRAM_CLOSED) |
  165. (LockState ? EFI_SMRAM_LOCKED : 0) |
  166. EFI_CACHEABLE;
  167. //
  168. // The first region hosts an SMM_S3_RESUME_STATE object. It is located at the
  169. // start of TSEG. We round up the size to whole pages, and we report it as
  170. // EFI_ALLOCATED, so that the SMM_CORE stays away from it.
  171. //
  172. SmramMap[DescIdxSmmS3ResumeState].PhysicalStart = TsegMemoryBase;
  173. SmramMap[DescIdxSmmS3ResumeState].CpuStart = TsegMemoryBase;
  174. SmramMap[DescIdxSmmS3ResumeState].PhysicalSize =
  175. EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (sizeof (SMM_S3_RESUME_STATE)));
  176. SmramMap[DescIdxSmmS3ResumeState].RegionState =
  177. CommonRegionState | EFI_ALLOCATED;
  178. //
  179. // Get the TSEG size bits from the ESMRAMC register.
  180. //
  181. TsegSizeBits = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC)) &
  182. MCH_ESMRAMC_TSEG_MASK;
  183. //
  184. // The second region is the main one, following the first.
  185. //
  186. SmramMap[DescIdxMain].PhysicalStart =
  187. SmramMap[DescIdxSmmS3ResumeState].PhysicalStart +
  188. SmramMap[DescIdxSmmS3ResumeState].PhysicalSize;
  189. SmramMap[DescIdxMain].CpuStart = SmramMap[DescIdxMain].PhysicalStart;
  190. SmramMap[DescIdxMain].PhysicalSize =
  191. (TsegSizeBits == MCH_ESMRAMC_TSEG_8MB ? SIZE_8MB :
  192. TsegSizeBits == MCH_ESMRAMC_TSEG_2MB ? SIZE_2MB :
  193. TsegSizeBits == MCH_ESMRAMC_TSEG_1MB ? SIZE_1MB :
  194. mQ35TsegMbytes * SIZE_1MB) -
  195. SmramMap[DescIdxSmmS3ResumeState].PhysicalSize;
  196. SmramMap[DescIdxMain].RegionState = CommonRegionState;
  197. return EFI_SUCCESS;
  198. }