SmmAccessPei.c 12 KB

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  1. /** @file
  2. A PEIM with the following responsibilities:
  3. - verify & configure the Q35 TSEG in the entry point,
  4. - provide SMRAM access by producing PEI_SMM_ACCESS_PPI,
  5. - set aside the SMM_S3_RESUME_STATE object at the bottom of TSEG, and expose
  6. it via the gEfiAcpiVariableGuid GUID HOB.
  7. This PEIM runs from RAM, so we can write to variables with static storage
  8. duration.
  9. Copyright (C) 2013, 2015, Red Hat, Inc.<BR>
  10. Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
  11. SPDX-License-Identifier: BSD-2-Clause-Patent
  12. **/
  13. #include <Guid/AcpiS3Context.h>
  14. #include <Library/BaseLib.h>
  15. #include <Library/BaseMemoryLib.h>
  16. #include <Library/DebugLib.h>
  17. #include <Library/HobLib.h>
  18. #include <Library/IoLib.h>
  19. #include <Library/PcdLib.h>
  20. #include <Library/PciLib.h>
  21. #include <Library/PeiServicesLib.h>
  22. #include <Ppi/SmmAccess.h>
  23. #include <OvmfPlatforms.h>
  24. #include "SmramInternal.h"
  25. //
  26. // PEI_SMM_ACCESS_PPI implementation.
  27. //
  28. /**
  29. Opens the SMRAM area to be accessible by a PEIM driver.
  30. This function "opens" SMRAM so that it is visible while not inside of SMM.
  31. The function should return EFI_UNSUPPORTED if the hardware does not support
  32. hiding of SMRAM. The function should return EFI_DEVICE_ERROR if the SMRAM
  33. configuration is locked.
  34. @param PeiServices General purpose services available to every
  35. PEIM.
  36. @param This The pointer to the SMM Access Interface.
  37. @param DescriptorIndex The region of SMRAM to Open.
  38. @retval EFI_SUCCESS The region was successfully opened.
  39. @retval EFI_DEVICE_ERROR The region could not be opened because locked
  40. by chipset.
  41. @retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.
  42. **/
  43. STATIC
  44. EFI_STATUS
  45. EFIAPI
  46. SmmAccessPeiOpen (
  47. IN EFI_PEI_SERVICES **PeiServices,
  48. IN PEI_SMM_ACCESS_PPI *This,
  49. IN UINTN DescriptorIndex
  50. )
  51. {
  52. if (DescriptorIndex >= DescIdxCount) {
  53. return EFI_INVALID_PARAMETER;
  54. }
  55. //
  56. // According to current practice, DescriptorIndex is not considered at all,
  57. // beyond validating it.
  58. //
  59. return SmramAccessOpen (&This->LockState, &This->OpenState);
  60. }
  61. /**
  62. Inhibits access to the SMRAM.
  63. This function "closes" SMRAM so that it is not visible while outside of SMM.
  64. The function should return EFI_UNSUPPORTED if the hardware does not support
  65. hiding of SMRAM.
  66. @param PeiServices General purpose services available to every
  67. PEIM.
  68. @param This The pointer to the SMM Access Interface.
  69. @param DescriptorIndex The region of SMRAM to Close.
  70. @retval EFI_SUCCESS The region was successfully closed.
  71. @retval EFI_DEVICE_ERROR The region could not be closed because
  72. locked by chipset.
  73. @retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.
  74. **/
  75. STATIC
  76. EFI_STATUS
  77. EFIAPI
  78. SmmAccessPeiClose (
  79. IN EFI_PEI_SERVICES **PeiServices,
  80. IN PEI_SMM_ACCESS_PPI *This,
  81. IN UINTN DescriptorIndex
  82. )
  83. {
  84. if (DescriptorIndex >= DescIdxCount) {
  85. return EFI_INVALID_PARAMETER;
  86. }
  87. //
  88. // According to current practice, DescriptorIndex is not considered at all,
  89. // beyond validating it.
  90. //
  91. return SmramAccessClose (&This->LockState, &This->OpenState);
  92. }
  93. /**
  94. Inhibits access to the SMRAM.
  95. This function prohibits access to the SMRAM region. This function is usually
  96. implemented such that it is a write-once operation.
  97. @param PeiServices General purpose services available to every
  98. PEIM.
  99. @param This The pointer to the SMM Access Interface.
  100. @param DescriptorIndex The region of SMRAM to Close.
  101. @retval EFI_SUCCESS The region was successfully locked.
  102. @retval EFI_DEVICE_ERROR The region could not be locked because at
  103. least one range is still open.
  104. @retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.
  105. **/
  106. STATIC
  107. EFI_STATUS
  108. EFIAPI
  109. SmmAccessPeiLock (
  110. IN EFI_PEI_SERVICES **PeiServices,
  111. IN PEI_SMM_ACCESS_PPI *This,
  112. IN UINTN DescriptorIndex
  113. )
  114. {
  115. if (DescriptorIndex >= DescIdxCount) {
  116. return EFI_INVALID_PARAMETER;
  117. }
  118. //
  119. // According to current practice, DescriptorIndex is not considered at all,
  120. // beyond validating it.
  121. //
  122. return SmramAccessLock (&This->LockState, &This->OpenState);
  123. }
  124. /**
  125. Queries the memory controller for the possible regions that will support
  126. SMRAM.
  127. @param PeiServices General purpose services available to every
  128. PEIM.
  129. @param This The pointer to the SmmAccessPpi Interface.
  130. @param SmramMapSize The pointer to the variable containing size of
  131. the buffer to contain the description
  132. information.
  133. @param SmramMap The buffer containing the data describing the
  134. Smram region descriptors.
  135. @retval EFI_BUFFER_TOO_SMALL The user did not provide a sufficient buffer.
  136. @retval EFI_SUCCESS The user provided a sufficiently-sized buffer.
  137. **/
  138. STATIC
  139. EFI_STATUS
  140. EFIAPI
  141. SmmAccessPeiGetCapabilities (
  142. IN EFI_PEI_SERVICES **PeiServices,
  143. IN PEI_SMM_ACCESS_PPI *This,
  144. IN OUT UINTN *SmramMapSize,
  145. IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
  146. )
  147. {
  148. return SmramAccessGetCapabilities (
  149. This->LockState,
  150. This->OpenState,
  151. SmramMapSize,
  152. SmramMap
  153. );
  154. }
  155. //
  156. // LockState and OpenState will be filled in by the entry point.
  157. //
  158. STATIC PEI_SMM_ACCESS_PPI mAccess = {
  159. &SmmAccessPeiOpen,
  160. &SmmAccessPeiClose,
  161. &SmmAccessPeiLock,
  162. &SmmAccessPeiGetCapabilities
  163. };
  164. STATIC EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {
  165. {
  166. EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  167. &gPeiSmmAccessPpiGuid, &mAccess
  168. }
  169. };
  170. //
  171. // Utility functions.
  172. //
  173. STATIC
  174. UINT8
  175. CmosRead8 (
  176. IN UINT8 Index
  177. )
  178. {
  179. IoWrite8 (0x70, Index);
  180. return IoRead8 (0x71);
  181. }
  182. STATIC
  183. UINT32
  184. GetSystemMemorySizeBelow4gb (
  185. VOID
  186. )
  187. {
  188. UINT32 Cmos0x34;
  189. UINT32 Cmos0x35;
  190. Cmos0x34 = CmosRead8 (0x34);
  191. Cmos0x35 = CmosRead8 (0x35);
  192. return ((Cmos0x35 << 8 | Cmos0x34) << 16) + SIZE_16MB;
  193. }
  194. //
  195. // Entry point of this driver.
  196. //
  197. EFI_STATUS
  198. EFIAPI
  199. SmmAccessPeiEntryPoint (
  200. IN EFI_PEI_FILE_HANDLE FileHandle,
  201. IN CONST EFI_PEI_SERVICES **PeiServices
  202. )
  203. {
  204. UINT16 HostBridgeDevId;
  205. UINT8 EsmramcVal;
  206. UINT8 RegMask8;
  207. UINT32 TopOfLowRam, TopOfLowRamMb;
  208. EFI_STATUS Status;
  209. UINTN SmramMapSize;
  210. EFI_SMRAM_DESCRIPTOR SmramMap[DescIdxCount];
  211. VOID *GuidHob;
  212. //
  213. // This module should only be included if SMRAM support is required.
  214. //
  215. ASSERT (FeaturePcdGet (PcdSmmSmramRequire));
  216. //
  217. // Verify if we're running on a Q35 machine type.
  218. //
  219. HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
  220. if (HostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {
  221. DEBUG ((
  222. DEBUG_ERROR,
  223. "%a: no SMRAM with host bridge DID=0x%04x; only "
  224. "DID=0x%04x (Q35) is supported\n",
  225. __FUNCTION__,
  226. HostBridgeDevId,
  227. INTEL_Q35_MCH_DEVICE_ID
  228. ));
  229. goto WrongConfig;
  230. }
  231. //
  232. // Confirm if QEMU supports SMRAM.
  233. //
  234. // With no support for it, the ESMRAMC (Extended System Management RAM
  235. // Control) register reads as zero. If there is support, the cache-enable
  236. // bits are hard-coded as 1 by QEMU.
  237. //
  238. EsmramcVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC));
  239. RegMask8 = MCH_ESMRAMC_SM_CACHE | MCH_ESMRAMC_SM_L1 | MCH_ESMRAMC_SM_L2;
  240. if ((EsmramcVal & RegMask8) != RegMask8) {
  241. DEBUG ((
  242. DEBUG_ERROR,
  243. "%a: this Q35 implementation lacks SMRAM\n",
  244. __FUNCTION__
  245. ));
  246. goto WrongConfig;
  247. }
  248. TopOfLowRam = GetSystemMemorySizeBelow4gb ();
  249. ASSERT ((TopOfLowRam & (SIZE_1MB - 1)) == 0);
  250. TopOfLowRamMb = TopOfLowRam >> 20;
  251. //
  252. // Some of the following registers are no-ops for QEMU at the moment, but it
  253. // is recommended to set them correctly, since the ESMRAMC that we ultimately
  254. // care about is in the same set of registers.
  255. //
  256. // First, we disable the integrated VGA, and set both the GTT Graphics Memory
  257. // Size and the Graphics Mode Select memory pre-allocation fields to zero.
  258. // This takes just one write to the Graphics Control Register.
  259. //
  260. PciWrite16 (DRAMC_REGISTER_Q35 (MCH_GGC), MCH_GGC_IVD);
  261. //
  262. // Set Top of Low Usable DRAM.
  263. //
  264. PciWrite16 (
  265. DRAMC_REGISTER_Q35 (MCH_TOLUD),
  266. (UINT16)(TopOfLowRamMb << MCH_TOLUD_MB_SHIFT)
  267. );
  268. //
  269. // Given the zero graphics memory sizes configured above, set the
  270. // graphics-related stolen memory bases to the same as TOLUD.
  271. //
  272. PciWrite32 (
  273. DRAMC_REGISTER_Q35 (MCH_GBSM),
  274. TopOfLowRamMb << MCH_GBSM_MB_SHIFT
  275. );
  276. PciWrite32 (
  277. DRAMC_REGISTER_Q35 (MCH_BGSM),
  278. TopOfLowRamMb << MCH_BGSM_MB_SHIFT
  279. );
  280. //
  281. // Set TSEG Memory Base.
  282. //
  283. InitQ35TsegMbytes ();
  284. PciWrite32 (
  285. DRAMC_REGISTER_Q35 (MCH_TSEGMB),
  286. (TopOfLowRamMb - mQ35TsegMbytes) << MCH_TSEGMB_MB_SHIFT
  287. );
  288. //
  289. // Set TSEG size, and disable TSEG visibility outside of SMM. Note that the
  290. // T_EN bit has inverse meaning; when T_EN is set, then TSEG visibility is
  291. // *restricted* to SMM.
  292. //
  293. EsmramcVal &= ~(UINT32)MCH_ESMRAMC_TSEG_MASK;
  294. EsmramcVal |= mQ35TsegMbytes == 8 ? MCH_ESMRAMC_TSEG_8MB :
  295. mQ35TsegMbytes == 2 ? MCH_ESMRAMC_TSEG_2MB :
  296. mQ35TsegMbytes == 1 ? MCH_ESMRAMC_TSEG_1MB :
  297. MCH_ESMRAMC_TSEG_EXT;
  298. EsmramcVal |= MCH_ESMRAMC_T_EN;
  299. PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal);
  300. //
  301. // TSEG should be closed (see above), but unlocked, initially. Set G_SMRAME
  302. // (Global SMRAM Enable) too, as both D_LCK and T_EN depend on it.
  303. //
  304. PciAndThenOr8 (
  305. DRAMC_REGISTER_Q35 (MCH_SMRAM),
  306. (UINT8)((~(UINT32)MCH_SMRAM_D_LCK) & 0xff),
  307. MCH_SMRAM_G_SMRAME
  308. );
  309. //
  310. // Create the GUID HOB and point it to the first SMRAM range.
  311. //
  312. GetStates (&mAccess.LockState, &mAccess.OpenState);
  313. SmramMapSize = sizeof SmramMap;
  314. Status = SmramAccessGetCapabilities (
  315. mAccess.LockState,
  316. mAccess.OpenState,
  317. &SmramMapSize,
  318. SmramMap
  319. );
  320. ASSERT_EFI_ERROR (Status);
  321. DEBUG_CODE_BEGIN ();
  322. {
  323. UINTN Count;
  324. UINTN Idx;
  325. Count = SmramMapSize / sizeof SmramMap[0];
  326. DEBUG ((
  327. DEBUG_VERBOSE,
  328. "%a: SMRAM map follows, %d entries\n",
  329. __FUNCTION__,
  330. (INT32)Count
  331. ));
  332. DEBUG ((
  333. DEBUG_VERBOSE,
  334. "% 20a % 20a % 20a % 20a\n",
  335. "PhysicalStart(0x)",
  336. "PhysicalSize(0x)",
  337. "CpuStart(0x)",
  338. "RegionState(0x)"
  339. ));
  340. for (Idx = 0; Idx < Count; ++Idx) {
  341. DEBUG ((
  342. DEBUG_VERBOSE,
  343. "% 20Lx % 20Lx % 20Lx % 20Lx\n",
  344. SmramMap[Idx].PhysicalStart,
  345. SmramMap[Idx].PhysicalSize,
  346. SmramMap[Idx].CpuStart,
  347. SmramMap[Idx].RegionState
  348. ));
  349. }
  350. }
  351. DEBUG_CODE_END ();
  352. GuidHob = BuildGuidHob (
  353. &gEfiAcpiVariableGuid,
  354. sizeof SmramMap[DescIdxSmmS3ResumeState]
  355. );
  356. if (GuidHob == NULL) {
  357. return EFI_OUT_OF_RESOURCES;
  358. }
  359. CopyMem (
  360. GuidHob,
  361. &SmramMap[DescIdxSmmS3ResumeState],
  362. sizeof SmramMap[DescIdxSmmS3ResumeState]
  363. );
  364. //
  365. // SmramAccessLock() depends on "mQ35SmramAtDefaultSmbase"; init the latter
  366. // just before exposing the former via PEI_SMM_ACCESS_PPI.Lock().
  367. //
  368. InitQ35SmramAtDefaultSmbase ();
  369. //
  370. // We're done. The next step should succeed, but even if it fails, we can't
  371. // roll back the above BuildGuidHob() allocation, because PEI doesn't support
  372. // releasing memory.
  373. //
  374. return PeiServicesInstallPpi (mPpiList);
  375. WrongConfig:
  376. //
  377. // We really don't want to continue in this case.
  378. //
  379. ASSERT (FALSE);
  380. CpuDeadLoop ();
  381. return EFI_UNSUPPORTED;
  382. }