PrePi.c 7.2 KB

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  1. /** @file
  2. Copyright (c) 2011-2017, ARM Limited. All rights reserved.
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #include <PiPei.h>
  6. #include <Library/CacheMaintenanceLib.h>
  7. #include <Library/DebugAgentLib.h>
  8. #include <Library/PrePiLib.h>
  9. #include <Library/PrintLib.h>
  10. #include <Library/PrePiHobListPointerLib.h>
  11. #include <Library/TimerLib.h>
  12. #include <Library/PerformanceLib.h>
  13. #include <Ppi/GuidedSectionExtraction.h>
  14. #include <Ppi/ArmMpCoreInfo.h>
  15. #include <Ppi/SecPerformance.h>
  16. #include "PrePi.h"
  17. #define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) ||\
  18. ((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= FixedPcdGet64 (PcdSystemMemoryBase)))
  19. UINT64 mSystemMemoryEnd = FixedPcdGet64 (PcdSystemMemoryBase) +
  20. FixedPcdGet64 (PcdSystemMemorySize) - 1;
  21. EFI_STATUS
  22. GetPlatformPpi (
  23. IN EFI_GUID *PpiGuid,
  24. OUT VOID **Ppi
  25. )
  26. {
  27. UINTN PpiListSize;
  28. UINTN PpiListCount;
  29. EFI_PEI_PPI_DESCRIPTOR *PpiList;
  30. UINTN Index;
  31. PpiListSize = 0;
  32. ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
  33. PpiListCount = PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR);
  34. for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
  35. if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {
  36. *Ppi = PpiList->Ppi;
  37. return EFI_SUCCESS;
  38. }
  39. }
  40. return EFI_NOT_FOUND;
  41. }
  42. VOID
  43. PrePiMain (
  44. IN UINTN UefiMemoryBase,
  45. IN UINTN StacksBase,
  46. IN UINT64 StartTimeStamp
  47. )
  48. {
  49. EFI_HOB_HANDOFF_INFO_TABLE *HobList;
  50. ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;
  51. UINTN ArmCoreCount;
  52. ARM_CORE_INFO *ArmCoreInfoTable;
  53. EFI_STATUS Status;
  54. CHAR8 Buffer[100];
  55. UINTN CharCount;
  56. UINTN StacksSize;
  57. FIRMWARE_SEC_PERFORMANCE Performance;
  58. // If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)
  59. ASSERT (
  60. IS_XIP () ||
  61. ((FixedPcdGet64 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) &&
  62. ((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT64)mSystemMemoryEnd))
  63. );
  64. // Initialize the architecture specific bits
  65. ArchInitialize ();
  66. // Initialize the Serial Port
  67. SerialPortInitialize ();
  68. CharCount = AsciiSPrint (
  69. Buffer,
  70. sizeof (Buffer),
  71. "UEFI firmware (version %s built at %a on %a)\n\r",
  72. (CHAR16 *)PcdGetPtr (PcdFirmwareVersionString),
  73. __TIME__,
  74. __DATE__
  75. );
  76. SerialPortWrite ((UINT8 *)Buffer, CharCount);
  77. // Initialize the Debug Agent for Source Level Debugging
  78. InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
  79. SaveAndSetDebugTimerInterrupt (TRUE);
  80. // Declare the PI/UEFI memory region
  81. HobList = HobConstructor (
  82. (VOID *)UefiMemoryBase,
  83. FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),
  84. (VOID *)UefiMemoryBase,
  85. (VOID *)StacksBase // The top of the UEFI Memory is reserved for the stacks
  86. );
  87. PrePeiSetHobList (HobList);
  88. // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)
  89. Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));
  90. ASSERT_EFI_ERROR (Status);
  91. // Create the Stacks HOB (reserve the memory for all stacks)
  92. if (ArmIsMpCore ()) {
  93. StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize) +
  94. ((FixedPcdGet32 (PcdCoreCount) - 1) * FixedPcdGet32 (PcdCPUCoreSecondaryStackSize));
  95. } else {
  96. StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);
  97. }
  98. BuildStackHob (StacksBase, StacksSize);
  99. // TODO: Call CpuPei as a library
  100. BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));
  101. if (ArmIsMpCore ()) {
  102. // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid
  103. Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID **)&ArmMpCoreInfoPpi);
  104. // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
  105. ASSERT_EFI_ERROR (Status);
  106. // Build the MP Core Info Table
  107. ArmCoreCount = 0;
  108. Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
  109. if (!EFI_ERROR (Status) && (ArmCoreCount > 0)) {
  110. // Build MPCore Info HOB
  111. BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);
  112. }
  113. }
  114. // Store timer value logged at the beginning of firmware image execution
  115. Performance.ResetEnd = GetTimeInNanoSecond (StartTimeStamp);
  116. // Build SEC Performance Data Hob
  117. BuildGuidDataHob (&gEfiFirmwarePerformanceGuid, &Performance, sizeof (Performance));
  118. // Set the Boot Mode
  119. SetBootMode (ArmPlatformGetBootMode ());
  120. // Initialize Platform HOBs (CpuHob and FvHob)
  121. Status = PlatformPeim ();
  122. ASSERT_EFI_ERROR (Status);
  123. // Now, the HOB List has been initialized, we can register performance information
  124. PERF_START (NULL, "PEI", NULL, StartTimeStamp);
  125. // SEC phase needs to run library constructors by hand.
  126. ProcessLibraryConstructorList ();
  127. // Assume the FV that contains the SEC (our code) also contains a compressed FV.
  128. Status = DecompressFirstFv ();
  129. ASSERT_EFI_ERROR (Status);
  130. // Load the DXE Core and transfer control to it
  131. Status = LoadDxeCoreFromFv (NULL, 0);
  132. ASSERT_EFI_ERROR (Status);
  133. }
  134. VOID
  135. CEntryPoint (
  136. IN UINTN MpId,
  137. IN UINTN UefiMemoryBase,
  138. IN UINTN StacksBase
  139. )
  140. {
  141. UINT64 StartTimeStamp;
  142. // Initialize the platform specific controllers
  143. ArmPlatformInitialize (MpId);
  144. if (ArmPlatformIsPrimaryCore (MpId) && PerformanceMeasurementEnabled ()) {
  145. // Initialize the Timer Library to setup the Timer HW controller
  146. TimerConstructor ();
  147. // We cannot call yet the PerformanceLib because the HOB List has not been initialized
  148. StartTimeStamp = GetPerformanceCounter ();
  149. } else {
  150. StartTimeStamp = 0;
  151. }
  152. // Data Cache enabled on Primary core when MMU is enabled.
  153. ArmDisableDataCache ();
  154. // Invalidate instruction cache
  155. ArmInvalidateInstructionCache ();
  156. // Enable Instruction Caches on all cores.
  157. ArmEnableInstructionCache ();
  158. // Define the Global Variable region when we are not running in XIP
  159. if (!IS_XIP ()) {
  160. if (ArmPlatformIsPrimaryCore (MpId)) {
  161. if (ArmIsMpCore ()) {
  162. // Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)
  163. ArmCallSEV ();
  164. }
  165. } else {
  166. // Wait the Primary core has defined the address of the Global Variable region (event: ARM_CPU_EVENT_DEFAULT)
  167. ArmCallWFE ();
  168. }
  169. }
  170. // If not primary Jump to Secondary Main
  171. if (ArmPlatformIsPrimaryCore (MpId)) {
  172. InvalidateDataCacheRange (
  173. (VOID *)UefiMemoryBase,
  174. FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)
  175. );
  176. // Goto primary Main.
  177. PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp);
  178. } else {
  179. SecondaryMain (MpId);
  180. }
  181. // DXE Core should always load and never return
  182. ASSERT (FALSE);
  183. }