DebugCommunicationLibUsb3Internal.h 19 KB

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  1. /** @file
  2. Debug Port Library implementation based on usb3 debug port.
  3. Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef __USB3_DEBUG_PORT_LIB_INTERNAL__
  7. #define __USB3_DEBUG_PORT_LIB_INTERNAL__
  8. #include <Uefi.h>
  9. #include <Base.h>
  10. #include <IndustryStandard/Usb.h>
  11. #include <Library/IoLib.h>
  12. #include <IndustryStandard/Pci.h>
  13. #include <Library/PcdLib.h>
  14. #include <Library/UefiLib.h>
  15. #include <Library/UefiBootServicesTableLib.h>
  16. #include <Library/MemoryAllocationLib.h>
  17. #include <Library/DebugLib.h>
  18. #include <Library/BaseMemoryLib.h>
  19. #include <Library/BaseLib.h>
  20. #include <Library/TimerLib.h>
  21. #include <Library/DebugCommunicationLib.h>
  22. #include <Library/PciLib.h>
  23. //
  24. // USB Debug GUID value
  25. //
  26. #define USB3_DBG_GUID \
  27. { \
  28. 0xb2a56f4d, 0x9177, 0x4fc8, { 0xa6, 0x77, 0xdd, 0x96, 0x3e, 0xb4, 0xcb, 0x1b } \
  29. }
  30. //
  31. // The state machine of usb debug port
  32. //
  33. #define USB3DBG_NO_DBG_CAB 0 // The XHCI host controller does not support debug capability
  34. #define USB3DBG_DBG_CAB 1 // The XHCI host controller supports debug capability
  35. #define USB3DBG_ENABLED 2 // The XHCI debug device is enabled
  36. #define USB3DBG_NOT_ENABLED 4 // The XHCI debug device is not enabled
  37. #define USB3DBG_UNINITIALIZED 255 // The XHCI debug device is uninitialized
  38. #define USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE 0x08
  39. //
  40. // MaxPacketSize for DbC Endpoint Descriptor IN and OUT
  41. //
  42. #define XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE 0x400
  43. #define XHCI_DEBUG_DEVICE_VENDOR_ID 0x0525
  44. #define XHCI_DEBUG_DEVICE_PRODUCT_ID 0x127A
  45. #define XHCI_DEBUG_DEVICE_PROTOCOL 0xFF
  46. #define XHCI_DEBUG_DEVICE_REVISION 0x00
  47. #define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL
  48. #define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000
  49. #define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A
  50. #define XHC_HCCPARAMS_OFFSET 0x10
  51. #define XHC_CAPABILITY_ID_MASK 0xFF
  52. #define XHC_NEXT_CAPABILITY_MASK 0xFF00
  53. #define XHC_HCSPARAMS1_OFFSET 0x4 // Structural Parameters 1
  54. #define XHC_USBCMD_OFFSET 0x0 // USB Command Register Offset
  55. #define XHC_USBSTS_OFFSET 0x4 // USB Status Register Offset
  56. #define XHC_PORTSC_OFFSET 0x400 // Port Status and Control Register Offset
  57. #define XHC_USBCMD_RUN BIT0 // Run/Stop
  58. #define XHC_USBCMD_RESET BIT1 // Host Controller Reset
  59. #define XHC_USBSTS_HALT BIT0
  60. //
  61. // Indicate the timeout when data is transferred in microsecond. 0 means infinite timeout.
  62. //
  63. #define DATA_TRANSFER_WRITE_TIMEOUT 0
  64. #define DATA_TRANSFER_READ_TIMEOUT 50000
  65. #define DATA_TRANSFER_POLL_TIMEOUT 1000
  66. #define XHC_DEBUG_PORT_1_MILLISECOND 1000
  67. //
  68. // XHCI port power off/on delay
  69. //
  70. #define XHC_DEBUG_PORT_ON_OFF_DELAY 100000
  71. //
  72. // USB debug device string descriptor (header size + unicode string length)
  73. //
  74. #define STRING0_DESC_LEN 4
  75. #define MANU_DESC_LEN 12
  76. #define PRODUCT_DESC_LEN 40
  77. #define SERIAL_DESC_LEN 4
  78. //
  79. // Debug Capability Register Offset
  80. //
  81. #define XHC_DC_DCID 0x0
  82. #define XHC_DC_DCDB 0x4
  83. #define XHC_DC_DCERSTSZ 0x8
  84. #define XHC_DC_DCERSTBA 0x10
  85. #define XHC_DC_DCERDP 0x18
  86. #define XHC_DC_DCCTRL 0x20
  87. #define XHC_DC_DCST 0x24
  88. #define XHC_DC_DCPORTSC 0x28
  89. #define XHC_DC_DCCP 0x30
  90. #define XHC_DC_DCDDI1 0x38
  91. #define XHC_DC_DCDDI2 0x3C
  92. #define TRB_TYPE_LINK 6
  93. #define ERST_NUMBER 0x01
  94. #define TR_RING_TRB_NUMBER 0x100
  95. #define EVENT_RING_TRB_NUMBER 0x200
  96. #define ED_BULK_OUT 2
  97. #define ED_BULK_IN 6
  98. #define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
  99. #define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
  100. #define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
  101. //
  102. // Endpoint Type (EP Type).
  103. //
  104. #define ED_NOT_VALID 0
  105. #define ED_ISOCH_OUT 1
  106. #define ED_BULK_OUT 2
  107. #define ED_INTERRUPT_OUT 3
  108. #define ED_CONTROL_BIDIR 4
  109. #define ED_ISOCH_IN 5
  110. #define ED_BULK_IN 6
  111. #define ED_INTERRUPT_IN 7
  112. //
  113. // 6.4.5 TRB Completion Codes
  114. //
  115. #define TRB_COMPLETION_INVALID 0
  116. #define TRB_COMPLETION_SUCCESS 1
  117. #define TRB_COMPLETION_DATA_BUFFER_ERROR 2
  118. #define TRB_COMPLETION_BABBLE_ERROR 3
  119. #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
  120. #define TRB_COMPLETION_TRB_ERROR 5
  121. #define TRB_COMPLETION_STALL_ERROR 6
  122. #define TRB_COMPLETION_SHORT_PACKET 13
  123. //
  124. // 6.4.6 TRB Types
  125. //
  126. #define TRB_TYPE_NORMAL 1
  127. #define TRB_TYPE_SETUP_STAGE 2
  128. #define TRB_TYPE_DATA_STAGE 3
  129. #define TRB_TYPE_STATUS_STAGE 4
  130. #define TRB_TYPE_ISOCH 5
  131. #define TRB_TYPE_LINK 6
  132. #define TRB_TYPE_EVENT_DATA 7
  133. #define TRB_TYPE_NO_OP 8
  134. #define TRB_TYPE_EN_SLOT 9
  135. #define TRB_TYPE_DIS_SLOT 10
  136. #define TRB_TYPE_ADDRESS_DEV 11
  137. #define TRB_TYPE_CON_ENDPOINT 12
  138. #define TRB_TYPE_EVALU_CONTXT 13
  139. #define TRB_TYPE_RESET_ENDPOINT 14
  140. #define TRB_TYPE_STOP_ENDPOINT 15
  141. #define TRB_TYPE_SET_TR_DEQUE 16
  142. #define TRB_TYPE_RESET_DEV 17
  143. #define TRB_TYPE_GET_PORT_BANW 21
  144. #define TRB_TYPE_FORCE_HEADER 22
  145. #define TRB_TYPE_NO_OP_COMMAND 23
  146. #define TRB_TYPE_TRANS_EVENT 32
  147. #define TRB_TYPE_COMMAND_COMPLT_EVENT 33
  148. #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
  149. #define TRB_TYPE_HOST_CONTROLLER_EVENT 37
  150. #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
  151. #define TRB_TYPE_MFINDEX_WRAP_EVENT 39
  152. //
  153. // Convert millisecond to microsecond.
  154. //
  155. #define XHC_1_MILLISECOND (1000)
  156. #define XHC_POLL_DELAY (1000)
  157. #define XHC_GENERIC_TIMEOUT (10 * 1000)
  158. #define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.
  159. #define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.
  160. #define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.
  161. #define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.
  162. //
  163. // Transfer types, used in URB to identify the transfer type
  164. //
  165. #define XHC_CTRL_TRANSFER 0x01
  166. #define XHC_BULK_TRANSFER 0x02
  167. #define XHC_INT_TRANSFER_SYNC 0x04
  168. #define XHC_INT_TRANSFER_ASYNC 0x08
  169. #define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
  170. //
  171. // USB Transfer Results
  172. //
  173. #define EFI_USB_NOERROR 0x00
  174. #define EFI_USB_ERR_NOTEXECUTE 0x01
  175. #define EFI_USB_ERR_STALL 0x02
  176. #define EFI_USB_ERR_BUFFER 0x04
  177. #define EFI_USB_ERR_BABBLE 0x08
  178. #define EFI_USB_ERR_NAK 0x10
  179. #define EFI_USB_ERR_CRC 0x20
  180. #define EFI_USB_ERR_TIMEOUT 0x40
  181. #define EFI_USB_ERR_BITSTUFF 0x80
  182. #define EFI_USB_ERR_SYSTEM 0x100
  183. #pragma pack(1)
  184. //
  185. // 7.6.9 OUT/IN EP Context: 64 bytes
  186. // 7.6.9.2 When used by the DbC it is always a 64 byte data structure
  187. //
  188. typedef struct _ENDPOINT_CONTEXT_64 {
  189. UINT32 EPState : 3;
  190. UINT32 RsvdZ1 : 5;
  191. UINT32 Mult : 2; // set to 0
  192. UINT32 MaxPStreams : 5; // set to 0
  193. UINT32 LSA : 1; // set to 0
  194. UINT32 Interval : 8; // set to 0
  195. UINT32 RsvdZ2 : 8;
  196. UINT32 RsvdZ3 : 1;
  197. UINT32 CErr : 2;
  198. UINT32 EPType : 3;
  199. UINT32 RsvdZ4 : 1;
  200. UINT32 HID : 1; // set to 0
  201. UINT32 MaxBurstSize : 8;
  202. UINT32 MaxPacketSize : 16;
  203. UINT32 PtrLo;
  204. UINT32 PtrHi;
  205. UINT32 AverageTRBLength : 16;
  206. UINT32 MaxESITPayload : 16; // set to 0
  207. UINT32 RsvdZ5; // Reserved
  208. UINT32 RsvdZ6;
  209. UINT32 RsvdZ7;
  210. UINT32 RsvdZ8;
  211. UINT32 RsvdZ9;
  212. UINT32 RsvdZ10;
  213. UINT32 RsvdZ11;
  214. UINT32 RsvdZ12;
  215. UINT32 RsvdZ13;
  216. UINT32 RsvdZ14;
  217. UINT32 RsvdZ15;
  218. } ENDPOINT_CONTEXT_64;
  219. //
  220. // 6.4.1.1 Normal TRB: 16 bytes
  221. // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and
  222. // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer
  223. // Rings, and to define the Data stage information for Control Transfer Rings.
  224. //
  225. typedef struct _TRANSFER_TRB_NORMAL {
  226. UINT32 TRBPtrLo;
  227. UINT32 TRBPtrHi;
  228. UINT32 Length : 17;
  229. UINT32 TDSize : 5;
  230. UINT32 IntTarget : 10;
  231. UINT32 CycleBit : 1;
  232. UINT32 ENT : 1;
  233. UINT32 ISP : 1;
  234. UINT32 NS : 1;
  235. UINT32 CH : 1;
  236. UINT32 IOC : 1;
  237. UINT32 IDT : 1;
  238. UINT32 RsvdZ1 : 2;
  239. UINT32 BEI : 1;
  240. UINT32 Type : 6;
  241. UINT32 RsvdZ2 : 16;
  242. } TRANSFER_TRB_NORMAL;
  243. //
  244. // 6.4.2.1 Transfer Event TRB: 16 bytes
  245. // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1
  246. // for more information on the use and operation of Transfer Events.
  247. //
  248. typedef struct _EVT_TRB_TRANSFER {
  249. UINT32 TRBPtrLo;
  250. UINT32 TRBPtrHi;
  251. UINT32 Length : 24;
  252. UINT32 Completecode : 8;
  253. UINT32 CycleBit : 1;
  254. UINT32 RsvdZ1 : 1;
  255. UINT32 ED : 1;
  256. UINT32 RsvdZ2 : 7;
  257. UINT32 Type : 6;
  258. UINT32 EndpointId : 5;
  259. UINT32 RsvdZ3 : 3;
  260. UINT32 SlotId : 8;
  261. } EVT_TRB_TRANSFER;
  262. //
  263. // 6.4.4.1 Link TRB: 16 bytes
  264. // A Link TRB provides support for non-contiguous TRB Rings.
  265. //
  266. typedef struct _LINK_TRB {
  267. UINT32 PtrLo;
  268. UINT32 PtrHi;
  269. UINT32 RsvdZ1 : 22;
  270. UINT32 InterTarget : 10;
  271. UINT32 CycleBit : 1;
  272. UINT32 TC : 1;
  273. UINT32 RsvdZ2 : 2;
  274. UINT32 CH : 1;
  275. UINT32 IOC : 1;
  276. UINT32 RsvdZ3 : 4;
  277. UINT32 Type : 6;
  278. UINT32 RsvdZ4 : 16;
  279. } LINK_TRB;
  280. //
  281. // TRB Template: 16 bytes
  282. //
  283. typedef struct _TRB_TEMPLATE {
  284. UINT32 Parameter1;
  285. UINT32 Parameter2;
  286. UINT32 Status;
  287. UINT32 CycleBit : 1;
  288. UINT32 RsvdZ1 : 9;
  289. UINT32 Type : 6;
  290. UINT32 Control : 16;
  291. } TRB_TEMPLATE;
  292. //
  293. // Refer to XHCI 6.5 Event Ring Segment Table: 16 bytes
  294. //
  295. typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
  296. UINT32 PtrLo;
  297. UINT32 PtrHi;
  298. UINT32 RingTrbSize : 16;
  299. UINT32 RsvdZ1 : 16;
  300. UINT32 RsvdZ2;
  301. } EVENT_RING_SEG_TABLE_ENTRY;
  302. //
  303. // Size: 40 bytes
  304. //
  305. typedef struct _EVENT_RING {
  306. EFI_PHYSICAL_ADDRESS ERSTBase;
  307. EFI_PHYSICAL_ADDRESS EventRingSeg0;
  308. UINT32 TrbNumber;
  309. EFI_PHYSICAL_ADDRESS EventRingEnqueue;
  310. EFI_PHYSICAL_ADDRESS EventRingDequeue;
  311. UINT32 EventRingCCS;
  312. } EVENT_RING;
  313. // Size: 32 bytes
  314. typedef struct _TRANSFER_RING {
  315. EFI_PHYSICAL_ADDRESS RingSeg0;
  316. UINT32 TrbNumber;
  317. EFI_PHYSICAL_ADDRESS RingEnqueue;
  318. EFI_PHYSICAL_ADDRESS RingDequeue;
  319. UINT32 RingPCS;
  320. } TRANSFER_RING;
  321. //
  322. // Size: 64 bytes
  323. //
  324. typedef struct _DBC_INFO_CONTEXT {
  325. UINT64 String0DescAddress;
  326. UINT64 ManufacturerStrDescAddress;
  327. UINT64 ProductStrDescAddress;
  328. UINT64 SerialNumberStrDescAddress;
  329. UINT64 String0Length : 8;
  330. UINT64 ManufacturerStrLength : 8;
  331. UINT64 ProductStrLength : 8;
  332. UINT64 SerialNumberStrLength : 8;
  333. UINT64 RsvdZ1 : 32;
  334. UINT64 RsvdZ2;
  335. UINT64 RsvdZ3;
  336. UINT64 RsvdZ4;
  337. } DBC_INFO_CONTEXT;
  338. //
  339. // Debug Capability Context Data Structure: 192 bytes
  340. //
  341. typedef struct _XHC_DC_CONTEXT {
  342. DBC_INFO_CONTEXT DbcInfoContext;
  343. ENDPOINT_CONTEXT_64 EpOutContext;
  344. ENDPOINT_CONTEXT_64 EpInContext;
  345. } XHC_DC_CONTEXT;
  346. //
  347. // Size: 16 bytes
  348. //
  349. typedef union _TRB {
  350. TRB_TEMPLATE TrbTemplate;
  351. TRANSFER_TRB_NORMAL TrbNormal;
  352. } TRB;
  353. ///
  354. /// USB data transfer direction
  355. ///
  356. typedef enum {
  357. EfiUsbDataIn,
  358. EfiUsbDataOut,
  359. EfiUsbNoData
  360. } EFI_USB_DATA_DIRECTION;
  361. //
  362. // URB (Usb Request Block) contains information for all kinds of
  363. // usb requests.
  364. //
  365. typedef struct _URB {
  366. //
  367. // Transfer data buffer
  368. //
  369. EFI_PHYSICAL_ADDRESS Data;
  370. UINT32 DataLen;
  371. //
  372. // Execute result
  373. //
  374. UINT32 Result;
  375. //
  376. // Completed data length
  377. //
  378. UINT32 Completed;
  379. //
  380. // Tranfer Ring info
  381. //
  382. EFI_PHYSICAL_ADDRESS Ring;
  383. EFI_PHYSICAL_ADDRESS Trb;
  384. BOOLEAN Finished;
  385. EFI_USB_DATA_DIRECTION Direction;
  386. } URB;
  387. typedef struct _USB3_DEBUG_PORT_INSTANCE {
  388. UINT8 Initialized;
  389. //
  390. // The flag indicates debug capability is supported
  391. //
  392. BOOLEAN DebugSupport;
  393. //
  394. // The flag indicates debug device is ready
  395. //
  396. BOOLEAN Ready;
  397. //
  398. // The flag indicates the instance is from HOB
  399. //
  400. BOOLEAN FromHob;
  401. //
  402. // Prevent notification being interrupted by debug timer
  403. //
  404. BOOLEAN InNotify;
  405. //
  406. // PciIo protocol event
  407. //
  408. EFI_PHYSICAL_ADDRESS PciIoEvent;
  409. //
  410. // The flag indicates if USB 3.0 ports has been turn off/on power
  411. //
  412. BOOLEAN ChangePortPower;
  413. //
  414. // XHCI MMIO Base address
  415. //
  416. EFI_PHYSICAL_ADDRESS XhciMmioBase;
  417. //
  418. // XHCI OP RegisterBase address
  419. //
  420. EFI_PHYSICAL_ADDRESS XhciOpRegister;
  421. //
  422. // XHCI Debug Register Base Address
  423. //
  424. EFI_PHYSICAL_ADDRESS DebugCapabilityBase;
  425. //
  426. // XHCI Debug Capability offset
  427. //
  428. UINT64 DebugCapabilityOffset;
  429. //
  430. // XHCI Debug Context Address
  431. //
  432. EFI_PHYSICAL_ADDRESS DebugCapabilityContext;
  433. //
  434. // Transfer Ring
  435. //
  436. TRANSFER_RING TransferRingOut;
  437. TRANSFER_RING TransferRingIn;
  438. //
  439. // EventRing
  440. //
  441. EVENT_RING EventRing;
  442. //
  443. // URB - Read
  444. //
  445. URB UrbOut;
  446. //
  447. // URB - Write
  448. //
  449. URB UrbIn;
  450. //
  451. // The available data length in the following data buffer.
  452. //
  453. UINT8 DataCount;
  454. //
  455. // The data buffer address for data read and poll.
  456. //
  457. EFI_PHYSICAL_ADDRESS Data;
  458. } USB3_DEBUG_PORT_HANDLE;
  459. #pragma pack()
  460. /**
  461. Read XHCI debug register.
  462. @param Handle Debug port handle.
  463. @param Offset The offset of the debug register.
  464. @return The register content read
  465. **/
  466. UINT32
  467. XhcReadDebugReg (
  468. IN USB3_DEBUG_PORT_HANDLE *Handle,
  469. IN UINT32 Offset
  470. );
  471. /**
  472. Set one bit of the debug register while keeping other bits.
  473. @param Handle Debug port handle.
  474. @param Offset The offset of the debug register.
  475. @param Bit The bit mask of the register to set.
  476. **/
  477. VOID
  478. XhcSetDebugRegBit (
  479. IN USB3_DEBUG_PORT_HANDLE *Handle,
  480. IN UINT32 Offset,
  481. IN UINT32 Bit
  482. );
  483. /**
  484. Write the data to the debug register.
  485. @param Handle Debug port handle.
  486. @param Offset The offset of the debug register.
  487. @param Data The data to write.
  488. **/
  489. VOID
  490. XhcWriteDebugReg (
  491. IN USB3_DEBUG_PORT_HANDLE *Handle,
  492. IN UINT32 Offset,
  493. IN UINT32 Data
  494. );
  495. /**
  496. Verifies if the bit positions specified by a mask are set in a register.
  497. @param[in, out] Register UINTN register
  498. @param[in] BitMask 32-bit mask
  499. @return BOOLEAN - TRUE if all bits specified by the mask are enabled.
  500. - FALSE even if one of the bits specified by the mask
  501. is not enabled.
  502. **/
  503. BOOLEAN
  504. XhcIsBitSet (
  505. UINTN Register,
  506. UINT32 BitMask
  507. );
  508. /**
  509. Sets bits as per the enabled bit positions in the mask.
  510. @param[in, out] Register UINTN register
  511. @param[in] BitMask 32-bit mask
  512. **/
  513. VOID
  514. XhcSetR32Bit (
  515. UINTN Register,
  516. UINT32 BitMask
  517. );
  518. /**
  519. Clears bits as per the enabled bit positions in the mask.
  520. @param[in, out] Register UINTN register
  521. @param[in] BitMask 32-bit mask
  522. **/
  523. VOID
  524. XhcClearR32Bit (
  525. IN OUT UINTN Register,
  526. IN UINT32 BitMask
  527. );
  528. /**
  529. Initialize USB3 debug port.
  530. This method invokes various internal functions to facilitate
  531. detection and initialization of USB3 debug port.
  532. @retval RETURN_SUCCESS The serial device was initialized.
  533. **/
  534. RETURN_STATUS
  535. EFIAPI
  536. USB3Initialize (
  537. VOID
  538. );
  539. /**
  540. Return command register value in XHCI controller.
  541. **/
  542. UINT16
  543. GetXhciPciCommand (
  544. VOID
  545. );
  546. /**
  547. Allocate aligned memory for XHC's usage.
  548. @param BufferSize The size, in bytes, of the Buffer.
  549. @return A pointer to the allocated buffer or NULL if allocation fails.
  550. **/
  551. VOID *
  552. AllocateAlignBuffer (
  553. IN UINTN BufferSize
  554. );
  555. /**
  556. The real function to initialize USB3 debug port.
  557. This method invokes various internal functions to facilitate
  558. detection and initialization of USB3 debug port.
  559. @retval RETURN_SUCCESS The serial device was initialized.
  560. **/
  561. RETURN_STATUS
  562. EFIAPI
  563. USB3InitializeReal (
  564. VOID
  565. );
  566. /**
  567. Submits bulk transfer to a bulk endpoint of a USB device.
  568. @param Handle The instance of debug device.
  569. @param Direction The direction of data transfer.
  570. @param Data Array of pointers to the buffers of data to transmit
  571. from or receive into.
  572. @param DataLength The length of the data buffer.
  573. @param Timeout Indicates the maximum time, in millisecond, which
  574. the transfer is allowed to complete.
  575. @retval EFI_SUCCESS The transfer was completed successfully.
  576. @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.
  577. @retval EFI_INVALID_PARAMETER Some parameters are invalid.
  578. @retval EFI_TIMEOUT The transfer failed due to timeout.
  579. @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
  580. **/
  581. EFI_STATUS
  582. EFIAPI
  583. XhcDataTransfer (
  584. IN USB3_DEBUG_PORT_HANDLE *Handle,
  585. IN EFI_USB_DATA_DIRECTION Direction,
  586. IN OUT VOID *Data,
  587. IN OUT UINTN *DataLength,
  588. IN UINTN Timeout
  589. );
  590. /**
  591. Initialize usb debug port hardware.
  592. @param Handle Debug port handle.
  593. @retval TRUE The usb debug port hardware configuration is changed.
  594. @retval FALSE The usb debug port hardware configuration is not changed.
  595. **/
  596. RETURN_STATUS
  597. EFIAPI
  598. InitializeUsbDebugHardware (
  599. IN USB3_DEBUG_PORT_HANDLE *Handle
  600. );
  601. /**
  602. Return USB3 debug instance address pointer.
  603. **/
  604. EFI_PHYSICAL_ADDRESS *
  605. GetUsb3DebugPortInstanceAddrPtr (
  606. VOID
  607. );
  608. /**
  609. Return USB3 debug instance address.
  610. **/
  611. USB3_DEBUG_PORT_HANDLE *
  612. GetUsb3DebugPortInstance (
  613. VOID
  614. );
  615. #endif //__SERIAL_PORT_LIB_USB__