Tpm12Tis.c 17 KB

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  1. /** @file
  2. TIS (TPM Interface Specification) functions used by TPM1.2.
  3. Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
  4. (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #include <Uefi.h>
  8. #include <IndustryStandard/Tpm12.h>
  9. #include <Library/BaseLib.h>
  10. #include <Library/BaseMemoryLib.h>
  11. #include <Library/IoLib.h>
  12. #include <Library/TimerLib.h>
  13. #include <Library/DebugLib.h>
  14. #include <Library/Tpm12CommandLib.h>
  15. #include <Library/PcdLib.h>
  16. #include <IndustryStandard/TpmPtp.h>
  17. #include <IndustryStandard/TpmTis.h>
  18. typedef enum {
  19. PtpInterfaceTis,
  20. PtpInterfaceFifo,
  21. PtpInterfaceCrb,
  22. PtpInterfaceMax,
  23. } PTP_INTERFACE_TYPE;
  24. //
  25. // Max TPM command/reponse length
  26. //
  27. #define TPMCMDBUFLENGTH 1024
  28. /**
  29. Check whether TPM chip exist.
  30. @param[in] TisReg Pointer to TIS register.
  31. @retval TRUE TPM chip exists.
  32. @retval FALSE TPM chip is not found.
  33. **/
  34. BOOLEAN
  35. Tpm12TisPcPresenceCheck (
  36. IN TIS_PC_REGISTERS_PTR TisReg
  37. )
  38. {
  39. UINT8 RegRead;
  40. RegRead = MmioRead8 ((UINTN)&TisReg->Access);
  41. return (BOOLEAN)(RegRead != (UINT8)-1);
  42. }
  43. /**
  44. Return PTP interface type.
  45. @param[in] Register Pointer to PTP register.
  46. @return PTP interface type.
  47. **/
  48. PTP_INTERFACE_TYPE
  49. Tpm12GetPtpInterface (
  50. IN VOID *Register
  51. )
  52. {
  53. PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;
  54. PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;
  55. if (!Tpm12TisPcPresenceCheck (Register)) {
  56. return PtpInterfaceMax;
  57. }
  58. //
  59. // Check interface id
  60. //
  61. InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
  62. InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
  63. if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&
  64. (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&
  65. (InterfaceId.Bits.CapCRB != 0)) {
  66. return PtpInterfaceCrb;
  67. }
  68. if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO) &&
  69. (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO) &&
  70. (InterfaceId.Bits.CapFIFO != 0) &&
  71. (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP)) {
  72. return PtpInterfaceFifo;
  73. }
  74. return PtpInterfaceTis;
  75. }
  76. /**
  77. Check whether the value of a TPM chip register satisfies the input BIT setting.
  78. @param[in] Register Address port of register to be checked.
  79. @param[in] BitSet Check these data bits are set.
  80. @param[in] BitClear Check these data bits are clear.
  81. @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.
  82. @retval EFI_SUCCESS The register satisfies the check bit.
  83. @retval EFI_TIMEOUT The register can't run into the expected status in time.
  84. **/
  85. EFI_STATUS
  86. Tpm12TisPcWaitRegisterBits (
  87. IN UINT8 *Register,
  88. IN UINT8 BitSet,
  89. IN UINT8 BitClear,
  90. IN UINT32 TimeOut
  91. )
  92. {
  93. UINT8 RegRead;
  94. UINT32 WaitTime;
  95. for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
  96. RegRead = MmioRead8 ((UINTN)Register);
  97. if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)
  98. return EFI_SUCCESS;
  99. MicroSecondDelay (30);
  100. }
  101. return EFI_TIMEOUT;
  102. }
  103. /**
  104. Get BurstCount by reading the burstCount field of a TIS regiger
  105. in the time of default TIS_TIMEOUT_D.
  106. @param[in] TisReg Pointer to TIS register.
  107. @param[out] BurstCount Pointer to a buffer to store the got BurstCount.
  108. @retval EFI_SUCCESS Get BurstCount.
  109. @retval EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.
  110. @retval EFI_TIMEOUT BurstCount can't be got in time.
  111. **/
  112. EFI_STATUS
  113. Tpm12TisPcReadBurstCount (
  114. IN TIS_PC_REGISTERS_PTR TisReg,
  115. OUT UINT16 *BurstCount
  116. )
  117. {
  118. UINT32 WaitTime;
  119. UINT8 DataByte0;
  120. UINT8 DataByte1;
  121. if (BurstCount == NULL || TisReg == NULL) {
  122. return EFI_INVALID_PARAMETER;
  123. }
  124. WaitTime = 0;
  125. do {
  126. //
  127. // TIS_PC_REGISTERS_PTR->burstCount is UINT16, but it is not 2bytes aligned,
  128. // so it needs to use MmioRead8 to read two times
  129. //
  130. DataByte0 = MmioRead8 ((UINTN)&TisReg->BurstCount);
  131. DataByte1 = MmioRead8 ((UINTN)&TisReg->BurstCount + 1);
  132. *BurstCount = (UINT16)((DataByte1 << 8) + DataByte0);
  133. if (*BurstCount != 0) {
  134. return EFI_SUCCESS;
  135. }
  136. MicroSecondDelay (30);
  137. WaitTime += 30;
  138. } while (WaitTime < TIS_TIMEOUT_D);
  139. return EFI_TIMEOUT;
  140. }
  141. /**
  142. Set TPM chip to ready state by sending ready command TIS_PC_STS_READY
  143. to Status Register in time.
  144. @param[in] TisReg Pointer to TIS register.
  145. @retval EFI_SUCCESS TPM chip enters into ready state.
  146. @retval EFI_INVALID_PARAMETER TisReg is NULL.
  147. @retval EFI_TIMEOUT TPM chip can't be set to ready state in time.
  148. **/
  149. EFI_STATUS
  150. Tpm12TisPcPrepareCommand (
  151. IN TIS_PC_REGISTERS_PTR TisReg
  152. )
  153. {
  154. EFI_STATUS Status;
  155. if (TisReg == NULL) {
  156. return EFI_INVALID_PARAMETER;
  157. }
  158. MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
  159. Status = Tpm12TisPcWaitRegisterBits (
  160. &TisReg->Status,
  161. TIS_PC_STS_READY,
  162. 0,
  163. TIS_TIMEOUT_B
  164. );
  165. return Status;
  166. }
  167. /**
  168. Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE
  169. to ACCESS Register in the time of default TIS_TIMEOUT_A.
  170. @param[in] TisReg Pointer to TIS register.
  171. @retval EFI_SUCCESS Get the control of TPM chip.
  172. @retval EFI_INVALID_PARAMETER TisReg is NULL.
  173. @retval EFI_NOT_FOUND TPM chip doesn't exit.
  174. @retval EFI_TIMEOUT Can't get the TPM control in time.
  175. **/
  176. EFI_STATUS
  177. Tpm12TisPcRequestUseTpm (
  178. IN TIS_PC_REGISTERS_PTR TisReg
  179. )
  180. {
  181. EFI_STATUS Status;
  182. if (TisReg == NULL) {
  183. return EFI_INVALID_PARAMETER;
  184. }
  185. if (!Tpm12TisPcPresenceCheck (TisReg)) {
  186. return EFI_NOT_FOUND;
  187. }
  188. MmioWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);
  189. Status = Tpm12TisPcWaitRegisterBits (
  190. &TisReg->Access,
  191. (UINT8)(TIS_PC_ACC_ACTIVE |TIS_PC_VALID),
  192. 0,
  193. TIS_TIMEOUT_A
  194. );
  195. return Status;
  196. }
  197. /**
  198. Send a command to TPM for execution and return response data.
  199. @param[in] TisReg TPM register space base address.
  200. @param[in] BufferIn Buffer for command data.
  201. @param[in] SizeIn Size of command data.
  202. @param[in, out] BufferOut Buffer for response data.
  203. @param[in, out] SizeOut Size of response data.
  204. @retval EFI_SUCCESS Operation completed successfully.
  205. @retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.
  206. @retval EFI_DEVICE_ERROR Unexpected device behavior.
  207. @retval EFI_UNSUPPORTED Unsupported TPM version
  208. **/
  209. EFI_STATUS
  210. Tpm12TisTpmCommand (
  211. IN TIS_PC_REGISTERS_PTR TisReg,
  212. IN UINT8 *BufferIn,
  213. IN UINT32 SizeIn,
  214. IN OUT UINT8 *BufferOut,
  215. IN OUT UINT32 *SizeOut
  216. )
  217. {
  218. EFI_STATUS Status;
  219. UINT16 BurstCount;
  220. UINT32 Index;
  221. UINT32 TpmOutSize;
  222. UINT16 Data16;
  223. UINT32 Data32;
  224. UINT16 RspTag;
  225. DEBUG_CODE (
  226. UINTN DebugSize;
  227. DEBUG ((EFI_D_VERBOSE, "Tpm12TisTpmCommand Send - "));
  228. if (SizeIn > 0x100) {
  229. DebugSize = 0x40;
  230. } else {
  231. DebugSize = SizeIn;
  232. }
  233. for (Index = 0; Index < DebugSize; Index++) {
  234. DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));
  235. }
  236. if (DebugSize != SizeIn) {
  237. DEBUG ((EFI_D_VERBOSE, "...... "));
  238. for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {
  239. DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));
  240. }
  241. }
  242. DEBUG ((EFI_D_VERBOSE, "\n"));
  243. );
  244. TpmOutSize = 0;
  245. Status = Tpm12TisPcPrepareCommand (TisReg);
  246. if (EFI_ERROR (Status)){
  247. DEBUG ((DEBUG_ERROR, "Tpm12 is not ready for command!\n"));
  248. return EFI_DEVICE_ERROR;
  249. }
  250. //
  251. // Send the command data to Tpm
  252. //
  253. Index = 0;
  254. while (Index < SizeIn) {
  255. Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);
  256. if (EFI_ERROR (Status)) {
  257. Status = EFI_DEVICE_ERROR;
  258. goto Exit;
  259. }
  260. for (; BurstCount > 0 && Index < SizeIn; BurstCount--) {
  261. MmioWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));
  262. Index++;
  263. }
  264. }
  265. //
  266. // Check the Tpm status STS_EXPECT change from 1 to 0
  267. //
  268. Status = Tpm12TisPcWaitRegisterBits (
  269. &TisReg->Status,
  270. (UINT8) TIS_PC_VALID,
  271. TIS_PC_STS_EXPECT,
  272. TIS_TIMEOUT_C
  273. );
  274. if (EFI_ERROR (Status)) {
  275. DEBUG ((DEBUG_ERROR, "Tpm12 The send buffer too small!\n"));
  276. Status = EFI_BUFFER_TOO_SMALL;
  277. goto Exit;
  278. }
  279. //
  280. // Executed the TPM command and waiting for the response data ready
  281. //
  282. MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);
  283. Status = Tpm12TisPcWaitRegisterBits (
  284. &TisReg->Status,
  285. (UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA),
  286. 0,
  287. TIS_TIMEOUT_B
  288. );
  289. if (EFI_ERROR (Status)) {
  290. DEBUG ((DEBUG_ERROR, "Wait for Tpm12 response data time out!!\n"));
  291. Status = EFI_DEVICE_ERROR;
  292. goto Exit;
  293. }
  294. //
  295. // Get response data header
  296. //
  297. Index = 0;
  298. BurstCount = 0;
  299. while (Index < sizeof (TPM_RSP_COMMAND_HDR)) {
  300. Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);
  301. if (EFI_ERROR (Status)) {
  302. Status = EFI_DEVICE_ERROR;
  303. goto Exit;
  304. }
  305. for (; BurstCount > 0; BurstCount--) {
  306. *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
  307. Index++;
  308. if (Index == sizeof (TPM_RSP_COMMAND_HDR)) break;
  309. }
  310. }
  311. DEBUG_CODE (
  312. DEBUG ((EFI_D_VERBOSE, "Tpm12TisTpmCommand ReceiveHeader - "));
  313. for (Index = 0; Index < sizeof (TPM_RSP_COMMAND_HDR); Index++) {
  314. DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));
  315. }
  316. DEBUG ((EFI_D_VERBOSE, "\n"));
  317. );
  318. //
  319. // Check the response data header (tag, parasize and returncode)
  320. //
  321. CopyMem (&Data16, BufferOut, sizeof (UINT16));
  322. RspTag = SwapBytes16 (Data16);
  323. if (RspTag != TPM_TAG_RSP_COMMAND && RspTag != TPM_TAG_RSP_AUTH1_COMMAND && RspTag != TPM_TAG_RSP_AUTH2_COMMAND) {
  324. DEBUG ((EFI_D_ERROR, "TPM12: Response tag error - current tag value is %x\n", RspTag));
  325. Status = EFI_UNSUPPORTED;
  326. goto Exit;
  327. }
  328. CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));
  329. TpmOutSize = SwapBytes32 (Data32);
  330. if (*SizeOut < TpmOutSize) {
  331. Status = EFI_BUFFER_TOO_SMALL;
  332. goto Exit;
  333. }
  334. *SizeOut = TpmOutSize;
  335. //
  336. // Continue reading the remaining data
  337. //
  338. while ( Index < TpmOutSize ) {
  339. for (; BurstCount > 0; BurstCount--) {
  340. *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
  341. Index++;
  342. if (Index == TpmOutSize) {
  343. Status = EFI_SUCCESS;
  344. goto Exit;
  345. }
  346. }
  347. Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);
  348. if (EFI_ERROR (Status)) {
  349. Status = EFI_DEVICE_ERROR;
  350. goto Exit;
  351. }
  352. }
  353. Exit:
  354. DEBUG_CODE (
  355. DEBUG ((EFI_D_VERBOSE, "Tpm12TisTpmCommand Receive - "));
  356. for (Index = 0; Index < TpmOutSize; Index++) {
  357. DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));
  358. }
  359. DEBUG ((EFI_D_VERBOSE, "\n"));
  360. );
  361. MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);
  362. return Status;
  363. }
  364. /**
  365. This service enables the sending of commands to the TPM12.
  366. @param[in] InputParameterBlockSize Size of the TPM12 input parameter block.
  367. @param[in] InputParameterBlock Pointer to the TPM12 input parameter block.
  368. @param[in,out] OutputParameterBlockSize Size of the TPM12 output parameter block.
  369. @param[in] OutputParameterBlock Pointer to the TPM12 output parameter block.
  370. @retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.
  371. @retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.
  372. @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small.
  373. **/
  374. EFI_STATUS
  375. EFIAPI
  376. Tpm12SubmitCommand (
  377. IN UINT32 InputParameterBlockSize,
  378. IN UINT8 *InputParameterBlock,
  379. IN OUT UINT32 *OutputParameterBlockSize,
  380. IN UINT8 *OutputParameterBlock
  381. )
  382. {
  383. PTP_INTERFACE_TYPE PtpInterface;
  384. //
  385. // Special handle for TPM1.2 to check PTP too, because PTP/TIS share same register address.
  386. //
  387. PtpInterface = Tpm12GetPtpInterface ((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));
  388. switch (PtpInterface) {
  389. case PtpInterfaceFifo:
  390. case PtpInterfaceTis:
  391. return Tpm12TisTpmCommand (
  392. (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),
  393. InputParameterBlock,
  394. InputParameterBlockSize,
  395. OutputParameterBlock,
  396. OutputParameterBlockSize
  397. );
  398. case PtpInterfaceCrb:
  399. //
  400. // No need to support CRB because it is only accept TPM2 command.
  401. //
  402. default:
  403. return EFI_DEVICE_ERROR;
  404. }
  405. }
  406. /**
  407. Check whether the value of a TPM chip register satisfies the input BIT setting.
  408. @param[in] Register Address port of register to be checked.
  409. @param[in] BitSet Check these data bits are set.
  410. @param[in] BitClear Check these data bits are clear.
  411. @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.
  412. @retval EFI_SUCCESS The register satisfies the check bit.
  413. @retval EFI_TIMEOUT The register can't run into the expected status in time.
  414. **/
  415. EFI_STATUS
  416. Tpm12PtpCrbWaitRegisterBits (
  417. IN UINT32 *Register,
  418. IN UINT32 BitSet,
  419. IN UINT32 BitClear,
  420. IN UINT32 TimeOut
  421. )
  422. {
  423. UINT32 RegRead;
  424. UINT32 WaitTime;
  425. for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
  426. RegRead = MmioRead32 ((UINTN)Register);
  427. if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {
  428. return EFI_SUCCESS;
  429. }
  430. MicroSecondDelay (30);
  431. }
  432. return EFI_TIMEOUT;
  433. }
  434. /**
  435. Get the control of TPM chip.
  436. @param[in] CrbReg Pointer to CRB register.
  437. @retval EFI_SUCCESS Get the control of TPM chip.
  438. @retval EFI_INVALID_PARAMETER CrbReg is NULL.
  439. @retval EFI_NOT_FOUND TPM chip doesn't exit.
  440. @retval EFI_TIMEOUT Can't get the TPM control in time.
  441. **/
  442. EFI_STATUS
  443. Tpm12PtpCrbRequestUseTpm (
  444. IN PTP_CRB_REGISTERS_PTR CrbReg
  445. )
  446. {
  447. EFI_STATUS Status;
  448. MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);
  449. Status = Tpm12PtpCrbWaitRegisterBits (
  450. &CrbReg->LocalityStatus,
  451. PTP_CRB_LOCALITY_STATUS_GRANTED,
  452. 0,
  453. PTP_TIMEOUT_A
  454. );
  455. return Status;
  456. }
  457. /**
  458. This service requests use TPM12.
  459. @retval EFI_SUCCESS Get the control of TPM12 chip.
  460. @retval EFI_NOT_FOUND TPM12 not found.
  461. @retval EFI_DEVICE_ERROR Unexpected device behavior.
  462. **/
  463. EFI_STATUS
  464. EFIAPI
  465. Tpm12RequestUseTpm (
  466. VOID
  467. )
  468. {
  469. PTP_INTERFACE_TYPE PtpInterface;
  470. //
  471. // Special handle for TPM1.2 to check PTP too, because PTP/TIS share same register address.
  472. // Some other program might leverage this function to check the existence of TPM chip.
  473. //
  474. PtpInterface = Tpm12GetPtpInterface ((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));
  475. switch (PtpInterface) {
  476. case PtpInterfaceCrb:
  477. return Tpm12PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
  478. case PtpInterfaceFifo:
  479. case PtpInterfaceTis:
  480. return Tpm12TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
  481. default:
  482. return EFI_NOT_FOUND;
  483. }
  484. }