TpmCommLib.h 8.1 KB

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  1. /** @file
  2. This library is only intended to be used by TPM modules.
  3. It provides basic TPM Interface Specification (TIS) and Command functions.
  4. Copyright (c) 2005 - 2018, Intel Corporation. All rights reserved.<BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #ifndef _TPM_COMM_LIB_H_
  8. #define _TPM_COMM_LIB_H_
  9. #include <IndustryStandard/Tpm12.h>
  10. typedef EFI_HANDLE TIS_TPM_HANDLE;
  11. ///
  12. /// TPM register base address.
  13. ///
  14. #define TPM_BASE_ADDRESS 0xfed40000
  15. //
  16. // Set structure alignment to 1-byte
  17. //
  18. #pragma pack (1)
  19. //
  20. // Register set map as specified in TIS specification Chapter 10
  21. //
  22. typedef struct {
  23. ///
  24. /// Used to gain ownership for this particular port.
  25. ///
  26. UINT8 Access; // 0
  27. UINT8 Reserved1[7]; // 1
  28. ///
  29. /// Controls interrupts.
  30. ///
  31. UINT32 IntEnable; // 8
  32. ///
  33. /// SIRQ vector to be used by the TPM.
  34. ///
  35. UINT8 IntVector; // 0ch
  36. UINT8 Reserved2[3]; // 0dh
  37. ///
  38. /// What caused interrupt.
  39. ///
  40. UINT32 IntSts; // 10h
  41. ///
  42. /// Shows which interrupts are supported by that particular TPM.
  43. ///
  44. UINT32 IntfCapability; // 14h
  45. ///
  46. /// Status Register. Provides status of the TPM.
  47. ///
  48. UINT8 Status; // 18h
  49. ///
  50. /// Number of consecutive writes that can be done to the TPM.
  51. ///
  52. UINT16 BurstCount; // 19h
  53. UINT8 Reserved3[9];
  54. ///
  55. /// Read or write FIFO, depending on transaction.
  56. ///
  57. UINT32 DataFifo; // 24
  58. UINT8 Reserved4[0xed8]; // 28h
  59. ///
  60. /// Vendor ID
  61. ///
  62. UINT16 Vid; // 0f00h
  63. ///
  64. /// Device ID
  65. ///
  66. UINT16 Did; // 0f02h
  67. ///
  68. /// Revision ID
  69. ///
  70. UINT8 Rid; // 0f04h
  71. ///
  72. /// TCG defined configuration registers.
  73. ///
  74. UINT8 TcgDefined[0x7b]; // 0f05h
  75. ///
  76. /// Alias to I/O legacy space.
  77. ///
  78. UINT32 LegacyAddress1; // 0f80h
  79. ///
  80. /// Additional 8 bits for I/O legacy space extension.
  81. ///
  82. UINT32 LegacyAddress1Ex; // 0f84h
  83. ///
  84. /// Alias to second I/O legacy space.
  85. ///
  86. UINT32 LegacyAddress2; // 0f88h
  87. ///
  88. /// Additional 8 bits for second I/O legacy space extension.
  89. ///
  90. UINT32 LegacyAddress2Ex; // 0f8ch
  91. ///
  92. /// Vendor-defined configuration registers.
  93. ///
  94. UINT8 VendorDefined[0x70];// 0f90h
  95. } TIS_PC_REGISTERS;
  96. //
  97. // Restore original structure alignment
  98. //
  99. #pragma pack ()
  100. //
  101. // Define pointer types used to access TIS registers on PC
  102. //
  103. typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;
  104. //
  105. // TCG Platform Type based on TCG ACPI Specification Version 1.00
  106. //
  107. #define TCG_PLATFORM_TYPE_CLIENT 0
  108. #define TCG_PLATFORM_TYPE_SERVER 1
  109. //
  110. // Define bits of ACCESS and STATUS registers
  111. //
  112. ///
  113. /// This bit is a 1 to indicate that the other bits in this register are valid.
  114. ///
  115. #define TIS_PC_VALID BIT7
  116. ///
  117. /// Indicate that this locality is active.
  118. ///
  119. #define TIS_PC_ACC_ACTIVE BIT5
  120. ///
  121. /// Set to 1 to indicate that this locality had the TPM taken away while
  122. /// this locality had the TIS_PC_ACC_ACTIVE bit set.
  123. ///
  124. #define TIS_PC_ACC_SEIZED BIT4
  125. ///
  126. /// Set to 1 to indicate that TPM MUST reset the
  127. /// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
  128. /// locality that is writing this bit.
  129. ///
  130. #define TIS_PC_ACC_SEIZE BIT3
  131. ///
  132. /// When this bit is 1, another locality is requesting usage of the TPM.
  133. ///
  134. #define TIS_PC_ACC_PENDIND BIT2
  135. ///
  136. /// Set to 1 to indicate that this locality is requesting to use TPM.
  137. ///
  138. #define TIS_PC_ACC_RQUUSE BIT1
  139. ///
  140. /// A value of 1 indicates that a T/OS has not been established on the platform
  141. ///
  142. #define TIS_PC_ACC_ESTABLISH BIT0
  143. ///
  144. /// When this bit is 1, TPM is in the Ready state,
  145. /// indicating it is ready to receive a new command.
  146. ///
  147. #define TIS_PC_STS_READY BIT6
  148. ///
  149. /// Write a 1 to this bit to cause the TPM to execute that command.
  150. ///
  151. #define TIS_PC_STS_GO BIT5
  152. ///
  153. /// This bit indicates that the TPM has data available as a response.
  154. ///
  155. #define TIS_PC_STS_DATA BIT4
  156. ///
  157. /// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
  158. ///
  159. #define TIS_PC_STS_EXPECT BIT3
  160. ///
  161. /// Writes a 1 to this bit to force the TPM to re-send the response.
  162. ///
  163. #define TIS_PC_STS_RETRY BIT1
  164. //
  165. // Default TimeOut value
  166. //
  167. #define TIS_TIMEOUT_A 750 * 1000 // 750ms
  168. #define TIS_TIMEOUT_B 2000 * 1000 // 2s
  169. #define TIS_TIMEOUT_C 750 * 1000 // 750ms
  170. #define TIS_TIMEOUT_D 750 * 1000 // 750ms
  171. //
  172. // Max TPM command/reponse length
  173. //
  174. #define TPMCMDBUFLENGTH 1024
  175. /**
  176. Check whether the value of a TPM chip register satisfies the input BIT setting.
  177. @param[in] Register Address port of register to be checked.
  178. @param[in] BitSet Check these data bits are set.
  179. @param[in] BitClear Check these data bits are clear.
  180. @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.
  181. @retval EFI_SUCCESS The register satisfies the check bit.
  182. @retval EFI_TIMEOUT The register can't run into the expected status in time.
  183. **/
  184. EFI_STATUS
  185. EFIAPI
  186. TisPcWaitRegisterBits (
  187. IN UINT8 *Register,
  188. IN UINT8 BitSet,
  189. IN UINT8 BitClear,
  190. IN UINT32 TimeOut
  191. );
  192. /**
  193. Get BurstCount by reading the burstCount field of a TIS regiger
  194. in the time of default TIS_TIMEOUT_D.
  195. @param[in] TisReg Pointer to TIS register.
  196. @param[out] BurstCount Pointer to a buffer to store the got BurstCount.
  197. @retval EFI_SUCCESS Get BurstCount.
  198. @retval EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.
  199. @retval EFI_TIMEOUT BurstCount can't be got in time.
  200. **/
  201. EFI_STATUS
  202. EFIAPI
  203. TisPcReadBurstCount (
  204. IN TIS_PC_REGISTERS_PTR TisReg,
  205. OUT UINT16 *BurstCount
  206. );
  207. /**
  208. Set TPM chip to ready state by sending ready command TIS_PC_STS_READY
  209. to Status Register in time.
  210. @param[in] TisReg Pointer to TIS register.
  211. @retval EFI_SUCCESS TPM chip enters into ready state.
  212. @retval EFI_INVALID_PARAMETER TisReg is NULL.
  213. @retval EFI_TIMEOUT TPM chip can't be set to ready state in time.
  214. **/
  215. EFI_STATUS
  216. EFIAPI
  217. TisPcPrepareCommand (
  218. IN TIS_PC_REGISTERS_PTR TisReg
  219. );
  220. /**
  221. Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE
  222. to ACCESS Register in the time of default TIS_TIMEOUT_D.
  223. @param[in] TisReg Pointer to TIS register.
  224. @retval EFI_SUCCESS Get the control of TPM chip.
  225. @retval EFI_INVALID_PARAMETER TisReg is NULL.
  226. @retval EFI_NOT_FOUND TPM chip doesn't exit.
  227. @retval EFI_TIMEOUT Can't get the TPM control in time.
  228. **/
  229. EFI_STATUS
  230. EFIAPI
  231. TisPcRequestUseTpm (
  232. IN TIS_PC_REGISTERS_PTR TisReg
  233. );
  234. /**
  235. Single function calculates SHA1 digest value for all raw data. It
  236. combines Sha1Init(), Sha1Update() and Sha1Final().
  237. @param[in] Data Raw data to be digested.
  238. @param[in] DataLen Size of the raw data.
  239. @param[out] Digest Pointer to a buffer that stores the final digest.
  240. @retval EFI_SUCCESS Always successfully calculate the final digest.
  241. **/
  242. EFI_STATUS
  243. EFIAPI
  244. TpmCommHashAll (
  245. IN CONST UINT8 *Data,
  246. IN UINTN DataLen,
  247. OUT TPM_DIGEST *Digest
  248. );
  249. #endif