ArmLib.h 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793
  1. /** @file
  2. Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
  3. Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
  4. Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #ifndef ARM_LIB_H_
  8. #define ARM_LIB_H_
  9. #include <Uefi/UefiBaseType.h>
  10. #ifdef MDE_CPU_ARM
  11. #include <Chipset/ArmV7.h>
  12. #elif defined (MDE_CPU_AARCH64)
  13. #include <Chipset/AArch64.h>
  14. #else
  15. #error "Unknown chipset."
  16. #endif
  17. #define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
  18. EFI_MEMORY_WT | EFI_MEMORY_WB | \
  19. EFI_MEMORY_UCE)
  20. /**
  21. * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
  22. *
  23. * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
  24. * be used in Secure World to distinguished Secure to Non-Secure memory.
  25. */
  26. typedef enum {
  27. ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  28. ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  29. ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  30. ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  31. // On some platforms, memory mapped flash region is designed as not supporting
  32. // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
  33. // need.
  34. // Do NOT use below two attributes if you are not sure.
  35. ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,
  36. ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,
  37. ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  38. ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  39. ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  40. ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
  41. } ARM_MEMORY_REGION_ATTRIBUTES;
  42. #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  43. typedef struct {
  44. EFI_PHYSICAL_ADDRESS PhysicalBase;
  45. EFI_VIRTUAL_ADDRESS VirtualBase;
  46. UINT64 Length;
  47. ARM_MEMORY_REGION_ATTRIBUTES Attributes;
  48. } ARM_MEMORY_REGION_DESCRIPTOR;
  49. typedef VOID (*CACHE_OPERATION)(
  50. VOID
  51. );
  52. typedef VOID (*LINE_OPERATION)(
  53. UINTN
  54. );
  55. //
  56. // ARM Processor Mode
  57. //
  58. typedef enum {
  59. ARM_PROCESSOR_MODE_USER = 0x10,
  60. ARM_PROCESSOR_MODE_FIQ = 0x11,
  61. ARM_PROCESSOR_MODE_IRQ = 0x12,
  62. ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  63. ARM_PROCESSOR_MODE_ABORT = 0x17,
  64. ARM_PROCESSOR_MODE_HYP = 0x1A,
  65. ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,
  66. ARM_PROCESSOR_MODE_SYSTEM = 0x1F,
  67. ARM_PROCESSOR_MODE_MASK = 0x1F
  68. } ARM_PROCESSOR_MODE;
  69. //
  70. // ARM Cpu IDs
  71. //
  72. #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
  73. #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
  74. #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
  75. #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
  76. #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
  77. #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
  78. #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
  79. #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
  80. #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
  81. #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
  82. #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
  83. #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
  84. //
  85. // ARM MP Core IDs
  86. //
  87. #define ARM_CORE_AFF0 0xFF
  88. #define ARM_CORE_AFF1 (0xFF << 8)
  89. #define ARM_CORE_AFF2 (0xFF << 16)
  90. #define ARM_CORE_AFF3 (0xFFULL << 32)
  91. #define ARM_CORE_MASK ARM_CORE_AFF0
  92. #define ARM_CLUSTER_MASK ARM_CORE_AFF1
  93. #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
  94. #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
  95. #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
  96. #define GET_MPIDR_AFF0(MpId) ((MpId) & ARM_CORE_AFF0)
  97. #define GET_MPIDR_AFF1(MpId) (((MpId) & ARM_CORE_AFF1) >> 8)
  98. #define GET_MPIDR_AFF2(MpId) (((MpId) & ARM_CORE_AFF2) >> 16)
  99. #define GET_MPIDR_AFF3(MpId) (((MpId) & ARM_CORE_AFF3) >> 32)
  100. #define GET_MPIDR_AFFINITY_BITS(MpId) ((MpId) & 0xFF00FFFFFF)
  101. #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
  102. #define MPIDR_MT_BIT BIT24
  103. /** Reads the CCSIDR register for the specified cache.
  104. @param CSSELR The CSSELR cache selection register value.
  105. @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
  106. Returns the contents of the CCSIDR register in AARCH32 mode.
  107. **/
  108. UINTN
  109. ReadCCSIDR (
  110. IN UINT32 CSSELR
  111. );
  112. /** Reads the CCSIDR2 for the specified cache.
  113. @param CSSELR The CSSELR cache selection register value
  114. @return The contents of the CCSIDR2 register for the specified cache.
  115. **/
  116. UINT32
  117. ReadCCSIDR2 (
  118. IN UINT32 CSSELR
  119. );
  120. /** Reads the Cache Level ID (CLIDR) register.
  121. @return The contents of the CLIDR_EL1 register.
  122. **/
  123. UINT32
  124. ReadCLIDR (
  125. VOID
  126. );
  127. UINTN
  128. EFIAPI
  129. ArmDataCacheLineLength (
  130. VOID
  131. );
  132. UINTN
  133. EFIAPI
  134. ArmInstructionCacheLineLength (
  135. VOID
  136. );
  137. UINTN
  138. EFIAPI
  139. ArmCacheWritebackGranule (
  140. VOID
  141. );
  142. UINTN
  143. EFIAPI
  144. ArmIsArchTimerImplemented (
  145. VOID
  146. );
  147. UINTN
  148. EFIAPI
  149. ArmCacheInfo (
  150. VOID
  151. );
  152. BOOLEAN
  153. EFIAPI
  154. ArmIsMpCore (
  155. VOID
  156. );
  157. VOID
  158. EFIAPI
  159. ArmInvalidateDataCache (
  160. VOID
  161. );
  162. VOID
  163. EFIAPI
  164. ArmCleanInvalidateDataCache (
  165. VOID
  166. );
  167. VOID
  168. EFIAPI
  169. ArmCleanDataCache (
  170. VOID
  171. );
  172. VOID
  173. EFIAPI
  174. ArmInvalidateInstructionCache (
  175. VOID
  176. );
  177. VOID
  178. EFIAPI
  179. ArmInvalidateDataCacheEntryByMVA (
  180. IN UINTN Address
  181. );
  182. VOID
  183. EFIAPI
  184. ArmCleanDataCacheEntryToPoUByMVA (
  185. IN UINTN Address
  186. );
  187. VOID
  188. EFIAPI
  189. ArmInvalidateInstructionCacheEntryToPoUByMVA (
  190. IN UINTN Address
  191. );
  192. VOID
  193. EFIAPI
  194. ArmCleanDataCacheEntryByMVA (
  195. IN UINTN Address
  196. );
  197. VOID
  198. EFIAPI
  199. ArmCleanInvalidateDataCacheEntryByMVA (
  200. IN UINTN Address
  201. );
  202. VOID
  203. EFIAPI
  204. ArmEnableDataCache (
  205. VOID
  206. );
  207. VOID
  208. EFIAPI
  209. ArmDisableDataCache (
  210. VOID
  211. );
  212. VOID
  213. EFIAPI
  214. ArmEnableInstructionCache (
  215. VOID
  216. );
  217. VOID
  218. EFIAPI
  219. ArmDisableInstructionCache (
  220. VOID
  221. );
  222. VOID
  223. EFIAPI
  224. ArmEnableMmu (
  225. VOID
  226. );
  227. VOID
  228. EFIAPI
  229. ArmDisableMmu (
  230. VOID
  231. );
  232. VOID
  233. EFIAPI
  234. ArmEnableCachesAndMmu (
  235. VOID
  236. );
  237. VOID
  238. EFIAPI
  239. ArmDisableCachesAndMmu (
  240. VOID
  241. );
  242. VOID
  243. EFIAPI
  244. ArmEnableInterrupts (
  245. VOID
  246. );
  247. UINTN
  248. EFIAPI
  249. ArmDisableInterrupts (
  250. VOID
  251. );
  252. BOOLEAN
  253. EFIAPI
  254. ArmGetInterruptState (
  255. VOID
  256. );
  257. VOID
  258. EFIAPI
  259. ArmEnableAsynchronousAbort (
  260. VOID
  261. );
  262. UINTN
  263. EFIAPI
  264. ArmDisableAsynchronousAbort (
  265. VOID
  266. );
  267. VOID
  268. EFIAPI
  269. ArmEnableIrq (
  270. VOID
  271. );
  272. UINTN
  273. EFIAPI
  274. ArmDisableIrq (
  275. VOID
  276. );
  277. VOID
  278. EFIAPI
  279. ArmEnableFiq (
  280. VOID
  281. );
  282. UINTN
  283. EFIAPI
  284. ArmDisableFiq (
  285. VOID
  286. );
  287. BOOLEAN
  288. EFIAPI
  289. ArmGetFiqState (
  290. VOID
  291. );
  292. /**
  293. * Invalidate Data and Instruction TLBs
  294. */
  295. VOID
  296. EFIAPI
  297. ArmInvalidateTlb (
  298. VOID
  299. );
  300. VOID
  301. EFIAPI
  302. ArmUpdateTranslationTableEntry (
  303. IN VOID *TranslationTableEntry,
  304. IN VOID *Mva
  305. );
  306. VOID
  307. EFIAPI
  308. ArmSetDomainAccessControl (
  309. IN UINT32 Domain
  310. );
  311. VOID
  312. EFIAPI
  313. ArmSetTTBR0 (
  314. IN VOID *TranslationTableBase
  315. );
  316. VOID
  317. EFIAPI
  318. ArmSetTTBCR (
  319. IN UINT32 Bits
  320. );
  321. VOID *
  322. EFIAPI
  323. ArmGetTTBR0BaseAddress (
  324. VOID
  325. );
  326. BOOLEAN
  327. EFIAPI
  328. ArmMmuEnabled (
  329. VOID
  330. );
  331. VOID
  332. EFIAPI
  333. ArmEnableBranchPrediction (
  334. VOID
  335. );
  336. VOID
  337. EFIAPI
  338. ArmDisableBranchPrediction (
  339. VOID
  340. );
  341. VOID
  342. EFIAPI
  343. ArmSetLowVectors (
  344. VOID
  345. );
  346. VOID
  347. EFIAPI
  348. ArmSetHighVectors (
  349. VOID
  350. );
  351. VOID
  352. EFIAPI
  353. ArmDataMemoryBarrier (
  354. VOID
  355. );
  356. VOID
  357. EFIAPI
  358. ArmDataSynchronizationBarrier (
  359. VOID
  360. );
  361. VOID
  362. EFIAPI
  363. ArmInstructionSynchronizationBarrier (
  364. VOID
  365. );
  366. VOID
  367. EFIAPI
  368. ArmWriteVBar (
  369. IN UINTN VectorBase
  370. );
  371. UINTN
  372. EFIAPI
  373. ArmReadVBar (
  374. VOID
  375. );
  376. VOID
  377. EFIAPI
  378. ArmWriteAuxCr (
  379. IN UINT32 Bit
  380. );
  381. UINT32
  382. EFIAPI
  383. ArmReadAuxCr (
  384. VOID
  385. );
  386. VOID
  387. EFIAPI
  388. ArmSetAuxCrBit (
  389. IN UINT32 Bits
  390. );
  391. VOID
  392. EFIAPI
  393. ArmUnsetAuxCrBit (
  394. IN UINT32 Bits
  395. );
  396. VOID
  397. EFIAPI
  398. ArmCallSEV (
  399. VOID
  400. );
  401. VOID
  402. EFIAPI
  403. ArmCallWFE (
  404. VOID
  405. );
  406. VOID
  407. EFIAPI
  408. ArmCallWFI (
  409. VOID
  410. );
  411. UINTN
  412. EFIAPI
  413. ArmReadMpidr (
  414. VOID
  415. );
  416. UINTN
  417. EFIAPI
  418. ArmReadMidr (
  419. VOID
  420. );
  421. UINT32
  422. EFIAPI
  423. ArmReadCpacr (
  424. VOID
  425. );
  426. VOID
  427. EFIAPI
  428. ArmWriteCpacr (
  429. IN UINT32 Access
  430. );
  431. VOID
  432. EFIAPI
  433. ArmEnableVFP (
  434. VOID
  435. );
  436. /**
  437. Get the Secure Configuration Register value
  438. @return Value read from the Secure Configuration Register
  439. **/
  440. UINT32
  441. EFIAPI
  442. ArmReadScr (
  443. VOID
  444. );
  445. /**
  446. Set the Secure Configuration Register
  447. @param Value Value to write to the Secure Configuration Register
  448. **/
  449. VOID
  450. EFIAPI
  451. ArmWriteScr (
  452. IN UINT32 Value
  453. );
  454. UINT32
  455. EFIAPI
  456. ArmReadMVBar (
  457. VOID
  458. );
  459. VOID
  460. EFIAPI
  461. ArmWriteMVBar (
  462. IN UINT32 VectorMonitorBase
  463. );
  464. UINT32
  465. EFIAPI
  466. ArmReadSctlr (
  467. VOID
  468. );
  469. VOID
  470. EFIAPI
  471. ArmWriteSctlr (
  472. IN UINT32 Value
  473. );
  474. UINTN
  475. EFIAPI
  476. ArmReadHVBar (
  477. VOID
  478. );
  479. VOID
  480. EFIAPI
  481. ArmWriteHVBar (
  482. IN UINTN HypModeVectorBase
  483. );
  484. //
  485. // Helper functions for accessing CPU ACTLR
  486. //
  487. UINTN
  488. EFIAPI
  489. ArmReadCpuActlr (
  490. VOID
  491. );
  492. VOID
  493. EFIAPI
  494. ArmWriteCpuActlr (
  495. IN UINTN Val
  496. );
  497. VOID
  498. EFIAPI
  499. ArmSetCpuActlrBit (
  500. IN UINTN Bits
  501. );
  502. VOID
  503. EFIAPI
  504. ArmUnsetCpuActlrBit (
  505. IN UINTN Bits
  506. );
  507. //
  508. // Accessors for the architected generic timer registers
  509. //
  510. #define ARM_ARCH_TIMER_ENABLE (1 << 0)
  511. #define ARM_ARCH_TIMER_IMASK (1 << 1)
  512. #define ARM_ARCH_TIMER_ISTATUS (1 << 2)
  513. UINTN
  514. EFIAPI
  515. ArmReadCntFrq (
  516. VOID
  517. );
  518. VOID
  519. EFIAPI
  520. ArmWriteCntFrq (
  521. UINTN FreqInHz
  522. );
  523. UINT64
  524. EFIAPI
  525. ArmReadCntPct (
  526. VOID
  527. );
  528. UINTN
  529. EFIAPI
  530. ArmReadCntkCtl (
  531. VOID
  532. );
  533. VOID
  534. EFIAPI
  535. ArmWriteCntkCtl (
  536. UINTN Val
  537. );
  538. UINTN
  539. EFIAPI
  540. ArmReadCntpTval (
  541. VOID
  542. );
  543. VOID
  544. EFIAPI
  545. ArmWriteCntpTval (
  546. UINTN Val
  547. );
  548. UINTN
  549. EFIAPI
  550. ArmReadCntpCtl (
  551. VOID
  552. );
  553. VOID
  554. EFIAPI
  555. ArmWriteCntpCtl (
  556. UINTN Val
  557. );
  558. UINTN
  559. EFIAPI
  560. ArmReadCntvTval (
  561. VOID
  562. );
  563. VOID
  564. EFIAPI
  565. ArmWriteCntvTval (
  566. UINTN Val
  567. );
  568. UINTN
  569. EFIAPI
  570. ArmReadCntvCtl (
  571. VOID
  572. );
  573. VOID
  574. EFIAPI
  575. ArmWriteCntvCtl (
  576. UINTN Val
  577. );
  578. UINT64
  579. EFIAPI
  580. ArmReadCntvCt (
  581. VOID
  582. );
  583. UINT64
  584. EFIAPI
  585. ArmReadCntpCval (
  586. VOID
  587. );
  588. VOID
  589. EFIAPI
  590. ArmWriteCntpCval (
  591. UINT64 Val
  592. );
  593. UINT64
  594. EFIAPI
  595. ArmReadCntvCval (
  596. VOID
  597. );
  598. VOID
  599. EFIAPI
  600. ArmWriteCntvCval (
  601. UINT64 Val
  602. );
  603. UINT64
  604. EFIAPI
  605. ArmReadCntvOff (
  606. VOID
  607. );
  608. VOID
  609. EFIAPI
  610. ArmWriteCntvOff (
  611. UINT64 Val
  612. );
  613. UINTN
  614. EFIAPI
  615. ArmGetPhysicalAddressBits (
  616. VOID
  617. );
  618. ///
  619. /// ID Register Helper functions
  620. ///
  621. /**
  622. Check whether the CPU supports the GIC system register interface (any version)
  623. @return Whether GIC System Register Interface is supported
  624. **/
  625. BOOLEAN
  626. EFIAPI
  627. ArmHasGicSystemRegisters (
  628. VOID
  629. );
  630. /** Checks if CCIDX is implemented.
  631. @retval TRUE CCIDX is implemented.
  632. @retval FALSE CCIDX is not implemented.
  633. **/
  634. BOOLEAN
  635. EFIAPI
  636. ArmHasCcidx (
  637. VOID
  638. );
  639. #ifdef MDE_CPU_ARM
  640. ///
  641. /// AArch32-only ID Register Helper functions
  642. ///
  643. /**
  644. Check whether the CPU supports the Security extensions
  645. @return Whether the Security extensions are implemented
  646. **/
  647. BOOLEAN
  648. EFIAPI
  649. ArmHasSecurityExtensions (
  650. VOID
  651. );
  652. #endif // MDE_CPU_ARM
  653. #endif // ARM_LIB_H_