ArmNameSpaceObjects.h 18 KB

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  1. /** @file
  2. Copyright (c) 2017 - 2019, ARM Limited. All rights reserved.
  3. This program and the accompanying materials
  4. are licensed and made available under the terms and conditions of the BSD License
  5. which accompanies this distribution. The full text of the license may be found at
  6. http://opensource.org/licenses/bsd-license.php
  7. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  8. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  9. @par Glossary:
  10. - Cm or CM - Configuration Manager
  11. - Obj or OBJ - Object
  12. - Std or STD - Standard
  13. **/
  14. #ifndef ARM_NAMESPACE_OBJECTS_H_
  15. #define ARM_NAMESPACE_OBJECTS_H_
  16. #include <StandardNameSpaceObjects.h>
  17. #pragma pack(1)
  18. /** The EARM_OBJECT_ID enum describes the Object IDs
  19. in the ARM Namespace
  20. */
  21. typedef enum ArmObjectID {
  22. EArmObjReserved, ///< 0 - Reserved
  23. EArmObjBootArchInfo, ///< 1 - Boot Architecture Info
  24. EArmObjCpuInfo, ///< 2 - CPU Info
  25. EArmObjPowerManagementProfileInfo, ///< 3 - Power Management Profile Info
  26. EArmObjGicCInfo, ///< 4 - GIC CPU Interface Info
  27. EArmObjGicDInfo, ///< 5 - GIC Distributor Info
  28. EArmObjGicMsiFrameInfo, ///< 6 - GIC MSI Frame Info
  29. EArmObjGicRedistributorInfo, ///< 7 - GIC Redistributor Info
  30. EArmObjGicItsInfo, ///< 8 - GIC ITS Info
  31. EArmObjSerialConsolePortInfo, ///< 9 - Serial Console Port Info
  32. EArmObjSerialDebugPortInfo, ///< 10 - Serial Debug Port Info
  33. EArmObjGenericTimerInfo, ///< 11 - Generic Timer Info
  34. EArmObjPlatformGTBlockInfo, ///< 12 - Platform GT Block Info
  35. EArmObjGTBlockTimerFrameInfo, ///< 13 - Generic Timer Block Frame Info
  36. EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog
  37. EArmObjPciConfigSpaceInfo, ///< 15 - PCI Configuration Space Info
  38. EArmObjHypervisorVendorIdentity, ///< 16 - Hypervisor Vendor Id
  39. EArmObjFixedFeatureFlags, ///< 17 - Fixed feature flags for FADT
  40. EArmObjItsGroup, ///< 18 - ITS Group
  41. EArmObjNamedComponent, ///< 19 - Named Component
  42. EArmObjRootComplex, ///< 20 - Root Complex
  43. EArmObjSmmuV1SmmuV2, ///< 21 - SMMUv1 or SMMUv2
  44. EArmObjSmmuV3, ///< 22 - SMMUv3
  45. EArmObjPmcg, ///< 23 - PMCG
  46. EArmObjGicItsIdentifierArray, ///< 24 - GIC ITS Identifier Array
  47. EArmObjIdMappingArray, ///< 25 - ID Mapping Array
  48. EArmObjSmmuInterruptArray, ///< 26 - SMMU Interrupt Array
  49. EArmObjMax
  50. } EARM_OBJECT_ID;
  51. /** A structure that describes the
  52. ARM Boot Architecture flags.
  53. ID: EArmObjBootArchInfo
  54. */
  55. typedef struct CmArmBootArchInfo {
  56. /** This is the ARM_BOOT_ARCH flags field of the FADT Table
  57. described in the ACPI Table Specification.
  58. */
  59. UINT32 BootArchFlags;
  60. } CM_ARM_BOOT_ARCH_INFO;
  61. typedef struct CmArmCpuInfo {
  62. // Reserved for use when SMBIOS tables are implemented
  63. } CM_ARM_CPU_INFO;
  64. /** A structure that describes the
  65. Power Management Profile Information for the Platform.
  66. ID: EArmObjPowerManagementProfileInfo
  67. */
  68. typedef struct CmArmPowerManagementProfileInfo {
  69. /** This is the Preferred_PM_Profile field of the FADT Table
  70. described in the ACPI Specification
  71. */
  72. UINT8 PowerManagementProfile;
  73. } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;
  74. /** A structure that describes the
  75. GIC CPU Interface for the Platform.
  76. ID: EArmObjGicCInfo
  77. */
  78. typedef struct CmArmGicCInfo {
  79. /// The GIC CPU Interface number.
  80. UINT32 CPUInterfaceNumber;
  81. /** The ACPI Processor UID. This must match the
  82. _UID of the CPU Device object information described
  83. in the DSDT/SSDT for the CPU.
  84. */
  85. UINT32 AcpiProcessorUid;
  86. /** The flags field as described by the GICC structure
  87. in the ACPI Specification.
  88. */
  89. UINT32 Flags;
  90. /** The parking protocol version field as described by
  91. the GICC structure in the ACPI Specification.
  92. */
  93. UINT32 ParkingProtocolVersion;
  94. /** The Performance Interrupt field as described by
  95. the GICC structure in the ACPI Specification.
  96. */
  97. UINT32 PerformanceInterruptGsiv;
  98. /** The CPU Parked address field as described by
  99. the GICC structure in the ACPI Specification.
  100. */
  101. UINT64 ParkedAddress;
  102. /** The base address for the GIC CPU Interface
  103. as described by the GICC structure in the
  104. ACPI Specification.
  105. */
  106. UINT64 PhysicalBaseAddress;
  107. /** The base address for GICV interface
  108. as described by the GICC structure in the
  109. ACPI Specification.
  110. */
  111. UINT64 GICV;
  112. /** The base address for GICH interface
  113. as described by the GICC structure in the
  114. ACPI Specification.
  115. */
  116. UINT64 GICH;
  117. /** The GICV maintenance interrupt
  118. as described by the GICC structure in the
  119. ACPI Specification.
  120. */
  121. UINT32 VGICMaintenanceInterrupt;
  122. /** The base address for GICR interface
  123. as described by the GICC structure in the
  124. ACPI Specification.
  125. */
  126. UINT64 GICRBaseAddress;
  127. /** The MPIDR for the CPU
  128. as described by the GICC structure in the
  129. ACPI Specification.
  130. */
  131. UINT64 MPIDR;
  132. /** The Processor Power Efficiency class
  133. as described by the GICC structure in the
  134. ACPI Specification.
  135. */
  136. UINT8 ProcessorPowerEfficiencyClass;
  137. } CM_ARM_GICC_INFO;
  138. /** A structure that describes the
  139. GIC Distributor information for the Platform.
  140. ID: EArmObjGicDInfo
  141. */
  142. typedef struct CmArmGicDInfo {
  143. /// The Physical Base address for the GIC Distributor.
  144. UINT64 PhysicalBaseAddress;
  145. /** The global system interrupt
  146. number where this GIC Distributor's
  147. interrupt inputs start.
  148. */
  149. UINT32 SystemVectorBase;
  150. /** The GIC version as described
  151. by the GICD structure in the
  152. ACPI Specification.
  153. */
  154. UINT8 GicVersion;
  155. } CM_ARM_GICD_INFO;
  156. /** A structure that describes the
  157. GIC MSI Frame information for the Platform.
  158. ID: EArmObjGicMsiFrameInfo
  159. */
  160. typedef struct CmArmGicMsiFrameInfo {
  161. /// The GIC MSI Frame ID
  162. UINT32 GicMsiFrameId;
  163. /// The Physical base address for the MSI Frame
  164. UINT64 PhysicalBaseAddress;
  165. /** The GIC MSI Frame flags
  166. as described by the GIC MSI frame
  167. structure in the ACPI Specification.
  168. */
  169. UINT32 Flags;
  170. /// SPI Count used by this frame
  171. UINT16 SPICount;
  172. /// SPI Base used by this frame
  173. UINT16 SPIBase;
  174. } CM_ARM_GIC_MSI_FRAME_INFO;
  175. /** A structure that describes the
  176. GIC Redistributor information for the Platform.
  177. ID: EArmObjGicRedistributorInfo
  178. */
  179. typedef struct CmArmGicRedistInfo {
  180. /** The physical address of a page range
  181. containing all GIC Redistributors.
  182. */
  183. UINT64 DiscoveryRangeBaseAddress;
  184. /// Length of the GIC Redistributor Discovery page range
  185. UINT32 DiscoveryRangeLength;
  186. } CM_ARM_GIC_REDIST_INFO;
  187. /** A structure that describes the
  188. GIC Interrupt Translation Service information for the Platform.
  189. ID: EArmObjGicItsInfo
  190. */
  191. typedef struct CmArmGicItsInfo {
  192. /// The GIC ITS ID
  193. UINT32 GicItsId;
  194. /// The physical address for the Interrupt Translation Service
  195. UINT64 PhysicalBaseAddress;
  196. } CM_ARM_GIC_ITS_INFO;
  197. /** A structure that describes the
  198. Serial Port information for the Platform.
  199. ID: EArmObjSerialConsolePortInfo or
  200. EArmObjSerialDebugPortInfo
  201. */
  202. typedef struct CmArmSerialPortInfo {
  203. /// The physical base address for the serial port
  204. UINT64 BaseAddress;
  205. /// The serial port interrupt
  206. UINT32 Interrupt;
  207. /// The serial port baud rate
  208. UINT64 BaudRate;
  209. /// The serial port clock
  210. UINT32 Clock;
  211. /// Serial Port subtype
  212. UINT16 PortSubtype;
  213. } CM_ARM_SERIAL_PORT_INFO;
  214. /** A structure that describes the
  215. Generic Timer information for the Platform.
  216. ID: EArmObjGenericTimerInfo
  217. */
  218. typedef struct CmArmGenericTimerInfo {
  219. /// The physical base address for the counter control frame
  220. UINT64 CounterControlBaseAddress;
  221. /// The physical base address for the counter read frame
  222. UINT64 CounterReadBaseAddress;
  223. /// The secure PL1 timer interrupt
  224. UINT32 SecurePL1TimerGSIV;
  225. /// The secure PL1 timer flags
  226. UINT32 SecurePL1TimerFlags;
  227. /// The non-secure PL1 timer interrupt
  228. UINT32 NonSecurePL1TimerGSIV;
  229. /// The non-secure PL1 timer flags
  230. UINT32 NonSecurePL1TimerFlags;
  231. /// The virtual timer interrupt
  232. UINT32 VirtualTimerGSIV;
  233. /// The virtual timer flags
  234. UINT32 VirtualTimerFlags;
  235. /// The non-secure PL2 timer interrupt
  236. UINT32 NonSecurePL2TimerGSIV;
  237. /// The non-secure PL2 timer flags
  238. UINT32 NonSecurePL2TimerFlags;
  239. } CM_ARM_GENERIC_TIMER_INFO;
  240. /** A structure that describes the
  241. Platform Generic Block Timer Frame information for the Platform.
  242. ID: EArmObjGTBlockTimerFrameInfo
  243. */
  244. typedef struct CmArmGTBlockTimerFrameInfo {
  245. /// The Generic Timer frame number
  246. UINT8 FrameNumber;
  247. /// The physical base address for the CntBase block
  248. UINT64 PhysicalAddressCntBase;
  249. /// The physical base address for the CntEL0Base block
  250. UINT64 PhysicalAddressCntEL0Base;
  251. /// The physical timer interrupt
  252. UINT32 PhysicalTimerGSIV;
  253. /** The physical timer flags as described by the GT Block
  254. Timer frame Structure in the ACPI Specification.
  255. */
  256. UINT32 PhysicalTimerFlags;
  257. /// The virtual timer interrupt
  258. UINT32 VirtualTimerGSIV;
  259. /** The virtual timer flags as described by the GT Block
  260. Timer frame Structure in the ACPI Specification.
  261. */
  262. UINT32 VirtualTimerFlags;
  263. /** The common timer flags as described by the GT Block
  264. Timer frame Structure in the ACPI Specification.
  265. */
  266. UINT32 CommonFlags;
  267. } CM_ARM_GTBLOCK_TIMER_FRAME_INFO;
  268. /** A structure that describes the
  269. Platform Generic Block Timer information for the Platform.
  270. ID: EArmObjPlatformGTBlockInfo
  271. */
  272. typedef struct CmArmGTBlockInfo {
  273. /// The physical base address for the GT Block Timer structure
  274. UINT64 GTBlockPhysicalAddress;
  275. /// The number of timer frames implemented in the GT Block
  276. UINT32 GTBlockTimerFrameCount;
  277. /// Reference token for the GT Block timer frame list
  278. CM_OBJECT_TOKEN GTBlockTimerFrameToken;
  279. } CM_ARM_GTBLOCK_INFO;
  280. /** A structure that describes the
  281. SBSA Generic Watchdog information for the Platform.
  282. ID: EArmObjPlatformGenericWatchdogInfo
  283. */
  284. typedef struct CmArmGenericWatchdogInfo {
  285. /// The physical base address of the SBSA Watchdog control frame
  286. UINT64 ControlFrameAddress;
  287. /// The physical base address of the SBSA Watchdog refresh frame
  288. UINT64 RefreshFrameAddress;
  289. /// The watchdog interrupt
  290. UINT32 TimerGSIV;
  291. /** The flags for the watchdog as described by the SBSA watchdog
  292. structure in the ACPI specification.
  293. */
  294. UINT32 Flags;
  295. } CM_ARM_GENERIC_WATCHDOG_INFO;
  296. /** A structure that describes the
  297. PCI Configuration Space information for the Platform.
  298. ID: EArmObjPciConfigSpaceInfo
  299. */
  300. typedef struct CmArmPciConfigSpaceInfo {
  301. /// The physical base address for the PCI segment
  302. UINT64 BaseAddress;
  303. /// The PCI segment group number
  304. UINT16 PciSegmentGroupNumber;
  305. /// The start bus number
  306. UINT8 StartBusNumber;
  307. /// The end bus number
  308. UINT8 EndBusNumber;
  309. } CM_ARM_PCI_CONFIG_SPACE_INFO;
  310. /** A structure that describes the
  311. Hypervisor Vendor ID information for the Platform.
  312. ID: EArmObjHypervisorVendorIdentity
  313. */
  314. typedef struct CmArmHypervisorVendorId {
  315. /// The hypervisor Vendor ID
  316. UINT64 HypervisorVendorId;
  317. } CM_ARM_HYPERVISOR_VENDOR_ID;
  318. /** A structure that describes the
  319. Fixed feature flags for the Platform.
  320. ID: EArmObjFixedFeatureFlags
  321. */
  322. typedef struct CmArmFixedFeatureFlags {
  323. /// The Fixed feature flags
  324. UINT32 Flags;
  325. } CM_ARM_FIXED_FEATURE_FLAGS;
  326. /** A structure that describes the
  327. ITS Group node for the Platform.
  328. ID: EArmObjItsGroup
  329. */
  330. typedef struct CmArmItsGroupNode {
  331. /// An unique token used to identify this object
  332. CM_OBJECT_TOKEN Token;
  333. /// The number of ITS identifiers in the ITS node
  334. UINT32 ItsIdCount;
  335. /// Reference token for the ITS identifier array
  336. CM_OBJECT_TOKEN ItsIdToken;
  337. } CM_ARM_ITS_GROUP_NODE;
  338. /** A structure that describes the
  339. GIC ITS Identifiers for an ITS Group node.
  340. ID: EArmObjGicItsIdentifierArray
  341. */
  342. typedef struct CmArmGicItsIdentifier {
  343. /// The ITS Identifier
  344. UINT32 ItsId;
  345. } CM_ARM_ITS_IDENTIFIER;
  346. /** A structure that describes the
  347. Named component node for the Platform.
  348. ID: EArmObjNamedComponent
  349. */
  350. typedef struct CmArmNamedComponentNode {
  351. /// An unique token used to identify this object
  352. CM_OBJECT_TOKEN Token;
  353. /// Number of ID mappings
  354. UINT32 IdMappingCount;
  355. /// Reference token for the ID mapping array
  356. CM_OBJECT_TOKEN IdMappingToken;
  357. /// Flags for the named component
  358. UINT32 Flags;
  359. /// Memory access properties : Cache coherent attributes
  360. UINT32 CacheCoherent;
  361. /// Memory access properties : Allocation hints
  362. UINT8 AllocationHints;
  363. /// Memory access properties : Memory access flags
  364. UINT8 MemoryAccessFlags;
  365. /// Memory access properties : Address size limit
  366. UINT8 AddressSizeLimit;
  367. /** ASCII Null terminated string with the full path to
  368. the entry in the namespace for this object.
  369. */
  370. CHAR8* ObjectName;
  371. } CM_ARM_NAMED_COMPONENT_NODE;
  372. /** A structure that describes the
  373. Root complex node for the Platform.
  374. ID: EArmObjRootComplex
  375. */
  376. typedef struct CmArmRootComplexNode {
  377. /// An unique token used to identify this object
  378. CM_OBJECT_TOKEN Token;
  379. /// Number of ID mappings
  380. UINT32 IdMappingCount;
  381. /// Reference token for the ID mapping array
  382. CM_OBJECT_TOKEN IdMappingToken;
  383. /// Memory access properties : Cache coherent attributes
  384. UINT32 CacheCoherent;
  385. /// Memory access properties : Allocation hints
  386. UINT8 AllocationHints;
  387. /// Memory access properties : Memory access flags
  388. UINT8 MemoryAccessFlags;
  389. /// ATS attributes
  390. UINT32 AtsAttribute;
  391. /// PCI segment number
  392. UINT32 PciSegmentNumber;
  393. /// Memory address size limit
  394. UINT8 MemoryAddressSize;
  395. } CM_ARM_ROOT_COMPLEX_NODE;
  396. /** A structure that describes the
  397. SMMUv1 or SMMUv2 node for the Platform.
  398. ID: EArmObjSmmuV1SmmuV2
  399. */
  400. typedef struct CmArmSmmuV1SmmuV2Node {
  401. /// An unique token used to identify this object
  402. CM_OBJECT_TOKEN Token;
  403. /// Number of ID mappings
  404. UINT32 IdMappingCount;
  405. /// Reference token for the ID mapping array
  406. CM_OBJECT_TOKEN IdMappingToken;
  407. /// SMMU Base Address
  408. UINT64 BaseAddress;
  409. /// Length of the memory range covered by the SMMU
  410. UINT64 Span;
  411. /// SMMU Model
  412. UINT32 Model;
  413. /// SMMU flags
  414. UINT32 Flags;
  415. /// Number of context interrupts
  416. UINT32 ContextInterruptCount;
  417. /// Reference token for the context interrupt array
  418. CM_OBJECT_TOKEN ContextInterruptToken;
  419. /// Number of PMU interrupts
  420. UINT32 PmuInterruptCount;
  421. /// Reference token for the PMU interrupt array
  422. CM_OBJECT_TOKEN PmuInterruptToken;
  423. /// GSIV of the SMMU_NSgIrpt interrupt
  424. UINT32 SMMU_NSgIrpt;
  425. /// SMMU_NSgIrpt interrupt flags
  426. UINT32 SMMU_NSgIrptFlags;
  427. /// GSIV of the SMMU_NSgCfgIrpt interrupt
  428. UINT32 SMMU_NSgCfgIrpt;
  429. /// SMMU_NSgCfgIrpt interrupt flags
  430. UINT32 SMMU_NSgCfgIrptFlags;
  431. } CM_ARM_SMMUV1_SMMUV2_NODE;
  432. /** A structure that describes the
  433. SMMUv3 node for the Platform.
  434. ID: EArmObjSmmuV3
  435. */
  436. typedef struct CmArmSmmuV3Node {
  437. /// An unique token used to identify this object
  438. CM_OBJECT_TOKEN Token;
  439. /// Number of ID mappings
  440. UINT32 IdMappingCount;
  441. /// Reference token for the ID mapping array
  442. CM_OBJECT_TOKEN IdMappingToken;
  443. /// SMMU Base Address
  444. UINT64 BaseAddress;
  445. /// SMMU flags
  446. UINT32 Flags;
  447. /// VATOS address
  448. UINT64 VatosAddress;
  449. /// Model
  450. UINT32 Model;
  451. /// GSIV of the Event interrupt if SPI based
  452. UINT32 EventInterrupt;
  453. /// PRI Interrupt if SPI based
  454. UINT32 PriInterrupt;
  455. /// GERR interrupt if GSIV based
  456. UINT32 GerrInterrupt;
  457. /// Sync interrupt if GSIV based
  458. UINT32 SyncInterrupt;
  459. /// Proximity domain flag
  460. UINT32 ProximityDomain;
  461. /// Index into the array of ID mapping
  462. UINT32 DeviceIdMappingIndex;
  463. } CM_ARM_SMMUV3_NODE;
  464. /** A structure that describes the
  465. PMCG node for the Platform.
  466. ID: EArmObjPmcg
  467. */
  468. typedef struct CmArmPmcgNode {
  469. /// An unique token used to identify this object
  470. CM_OBJECT_TOKEN Token;
  471. /// Number of ID mappings
  472. UINT32 IdMappingCount;
  473. /// Reference token for the ID mapping array
  474. CM_OBJECT_TOKEN IdMappingToken;
  475. /// Base Address for performance monitor counter group
  476. UINT64 BaseAddress;
  477. /// GSIV for the Overflow interrupt
  478. UINT32 OverflowInterrupt;
  479. /// Page 1 Base address
  480. UINT64 Page1BaseAddress;
  481. /// Reference token for the IORT node associated with this node
  482. CM_OBJECT_TOKEN ReferenceToken;
  483. } CM_ARM_PMCG_NODE;
  484. /** A structure that describes the
  485. ID Mappings for the Platform.
  486. ID: EArmObjIdMappingArray
  487. */
  488. typedef struct CmArmIdMapping {
  489. /// Input base
  490. UINT32 InputBase;
  491. /// Number of input IDs
  492. UINT32 NumIds;
  493. /// Output Base
  494. UINT32 OutputBase;
  495. /// Reference token for the output node
  496. CM_OBJECT_TOKEN OutputReferenceToken;
  497. /// Flags
  498. UINT32 Flags;
  499. } CM_ARM_ID_MAPPING;
  500. /** A structure that describes the
  501. SMMU interrupts for the Platform.
  502. ID: EArmObjSmmuInterruptArray
  503. */
  504. typedef struct CmArmSmmuInterrupt {
  505. /// Interrupt number
  506. UINT32 Interrupt;
  507. /// Flags
  508. UINT32 Flags;
  509. } CM_ARM_SMMU_INTERRUPT;
  510. #pragma pack()
  511. #endif // ARM_NAMESPACE_OBJECTS_H_