Tpm12Tis.c 16 KB

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  1. /** @file
  2. TIS (TPM Interface Specification) functions used by TPM1.2.
  3. Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
  4. (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #include <Uefi.h>
  8. #include <IndustryStandard/Tpm12.h>
  9. #include <Library/BaseLib.h>
  10. #include <Library/BaseMemoryLib.h>
  11. #include <Library/IoLib.h>
  12. #include <Library/TimerLib.h>
  13. #include <Library/DebugLib.h>
  14. #include <Library/Tpm12CommandLib.h>
  15. #include <Library/PcdLib.h>
  16. #include <IndustryStandard/TpmPtp.h>
  17. #include <IndustryStandard/TpmTis.h>
  18. typedef enum {
  19. PtpInterfaceTis,
  20. PtpInterfaceFifo,
  21. PtpInterfaceCrb,
  22. PtpInterfaceMax,
  23. } PTP_INTERFACE_TYPE;
  24. //
  25. // Max TPM command/response length
  26. //
  27. #define TPMCMDBUFLENGTH 1024
  28. /**
  29. Check whether TPM chip exist.
  30. @param[in] TisReg Pointer to TIS register.
  31. @retval TRUE TPM chip exists.
  32. @retval FALSE TPM chip is not found.
  33. **/
  34. BOOLEAN
  35. Tpm12TisPcPresenceCheck (
  36. IN TIS_PC_REGISTERS_PTR TisReg
  37. )
  38. {
  39. UINT8 RegRead;
  40. RegRead = MmioRead8 ((UINTN)&TisReg->Access);
  41. return (BOOLEAN)(RegRead != (UINT8)-1);
  42. }
  43. /**
  44. Return PTP interface type.
  45. @param[in] Register Pointer to PTP register.
  46. @return PTP interface type.
  47. **/
  48. PTP_INTERFACE_TYPE
  49. Tpm12GetPtpInterface (
  50. IN VOID *Register
  51. )
  52. {
  53. PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;
  54. PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;
  55. if (!Tpm12TisPcPresenceCheck (Register)) {
  56. return PtpInterfaceMax;
  57. }
  58. //
  59. // Check interface id
  60. //
  61. InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
  62. InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
  63. if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&
  64. (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&
  65. (InterfaceId.Bits.CapCRB != 0))
  66. {
  67. return PtpInterfaceCrb;
  68. }
  69. if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO) &&
  70. (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO) &&
  71. (InterfaceId.Bits.CapFIFO != 0) &&
  72. (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP))
  73. {
  74. return PtpInterfaceFifo;
  75. }
  76. return PtpInterfaceTis;
  77. }
  78. /**
  79. Check whether the value of a TPM chip register satisfies the input BIT setting.
  80. @param[in] Register Address port of register to be checked.
  81. @param[in] BitSet Check these data bits are set.
  82. @param[in] BitClear Check these data bits are clear.
  83. @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.
  84. @retval EFI_SUCCESS The register satisfies the check bit.
  85. @retval EFI_TIMEOUT The register can't run into the expected status in time.
  86. **/
  87. EFI_STATUS
  88. Tpm12TisPcWaitRegisterBits (
  89. IN UINT8 *Register,
  90. IN UINT8 BitSet,
  91. IN UINT8 BitClear,
  92. IN UINT32 TimeOut
  93. )
  94. {
  95. UINT8 RegRead;
  96. UINT32 WaitTime;
  97. for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30) {
  98. RegRead = MmioRead8 ((UINTN)Register);
  99. if (((RegRead & BitSet) == BitSet) && ((RegRead & BitClear) == 0)) {
  100. return EFI_SUCCESS;
  101. }
  102. MicroSecondDelay (30);
  103. }
  104. return EFI_TIMEOUT;
  105. }
  106. /**
  107. Get BurstCount by reading the burstCount field of a TIS register
  108. in the time of default TIS_TIMEOUT_D.
  109. @param[in] TisReg Pointer to TIS register.
  110. @param[out] BurstCount Pointer to a buffer to store the got BurstCount.
  111. @retval EFI_SUCCESS Get BurstCount.
  112. @retval EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.
  113. @retval EFI_TIMEOUT BurstCount can't be got in time.
  114. **/
  115. EFI_STATUS
  116. Tpm12TisPcReadBurstCount (
  117. IN TIS_PC_REGISTERS_PTR TisReg,
  118. OUT UINT16 *BurstCount
  119. )
  120. {
  121. UINT32 WaitTime;
  122. UINT8 DataByte0;
  123. UINT8 DataByte1;
  124. if ((BurstCount == NULL) || (TisReg == NULL)) {
  125. return EFI_INVALID_PARAMETER;
  126. }
  127. WaitTime = 0;
  128. do {
  129. //
  130. // TIS_PC_REGISTERS_PTR->burstCount is UINT16, but it is not 2bytes aligned,
  131. // so it needs to use MmioRead8 to read two times
  132. //
  133. DataByte0 = MmioRead8 ((UINTN)&TisReg->BurstCount);
  134. DataByte1 = MmioRead8 ((UINTN)&TisReg->BurstCount + 1);
  135. *BurstCount = (UINT16)((DataByte1 << 8) + DataByte0);
  136. if (*BurstCount != 0) {
  137. return EFI_SUCCESS;
  138. }
  139. MicroSecondDelay (30);
  140. WaitTime += 30;
  141. } while (WaitTime < TIS_TIMEOUT_D);
  142. return EFI_TIMEOUT;
  143. }
  144. /**
  145. Set TPM chip to ready state by sending ready command TIS_PC_STS_READY
  146. to Status Register in time.
  147. @param[in] TisReg Pointer to TIS register.
  148. @retval EFI_SUCCESS TPM chip enters into ready state.
  149. @retval EFI_INVALID_PARAMETER TisReg is NULL.
  150. @retval EFI_TIMEOUT TPM chip can't be set to ready state in time.
  151. **/
  152. EFI_STATUS
  153. Tpm12TisPcPrepareCommand (
  154. IN TIS_PC_REGISTERS_PTR TisReg
  155. )
  156. {
  157. EFI_STATUS Status;
  158. if (TisReg == NULL) {
  159. return EFI_INVALID_PARAMETER;
  160. }
  161. MmioWrite8 ((UINTN)&TisReg->Status, TIS_PC_STS_READY);
  162. Status = Tpm12TisPcWaitRegisterBits (
  163. &TisReg->Status,
  164. TIS_PC_STS_READY,
  165. 0,
  166. TIS_TIMEOUT_B
  167. );
  168. return Status;
  169. }
  170. /**
  171. Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE
  172. to ACCESS Register in the time of default TIS_TIMEOUT_A.
  173. @param[in] TisReg Pointer to TIS register.
  174. @retval EFI_SUCCESS Get the control of TPM chip.
  175. @retval EFI_INVALID_PARAMETER TisReg is NULL.
  176. @retval EFI_NOT_FOUND TPM chip doesn't exit.
  177. @retval EFI_TIMEOUT Can't get the TPM control in time.
  178. **/
  179. EFI_STATUS
  180. Tpm12TisPcRequestUseTpm (
  181. IN TIS_PC_REGISTERS_PTR TisReg
  182. )
  183. {
  184. EFI_STATUS Status;
  185. if (TisReg == NULL) {
  186. return EFI_INVALID_PARAMETER;
  187. }
  188. if (!Tpm12TisPcPresenceCheck (TisReg)) {
  189. return EFI_NOT_FOUND;
  190. }
  191. MmioWrite8 ((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);
  192. Status = Tpm12TisPcWaitRegisterBits (
  193. &TisReg->Access,
  194. (UINT8)(TIS_PC_ACC_ACTIVE |TIS_PC_VALID),
  195. 0,
  196. TIS_TIMEOUT_A
  197. );
  198. return Status;
  199. }
  200. /**
  201. Send a command to TPM for execution and return response data.
  202. @param[in] TisReg TPM register space base address.
  203. @param[in] BufferIn Buffer for command data.
  204. @param[in] SizeIn Size of command data.
  205. @param[in, out] BufferOut Buffer for response data.
  206. @param[in, out] SizeOut Size of response data.
  207. @retval EFI_SUCCESS Operation completed successfully.
  208. @retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.
  209. @retval EFI_DEVICE_ERROR Unexpected device behavior.
  210. @retval EFI_UNSUPPORTED Unsupported TPM version
  211. **/
  212. EFI_STATUS
  213. Tpm12TisTpmCommand (
  214. IN TIS_PC_REGISTERS_PTR TisReg,
  215. IN UINT8 *BufferIn,
  216. IN UINT32 SizeIn,
  217. IN OUT UINT8 *BufferOut,
  218. IN OUT UINT32 *SizeOut
  219. )
  220. {
  221. EFI_STATUS Status;
  222. UINT16 BurstCount;
  223. UINT32 Index;
  224. UINT32 TpmOutSize;
  225. UINT16 Data16;
  226. UINT32 Data32;
  227. UINT16 RspTag;
  228. DEBUG_CODE_BEGIN ();
  229. UINTN DebugSize;
  230. DEBUG ((DEBUG_VERBOSE, "Tpm12TisTpmCommand Send - "));
  231. if (SizeIn > 0x100) {
  232. DebugSize = 0x40;
  233. } else {
  234. DebugSize = SizeIn;
  235. }
  236. for (Index = 0; Index < DebugSize; Index++) {
  237. DEBUG ((DEBUG_VERBOSE, "%02x ", BufferIn[Index]));
  238. }
  239. if (DebugSize != SizeIn) {
  240. DEBUG ((DEBUG_VERBOSE, "...... "));
  241. for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {
  242. DEBUG ((DEBUG_VERBOSE, "%02x ", BufferIn[Index]));
  243. }
  244. }
  245. DEBUG ((DEBUG_VERBOSE, "\n"));
  246. DEBUG_CODE_END ();
  247. TpmOutSize = 0;
  248. Status = Tpm12TisPcPrepareCommand (TisReg);
  249. if (EFI_ERROR (Status)) {
  250. DEBUG ((DEBUG_ERROR, "Tpm12 is not ready for command!\n"));
  251. return EFI_DEVICE_ERROR;
  252. }
  253. //
  254. // Send the command data to Tpm
  255. //
  256. Index = 0;
  257. while (Index < SizeIn) {
  258. Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);
  259. if (EFI_ERROR (Status)) {
  260. Status = EFI_DEVICE_ERROR;
  261. goto Exit;
  262. }
  263. for ( ; BurstCount > 0 && Index < SizeIn; BurstCount--) {
  264. MmioWrite8 ((UINTN)&TisReg->DataFifo, *(BufferIn + Index));
  265. Index++;
  266. }
  267. }
  268. //
  269. // Check the Tpm status STS_EXPECT change from 1 to 0
  270. //
  271. Status = Tpm12TisPcWaitRegisterBits (
  272. &TisReg->Status,
  273. (UINT8)TIS_PC_VALID,
  274. TIS_PC_STS_EXPECT,
  275. TIS_TIMEOUT_C
  276. );
  277. if (EFI_ERROR (Status)) {
  278. DEBUG ((DEBUG_ERROR, "Tpm12 The send buffer too small!\n"));
  279. Status = EFI_BUFFER_TOO_SMALL;
  280. goto Exit;
  281. }
  282. //
  283. // Executed the TPM command and waiting for the response data ready
  284. //
  285. MmioWrite8 ((UINTN)&TisReg->Status, TIS_PC_STS_GO);
  286. Status = Tpm12TisPcWaitRegisterBits (
  287. &TisReg->Status,
  288. (UINT8)(TIS_PC_VALID | TIS_PC_STS_DATA),
  289. 0,
  290. TIS_TIMEOUT_B
  291. );
  292. if (EFI_ERROR (Status)) {
  293. DEBUG ((DEBUG_ERROR, "Wait for Tpm12 response data time out!!\n"));
  294. Status = EFI_DEVICE_ERROR;
  295. goto Exit;
  296. }
  297. //
  298. // Get response data header
  299. //
  300. Index = 0;
  301. BurstCount = 0;
  302. while (Index < sizeof (TPM_RSP_COMMAND_HDR)) {
  303. Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);
  304. if (EFI_ERROR (Status)) {
  305. Status = EFI_DEVICE_ERROR;
  306. goto Exit;
  307. }
  308. for ( ; BurstCount > 0; BurstCount--) {
  309. *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
  310. Index++;
  311. if (Index == sizeof (TPM_RSP_COMMAND_HDR)) {
  312. break;
  313. }
  314. }
  315. }
  316. DEBUG_CODE_BEGIN ();
  317. DEBUG ((DEBUG_VERBOSE, "Tpm12TisTpmCommand ReceiveHeader - "));
  318. for (Index = 0; Index < sizeof (TPM_RSP_COMMAND_HDR); Index++) {
  319. DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));
  320. }
  321. DEBUG ((DEBUG_VERBOSE, "\n"));
  322. DEBUG_CODE_END ();
  323. //
  324. // Check the response data header (tag, parasize and returncode)
  325. //
  326. CopyMem (&Data16, BufferOut, sizeof (UINT16));
  327. RspTag = SwapBytes16 (Data16);
  328. if ((RspTag != TPM_TAG_RSP_COMMAND) && (RspTag != TPM_TAG_RSP_AUTH1_COMMAND) && (RspTag != TPM_TAG_RSP_AUTH2_COMMAND)) {
  329. DEBUG ((DEBUG_ERROR, "TPM12: Response tag error - current tag value is %x\n", RspTag));
  330. Status = EFI_UNSUPPORTED;
  331. goto Exit;
  332. }
  333. CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));
  334. TpmOutSize = SwapBytes32 (Data32);
  335. if (*SizeOut < TpmOutSize) {
  336. Status = EFI_BUFFER_TOO_SMALL;
  337. goto Exit;
  338. }
  339. *SizeOut = TpmOutSize;
  340. //
  341. // Continue reading the remaining data
  342. //
  343. while ( Index < TpmOutSize ) {
  344. for ( ; BurstCount > 0; BurstCount--) {
  345. *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);
  346. Index++;
  347. if (Index == TpmOutSize) {
  348. Status = EFI_SUCCESS;
  349. goto Exit;
  350. }
  351. }
  352. Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);
  353. if (EFI_ERROR (Status)) {
  354. Status = EFI_DEVICE_ERROR;
  355. goto Exit;
  356. }
  357. }
  358. Exit:
  359. DEBUG_CODE_BEGIN ();
  360. DEBUG ((DEBUG_VERBOSE, "Tpm12TisTpmCommand Receive - "));
  361. for (Index = 0; Index < TpmOutSize; Index++) {
  362. DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));
  363. }
  364. DEBUG ((DEBUG_VERBOSE, "\n"));
  365. DEBUG_CODE_END ();
  366. MmioWrite8 ((UINTN)&TisReg->Status, TIS_PC_STS_READY);
  367. return Status;
  368. }
  369. /**
  370. This service enables the sending of commands to the TPM12.
  371. @param[in] InputParameterBlockSize Size of the TPM12 input parameter block.
  372. @param[in] InputParameterBlock Pointer to the TPM12 input parameter block.
  373. @param[in,out] OutputParameterBlockSize Size of the TPM12 output parameter block.
  374. @param[in] OutputParameterBlock Pointer to the TPM12 output parameter block.
  375. @retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.
  376. @retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.
  377. @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small.
  378. **/
  379. EFI_STATUS
  380. EFIAPI
  381. Tpm12SubmitCommand (
  382. IN UINT32 InputParameterBlockSize,
  383. IN UINT8 *InputParameterBlock,
  384. IN OUT UINT32 *OutputParameterBlockSize,
  385. IN UINT8 *OutputParameterBlock
  386. )
  387. {
  388. PTP_INTERFACE_TYPE PtpInterface;
  389. //
  390. // Special handle for TPM1.2 to check PTP too, because PTP/TIS share same register address.
  391. //
  392. PtpInterface = Tpm12GetPtpInterface ((VOID *)(UINTN)PcdGet64 (PcdTpmBaseAddress));
  393. switch (PtpInterface) {
  394. case PtpInterfaceFifo:
  395. case PtpInterfaceTis:
  396. return Tpm12TisTpmCommand (
  397. (TIS_PC_REGISTERS_PTR)(UINTN)PcdGet64 (PcdTpmBaseAddress),
  398. InputParameterBlock,
  399. InputParameterBlockSize,
  400. OutputParameterBlock,
  401. OutputParameterBlockSize
  402. );
  403. case PtpInterfaceCrb:
  404. //
  405. // No need to support CRB because it is only accept TPM2 command.
  406. //
  407. default:
  408. return EFI_DEVICE_ERROR;
  409. }
  410. }
  411. /**
  412. Check whether the value of a TPM chip register satisfies the input BIT setting.
  413. @param[in] Register Address port of register to be checked.
  414. @param[in] BitSet Check these data bits are set.
  415. @param[in] BitClear Check these data bits are clear.
  416. @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.
  417. @retval EFI_SUCCESS The register satisfies the check bit.
  418. @retval EFI_TIMEOUT The register can't run into the expected status in time.
  419. **/
  420. EFI_STATUS
  421. Tpm12PtpCrbWaitRegisterBits (
  422. IN UINT32 *Register,
  423. IN UINT32 BitSet,
  424. IN UINT32 BitClear,
  425. IN UINT32 TimeOut
  426. )
  427. {
  428. UINT32 RegRead;
  429. UINT32 WaitTime;
  430. for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30) {
  431. RegRead = MmioRead32 ((UINTN)Register);
  432. if (((RegRead & BitSet) == BitSet) && ((RegRead & BitClear) == 0)) {
  433. return EFI_SUCCESS;
  434. }
  435. MicroSecondDelay (30);
  436. }
  437. return EFI_TIMEOUT;
  438. }
  439. /**
  440. Get the control of TPM chip.
  441. @param[in] CrbReg Pointer to CRB register.
  442. @retval EFI_SUCCESS Get the control of TPM chip.
  443. @retval EFI_INVALID_PARAMETER CrbReg is NULL.
  444. @retval EFI_NOT_FOUND TPM chip doesn't exit.
  445. @retval EFI_TIMEOUT Can't get the TPM control in time.
  446. **/
  447. EFI_STATUS
  448. Tpm12PtpCrbRequestUseTpm (
  449. IN PTP_CRB_REGISTERS_PTR CrbReg
  450. )
  451. {
  452. EFI_STATUS Status;
  453. MmioWrite32 ((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);
  454. Status = Tpm12PtpCrbWaitRegisterBits (
  455. &CrbReg->LocalityStatus,
  456. PTP_CRB_LOCALITY_STATUS_GRANTED,
  457. 0,
  458. PTP_TIMEOUT_A
  459. );
  460. return Status;
  461. }
  462. /**
  463. This service requests use TPM12.
  464. @retval EFI_SUCCESS Get the control of TPM12 chip.
  465. @retval EFI_NOT_FOUND TPM12 not found.
  466. @retval EFI_DEVICE_ERROR Unexpected device behavior.
  467. **/
  468. EFI_STATUS
  469. EFIAPI
  470. Tpm12RequestUseTpm (
  471. VOID
  472. )
  473. {
  474. PTP_INTERFACE_TYPE PtpInterface;
  475. //
  476. // Special handle for TPM1.2 to check PTP too, because PTP/TIS share same register address.
  477. // Some other program might leverage this function to check the existence of TPM chip.
  478. //
  479. PtpInterface = Tpm12GetPtpInterface ((VOID *)(UINTN)PcdGet64 (PcdTpmBaseAddress));
  480. switch (PtpInterface) {
  481. case PtpInterfaceCrb:
  482. return Tpm12PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR)(UINTN)PcdGet64 (PcdTpmBaseAddress));
  483. case PtpInterfaceFifo:
  484. case PtpInterfaceTis:
  485. return Tpm12TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR)(UINTN)PcdGet64 (PcdTpmBaseAddress));
  486. default:
  487. return EFI_NOT_FOUND;
  488. }
  489. }