CpuDxe.c 11 KB

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  1. /** @file
  2. RISC-V CPU DXE driver.
  3. Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
  4. Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #include "CpuDxe.h"
  8. //
  9. // Global Variables
  10. //
  11. STATIC BOOLEAN mInterruptState = FALSE;
  12. STATIC EFI_HANDLE mCpuHandle = NULL;
  13. STATIC UINTN mBootHartId;
  14. RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol;
  15. /**
  16. Get the boot hartid
  17. @param This Protocol instance structure
  18. @param BootHartId Pointer to the Boot Hart ID variable
  19. @retval EFI_SUCCESS If BootHartId is returned
  20. @retval EFI_INVALID_PARAMETER Either "BootHartId" is NULL or "This" is not
  21. a valid RISCV_EFI_BOOT_PROTOCOL instance.
  22. **/
  23. EFI_STATUS
  24. EFIAPI
  25. RiscvGetBootHartId (
  26. IN RISCV_EFI_BOOT_PROTOCOL *This,
  27. OUT UINTN *BootHartId
  28. )
  29. {
  30. if ((This != &gRiscvBootProtocol) || (BootHartId == NULL)) {
  31. return EFI_INVALID_PARAMETER;
  32. }
  33. *BootHartId = mBootHartId;
  34. return EFI_SUCCESS;
  35. }
  36. RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol = {
  37. RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION,
  38. RiscvGetBootHartId
  39. };
  40. EFI_CPU_ARCH_PROTOCOL gCpu = {
  41. CpuFlushCpuDataCache,
  42. CpuEnableInterrupt,
  43. CpuDisableInterrupt,
  44. CpuGetInterruptState,
  45. CpuInit,
  46. CpuRegisterInterruptHandler,
  47. CpuGetTimerValue,
  48. CpuSetMemoryAttributes,
  49. 1, // NumberOfTimers
  50. 4 // DmaBufferAlignment
  51. };
  52. //
  53. // CPU Arch Protocol Functions
  54. //
  55. /**
  56. Flush CPU data cache. If the instruction cache is fully coherent
  57. with all DMA operations then function can just return EFI_SUCCESS.
  58. @param This Protocol instance structure
  59. @param Start Physical address to start flushing from.
  60. @param Length Number of bytes to flush. Round up to chipset
  61. granularity.
  62. @param FlushType Specifies the type of flush operation to perform.
  63. @retval EFI_SUCCESS If cache was flushed
  64. @retval EFI_UNSUPPORTED If flush type is not supported.
  65. @retval EFI_DEVICE_ERROR If requested range could not be flushed.
  66. **/
  67. EFI_STATUS
  68. EFIAPI
  69. CpuFlushCpuDataCache (
  70. IN EFI_CPU_ARCH_PROTOCOL *This,
  71. IN EFI_PHYSICAL_ADDRESS Start,
  72. IN UINT64 Length,
  73. IN EFI_CPU_FLUSH_TYPE FlushType
  74. )
  75. {
  76. return EFI_SUCCESS;
  77. }
  78. /**
  79. Enables CPU interrupts.
  80. @param This Protocol instance structure
  81. @retval EFI_SUCCESS If interrupts were enabled in the CPU
  82. @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
  83. **/
  84. EFI_STATUS
  85. EFIAPI
  86. CpuEnableInterrupt (
  87. IN EFI_CPU_ARCH_PROTOCOL *This
  88. )
  89. {
  90. EnableInterrupts ();
  91. mInterruptState = TRUE;
  92. return EFI_SUCCESS;
  93. }
  94. /**
  95. Disables CPU interrupts.
  96. @param This Protocol instance structure
  97. @retval EFI_SUCCESS If interrupts were disabled in the CPU.
  98. @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
  99. **/
  100. EFI_STATUS
  101. EFIAPI
  102. CpuDisableInterrupt (
  103. IN EFI_CPU_ARCH_PROTOCOL *This
  104. )
  105. {
  106. DisableInterrupts ();
  107. mInterruptState = FALSE;
  108. return EFI_SUCCESS;
  109. }
  110. /**
  111. Return the state of interrupts.
  112. @param This Protocol instance structure
  113. @param State Pointer to the CPU's current interrupt state
  114. @retval EFI_SUCCESS If interrupts were disabled in the CPU.
  115. @retval EFI_INVALID_PARAMETER State is NULL.
  116. **/
  117. EFI_STATUS
  118. EFIAPI
  119. CpuGetInterruptState (
  120. IN EFI_CPU_ARCH_PROTOCOL *This,
  121. OUT BOOLEAN *State
  122. )
  123. {
  124. if (State == NULL) {
  125. return EFI_INVALID_PARAMETER;
  126. }
  127. *State = mInterruptState;
  128. return EFI_SUCCESS;
  129. }
  130. /**
  131. Generates an INIT to the CPU.
  132. @param This Protocol instance structure
  133. @param InitType Type of CPU INIT to perform
  134. @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
  135. seen.
  136. @retval EFI_DEVICE_ERROR If CPU INIT failed.
  137. @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
  138. **/
  139. EFI_STATUS
  140. EFIAPI
  141. CpuInit (
  142. IN EFI_CPU_ARCH_PROTOCOL *This,
  143. IN EFI_CPU_INIT_TYPE InitType
  144. )
  145. {
  146. return EFI_UNSUPPORTED;
  147. }
  148. /**
  149. Registers a function to be called from the CPU interrupt handler.
  150. @param This Protocol instance structure
  151. @param InterruptType Defines which interrupt to hook. IA-32
  152. valid range is 0x00 through 0xFF
  153. @param InterruptHandler A pointer to a function of type
  154. EFI_CPU_INTERRUPT_HANDLER that is called
  155. when a processor interrupt occurs. A null
  156. pointer is an error condition.
  157. @retval EFI_SUCCESS If handler installed or uninstalled.
  158. @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
  159. for InterruptType was previously installed.
  160. @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
  161. InterruptType was not previously installed.
  162. @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
  163. is not supported.
  164. **/
  165. EFI_STATUS
  166. EFIAPI
  167. CpuRegisterInterruptHandler (
  168. IN EFI_CPU_ARCH_PROTOCOL *This,
  169. IN EFI_EXCEPTION_TYPE InterruptType,
  170. IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
  171. )
  172. {
  173. return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
  174. }
  175. /**
  176. Returns a timer value from one of the CPU's internal timers. There is no
  177. inherent time interval between ticks but is a function of the CPU frequency.
  178. @param This - Protocol instance structure.
  179. @param TimerIndex - Specifies which CPU timer is requested.
  180. @param TimerValue - Pointer to the returned timer value.
  181. @param TimerPeriod - A pointer to the amount of time that passes
  182. in femtoseconds (10-15) for each increment
  183. of TimerValue. If TimerValue does not
  184. increment at a predictable rate, then 0 is
  185. returned. The amount of time that has
  186. passed between two calls to GetTimerValue()
  187. can be calculated with the formula
  188. (TimerValue2 - TimerValue1) * TimerPeriod.
  189. This parameter is optional and may be NULL.
  190. @retval EFI_SUCCESS - If the CPU timer count was returned.
  191. @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
  192. @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
  193. @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
  194. **/
  195. EFI_STATUS
  196. EFIAPI
  197. CpuGetTimerValue (
  198. IN EFI_CPU_ARCH_PROTOCOL *This,
  199. IN UINT32 TimerIndex,
  200. OUT UINT64 *TimerValue,
  201. OUT UINT64 *TimerPeriod OPTIONAL
  202. )
  203. {
  204. if (TimerValue == NULL) {
  205. return EFI_INVALID_PARAMETER;
  206. }
  207. if (TimerIndex != 0) {
  208. return EFI_INVALID_PARAMETER;
  209. }
  210. *TimerValue = (UINT64)RiscVReadTimer ();
  211. if (TimerPeriod != NULL) {
  212. *TimerPeriod = DivU64x32 (
  213. 1000000000000000u,
  214. PcdGet64 (PcdCpuCoreCrystalClockFrequency)
  215. );
  216. }
  217. return EFI_SUCCESS;
  218. }
  219. /**
  220. Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.
  221. This function modifies the attributes for the memory region specified by BaseAddress and
  222. Length from their current attributes to the attributes specified by Attributes.
  223. @param This The EFI_CPU_ARCH_PROTOCOL instance.
  224. @param BaseAddress The physical address that is the start address of a memory region.
  225. @param Length The size in bytes of the memory region.
  226. @param Attributes The bit mask of attributes to set for the memory region.
  227. @retval EFI_SUCCESS The attributes were set for the memory region.
  228. @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
  229. BaseAddress and Length cannot be modified.
  230. @retval EFI_INVALID_PARAMETER Length is zero.
  231. Attributes specified an illegal combination of attributes that
  232. cannot be set together.
  233. @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
  234. the memory resource range.
  235. @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
  236. resource range specified by BaseAddress and Length.
  237. The bit mask of attributes is not support for the memory resource
  238. range specified by BaseAddress and Length.
  239. **/
  240. EFI_STATUS
  241. EFIAPI
  242. CpuSetMemoryAttributes (
  243. IN EFI_CPU_ARCH_PROTOCOL *This,
  244. IN EFI_PHYSICAL_ADDRESS BaseAddress,
  245. IN UINT64 Length,
  246. IN UINT64 Attributes
  247. )
  248. {
  249. DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __FUNCTION__));
  250. return EFI_SUCCESS;
  251. }
  252. /**
  253. Initialize the state information for the CPU Architectural Protocol.
  254. @param ImageHandle Image handle this driver.
  255. @param SystemTable Pointer to the System Table.
  256. @retval EFI_SUCCESS Thread can be successfully created
  257. @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
  258. @retval EFI_DEVICE_ERROR Cannot create the thread
  259. **/
  260. EFI_STATUS
  261. EFIAPI
  262. InitializeCpu (
  263. IN EFI_HANDLE ImageHandle,
  264. IN EFI_SYSTEM_TABLE *SystemTable
  265. )
  266. {
  267. EFI_STATUS Status;
  268. EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext;
  269. GetFirmwareContextPointer (&FirmwareContext);
  270. ASSERT (FirmwareContext != NULL);
  271. if (FirmwareContext == NULL) {
  272. DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_FIRMWARE_CONTEXT\n"));
  273. return EFI_NOT_FOUND;
  274. }
  275. DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n", __FUNCTION__, FirmwareContext));
  276. mBootHartId = FirmwareContext->BootHartId;
  277. DEBUG ((DEBUG_INFO, " %a: mBootHartId = 0x%x.\n", __FUNCTION__, mBootHartId));
  278. InitializeCpuExceptionHandlers (NULL);
  279. //
  280. // Make sure interrupts are disabled
  281. //
  282. DisableInterrupts ();
  283. //
  284. // Install Boot protocol
  285. //
  286. Status = gBS->InstallProtocolInterface (
  287. &ImageHandle,
  288. &gRiscVEfiBootProtocolGuid,
  289. EFI_NATIVE_INTERFACE,
  290. &gRiscvBootProtocol
  291. );
  292. ASSERT_EFI_ERROR (Status);
  293. //
  294. // Install CPU Architectural Protocol
  295. //
  296. Status = gBS->InstallMultipleProtocolInterfaces (
  297. &mCpuHandle,
  298. &gEfiCpuArchProtocolGuid,
  299. &gCpu,
  300. NULL
  301. );
  302. ASSERT_EFI_ERROR (Status);
  303. return Status;
  304. }