FdtPciHostBridgeLib.c 14 KB

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  1. /** @file
  2. PCI Host Bridge Library instance for pci-ecam-generic DT nodes
  3. Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <PiDxe.h>
  7. #include <Library/BaseMemoryLib.h>
  8. #include <Library/DebugLib.h>
  9. #include <Library/DevicePathLib.h>
  10. #include <Library/DxeServicesTableLib.h>
  11. #include <Library/MemoryAllocationLib.h>
  12. #include <Library/PcdLib.h>
  13. #include <Library/PciHostBridgeLib.h>
  14. #include <Library/PciHostBridgeUtilityLib.h>
  15. #include <Library/UefiBootServicesTableLib.h>
  16. #include <Protocol/FdtClient.h>
  17. #include <Protocol/PciRootBridgeIo.h>
  18. #include <Protocol/PciHostBridgeResourceAllocation.h>
  19. //
  20. // We expect the "ranges" property of "pci-host-ecam-generic" to consist of
  21. // records like this.
  22. //
  23. #pragma pack (1)
  24. typedef struct {
  25. UINT32 Type;
  26. UINT64 ChildBase;
  27. UINT64 CpuBase;
  28. UINT64 Size;
  29. } DTB_PCI_HOST_RANGE_RECORD;
  30. #pragma pack ()
  31. #define DTB_PCI_HOST_RANGE_RELOCATABLE BIT31
  32. #define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
  33. #define DTB_PCI_HOST_RANGE_ALIASED BIT29
  34. #define DTB_PCI_HOST_RANGE_MMIO32 BIT25
  35. #define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24)
  36. #define DTB_PCI_HOST_RANGE_IO BIT24
  37. #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
  38. STATIC
  39. EFI_STATUS
  40. MapGcdMmioSpace (
  41. IN UINT64 Base,
  42. IN UINT64 Size
  43. )
  44. {
  45. EFI_STATUS Status;
  46. Status = gDS->AddMemorySpace (
  47. EfiGcdMemoryTypeMemoryMappedIo,
  48. Base,
  49. Size,
  50. EFI_MEMORY_UC
  51. );
  52. if (EFI_ERROR (Status)) {
  53. DEBUG ((
  54. DEBUG_ERROR,
  55. "%a: failed to add GCD memory space for region [0x%Lx+0x%Lx)\n",
  56. __FUNCTION__,
  57. Base,
  58. Size
  59. ));
  60. return Status;
  61. }
  62. Status = gDS->SetMemorySpaceAttributes (Base, Size, EFI_MEMORY_UC);
  63. if (EFI_ERROR (Status)) {
  64. DEBUG ((
  65. DEBUG_ERROR,
  66. "%a: failed to set memory space attributes for region [0x%Lx+0x%Lx)\n",
  67. __FUNCTION__,
  68. Base,
  69. Size
  70. ));
  71. }
  72. return Status;
  73. }
  74. STATIC
  75. EFI_STATUS
  76. ProcessPciHost (
  77. OUT UINT64 *IoBase,
  78. OUT UINT64 *IoSize,
  79. OUT UINT64 *Mmio32Base,
  80. OUT UINT64 *Mmio32Size,
  81. OUT UINT64 *Mmio64Base,
  82. OUT UINT64 *Mmio64Size,
  83. OUT UINT32 *BusMin,
  84. OUT UINT32 *BusMax
  85. )
  86. {
  87. FDT_CLIENT_PROTOCOL *FdtClient;
  88. INT32 Node;
  89. UINT64 ConfigBase, ConfigSize;
  90. CONST VOID *Prop;
  91. UINT32 Len;
  92. UINT32 RecordIdx;
  93. EFI_STATUS Status;
  94. UINT64 IoTranslation;
  95. UINT64 Mmio32Translation;
  96. UINT64 Mmio64Translation;
  97. //
  98. // The following output arguments are initialized only in
  99. // order to suppress '-Werror=maybe-uninitialized' warnings
  100. // *incorrectly* emitted by some gcc versions.
  101. //
  102. *IoBase = 0;
  103. *Mmio32Base = 0;
  104. *Mmio64Base = MAX_UINT64;
  105. *BusMin = 0;
  106. *BusMax = 0;
  107. //
  108. // *IoSize, *Mmio##Size and IoTranslation are initialized to zero because the
  109. // logic below requires it. However, since they are also affected by the issue
  110. // reported above, they are initialized early.
  111. //
  112. *IoSize = 0;
  113. *Mmio32Size = 0;
  114. *Mmio64Size = 0;
  115. IoTranslation = 0;
  116. Status = gBS->LocateProtocol (
  117. &gFdtClientProtocolGuid,
  118. NULL,
  119. (VOID **)&FdtClient
  120. );
  121. ASSERT_EFI_ERROR (Status);
  122. Status = FdtClient->FindCompatibleNode (
  123. FdtClient,
  124. "pci-host-ecam-generic",
  125. &Node
  126. );
  127. if (EFI_ERROR (Status)) {
  128. DEBUG ((
  129. DEBUG_INFO,
  130. "%a: No 'pci-host-ecam-generic' compatible DT node found\n",
  131. __FUNCTION__
  132. ));
  133. return EFI_NOT_FOUND;
  134. }
  135. DEBUG_CODE (
  136. INT32 Tmp;
  137. //
  138. // A DT can legally describe multiple PCI host bridges, but we are not
  139. // equipped to deal with that. So assert that there is only one.
  140. //
  141. Status = FdtClient->FindNextCompatibleNode (
  142. FdtClient,
  143. "pci-host-ecam-generic",
  144. Node,
  145. &Tmp
  146. );
  147. ASSERT (Status == EFI_NOT_FOUND);
  148. );
  149. Status = FdtClient->GetNodeProperty (FdtClient, Node, "reg", &Prop, &Len);
  150. if (EFI_ERROR (Status) || (Len != 2 * sizeof (UINT64))) {
  151. DEBUG ((
  152. DEBUG_ERROR,
  153. "%a: 'reg' property not found or invalid\n",
  154. __FUNCTION__
  155. ));
  156. return EFI_PROTOCOL_ERROR;
  157. }
  158. //
  159. // Fetch the ECAM window.
  160. //
  161. ConfigBase = SwapBytes64 (((CONST UINT64 *)Prop)[0]);
  162. ConfigSize = SwapBytes64 (((CONST UINT64 *)Prop)[1]);
  163. //
  164. // Fetch the bus range (note: inclusive).
  165. //
  166. Status = FdtClient->GetNodeProperty (
  167. FdtClient,
  168. Node,
  169. "bus-range",
  170. &Prop,
  171. &Len
  172. );
  173. if (EFI_ERROR (Status) || (Len != 2 * sizeof (UINT32))) {
  174. DEBUG ((
  175. DEBUG_ERROR,
  176. "%a: 'bus-range' not found or invalid\n",
  177. __FUNCTION__
  178. ));
  179. return EFI_PROTOCOL_ERROR;
  180. }
  181. *BusMin = SwapBytes32 (((CONST UINT32 *)Prop)[0]);
  182. *BusMax = SwapBytes32 (((CONST UINT32 *)Prop)[1]);
  183. //
  184. // Sanity check: the config space must accommodate all 4K register bytes of
  185. // all 8 functions of all 32 devices of all buses.
  186. //
  187. if ((*BusMax < *BusMin) || (*BusMax - *BusMin == MAX_UINT32) ||
  188. (DivU64x32 (ConfigSize, SIZE_4KB * 8 * 32) < *BusMax - *BusMin + 1))
  189. {
  190. DEBUG ((
  191. DEBUG_ERROR,
  192. "%a: invalid 'bus-range' and/or 'reg'\n",
  193. __FUNCTION__
  194. ));
  195. return EFI_PROTOCOL_ERROR;
  196. }
  197. //
  198. // Iterate over "ranges".
  199. //
  200. Status = FdtClient->GetNodeProperty (FdtClient, Node, "ranges", &Prop, &Len);
  201. if (EFI_ERROR (Status) || (Len == 0) ||
  202. (Len % sizeof (DTB_PCI_HOST_RANGE_RECORD) != 0))
  203. {
  204. DEBUG ((DEBUG_ERROR, "%a: 'ranges' not found or invalid\n", __FUNCTION__));
  205. return EFI_PROTOCOL_ERROR;
  206. }
  207. for (RecordIdx = 0; RecordIdx < Len / sizeof (DTB_PCI_HOST_RANGE_RECORD);
  208. ++RecordIdx)
  209. {
  210. CONST DTB_PCI_HOST_RANGE_RECORD *Record;
  211. Record = (CONST DTB_PCI_HOST_RANGE_RECORD *)Prop + RecordIdx;
  212. switch (SwapBytes32 (Record->Type) & DTB_PCI_HOST_RANGE_TYPEMASK) {
  213. case DTB_PCI_HOST_RANGE_IO:
  214. *IoBase = SwapBytes64 (Record->ChildBase);
  215. *IoSize = SwapBytes64 (Record->Size);
  216. IoTranslation = SwapBytes64 (Record->CpuBase) - *IoBase;
  217. ASSERT (PcdGet64 (PcdPciIoTranslation) == IoTranslation);
  218. break;
  219. case DTB_PCI_HOST_RANGE_MMIO32:
  220. *Mmio32Base = SwapBytes64 (Record->ChildBase);
  221. *Mmio32Size = SwapBytes64 (Record->Size);
  222. Mmio32Translation = SwapBytes64 (Record->CpuBase) - *Mmio32Base;
  223. if ((*Mmio32Base > MAX_UINT32) || (*Mmio32Size > MAX_UINT32) ||
  224. (*Mmio32Base + *Mmio32Size > SIZE_4GB))
  225. {
  226. DEBUG ((DEBUG_ERROR, "%a: MMIO32 space invalid\n", __FUNCTION__));
  227. return EFI_PROTOCOL_ERROR;
  228. }
  229. ASSERT (PcdGet64 (PcdPciMmio32Translation) == Mmio32Translation);
  230. if (Mmio32Translation != 0) {
  231. DEBUG ((
  232. DEBUG_ERROR,
  233. "%a: unsupported nonzero MMIO32 translation "
  234. "0x%Lx\n",
  235. __FUNCTION__,
  236. Mmio32Translation
  237. ));
  238. return EFI_UNSUPPORTED;
  239. }
  240. break;
  241. case DTB_PCI_HOST_RANGE_MMIO64:
  242. *Mmio64Base = SwapBytes64 (Record->ChildBase);
  243. *Mmio64Size = SwapBytes64 (Record->Size);
  244. Mmio64Translation = SwapBytes64 (Record->CpuBase) - *Mmio64Base;
  245. ASSERT (PcdGet64 (PcdPciMmio64Translation) == Mmio64Translation);
  246. if (Mmio64Translation != 0) {
  247. DEBUG ((
  248. DEBUG_ERROR,
  249. "%a: unsupported nonzero MMIO64 translation "
  250. "0x%Lx\n",
  251. __FUNCTION__,
  252. Mmio64Translation
  253. ));
  254. return EFI_UNSUPPORTED;
  255. }
  256. break;
  257. }
  258. }
  259. if (*Mmio32Size == 0) {
  260. DEBUG ((DEBUG_ERROR, "%a: MMIO32 space empty\n", __FUNCTION__));
  261. return EFI_PROTOCOL_ERROR;
  262. }
  263. //
  264. // The dynamic PCD PcdPciExpressBaseAddress should have already been set,
  265. // and should match the value we found in the DT node.
  266. //
  267. ASSERT (PcdGet64 (PcdPciExpressBaseAddress) == ConfigBase);
  268. DEBUG ((
  269. DEBUG_INFO,
  270. "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] "
  271. "Io[0x%Lx+0x%Lx)@0x%Lx Mem32[0x%Lx+0x%Lx)@0x0 Mem64[0x%Lx+0x%Lx)@0x0\n",
  272. __FUNCTION__,
  273. ConfigBase,
  274. ConfigSize,
  275. *BusMin,
  276. *BusMax,
  277. *IoBase,
  278. *IoSize,
  279. IoTranslation,
  280. *Mmio32Base,
  281. *Mmio32Size,
  282. *Mmio64Base,
  283. *Mmio64Size
  284. ));
  285. // Map the ECAM space in the GCD memory map
  286. Status = MapGcdMmioSpace (ConfigBase, ConfigSize);
  287. ASSERT_EFI_ERROR (Status);
  288. if (EFI_ERROR (Status)) {
  289. return Status;
  290. }
  291. if (*IoSize != 0) {
  292. //
  293. // Map the MMIO window that provides I/O access - the PCI host bridge code
  294. // is not aware of this translation and so it will only map the I/O view
  295. // in the GCD I/O map.
  296. //
  297. Status = MapGcdMmioSpace (*IoBase + IoTranslation, *IoSize);
  298. ASSERT_EFI_ERROR (Status);
  299. }
  300. return Status;
  301. }
  302. /**
  303. Return all the root bridge instances in an array.
  304. @param Count Return the count of root bridge instances.
  305. @return All the root bridge instances in an array.
  306. The array should be passed into PciHostBridgeFreeRootBridges()
  307. when it's not used.
  308. **/
  309. PCI_ROOT_BRIDGE *
  310. EFIAPI
  311. PciHostBridgeGetRootBridges (
  312. UINTN *Count
  313. )
  314. {
  315. UINT64 IoBase, IoSize;
  316. UINT64 Mmio32Base, Mmio32Size;
  317. UINT64 Mmio64Base, Mmio64Size;
  318. UINT32 BusMin, BusMax;
  319. EFI_STATUS Status;
  320. UINT64 Attributes;
  321. UINT64 AllocationAttributes;
  322. PCI_ROOT_BRIDGE_APERTURE Io;
  323. PCI_ROOT_BRIDGE_APERTURE Mem;
  324. PCI_ROOT_BRIDGE_APERTURE MemAbove4G;
  325. PCI_ROOT_BRIDGE_APERTURE PMem;
  326. PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;
  327. if (PcdGet64 (PcdPciExpressBaseAddress) == 0) {
  328. DEBUG ((DEBUG_INFO, "%a: PCI host bridge not present\n", __FUNCTION__));
  329. *Count = 0;
  330. return NULL;
  331. }
  332. Status = ProcessPciHost (
  333. &IoBase,
  334. &IoSize,
  335. &Mmio32Base,
  336. &Mmio32Size,
  337. &Mmio64Base,
  338. &Mmio64Size,
  339. &BusMin,
  340. &BusMax
  341. );
  342. if (EFI_ERROR (Status)) {
  343. DEBUG ((
  344. DEBUG_ERROR,
  345. "%a: failed to discover PCI host bridge: %r\n",
  346. __FUNCTION__,
  347. Status
  348. ));
  349. *Count = 0;
  350. return NULL;
  351. }
  352. ZeroMem (&Io, sizeof (Io));
  353. ZeroMem (&Mem, sizeof (Mem));
  354. ZeroMem (&MemAbove4G, sizeof (MemAbove4G));
  355. ZeroMem (&PMem, sizeof (PMem));
  356. ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));
  357. Attributes = EFI_PCI_ATTRIBUTE_ISA_IO_16 |
  358. EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
  359. EFI_PCI_ATTRIBUTE_VGA_IO_16 |
  360. EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
  361. AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;
  362. if (IoSize != 0) {
  363. Io.Base = IoBase;
  364. Io.Limit = IoBase + IoSize - 1;
  365. } else {
  366. Io.Base = MAX_UINT64;
  367. Io.Limit = 0;
  368. }
  369. Mem.Base = Mmio32Base;
  370. Mem.Limit = Mmio32Base + Mmio32Size - 1;
  371. if ((sizeof (UINTN) == sizeof (UINT64)) && (Mmio64Size != 0)) {
  372. MemAbove4G.Base = Mmio64Base;
  373. MemAbove4G.Limit = Mmio64Base + Mmio64Size - 1;
  374. AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
  375. } else {
  376. //
  377. // UEFI mandates a 1:1 virtual-to-physical mapping, so on a 32-bit
  378. // architecture such as ARM, we will not be able to access 64-bit MMIO
  379. // BARs unless they are allocated below 4 GB. So ignore the range above
  380. // 4 GB in this case.
  381. //
  382. MemAbove4G.Base = MAX_UINT64;
  383. MemAbove4G.Limit = 0;
  384. }
  385. //
  386. // No separate ranges for prefetchable and non-prefetchable BARs
  387. //
  388. PMem.Base = MAX_UINT64;
  389. PMem.Limit = 0;
  390. PMemAbove4G.Base = MAX_UINT64;
  391. PMemAbove4G.Limit = 0;
  392. return PciHostBridgeUtilityGetRootBridges (
  393. Count,
  394. Attributes,
  395. AllocationAttributes,
  396. TRUE,
  397. FALSE,
  398. BusMin,
  399. BusMax,
  400. &Io,
  401. &Mem,
  402. &MemAbove4G,
  403. &PMem,
  404. &PMemAbove4G
  405. );
  406. }
  407. /**
  408. Free the root bridge instances array returned from
  409. PciHostBridgeGetRootBridges().
  410. @param Bridges The root bridge instances array.
  411. @param Count The count of the array.
  412. **/
  413. VOID
  414. EFIAPI
  415. PciHostBridgeFreeRootBridges (
  416. PCI_ROOT_BRIDGE *Bridges,
  417. UINTN Count
  418. )
  419. {
  420. PciHostBridgeUtilityFreeRootBridges (Bridges, Count);
  421. }
  422. /**
  423. Inform the platform that the resource conflict happens.
  424. @param HostBridgeHandle Handle of the Host Bridge.
  425. @param Configuration Pointer to PCI I/O and PCI memory resource
  426. descriptors. The Configuration contains the resources
  427. for all the root bridges. The resource for each root
  428. bridge is terminated with END descriptor and an
  429. additional END is appended indicating the end of the
  430. entire resources. The resource descriptor field
  431. values follow the description in
  432. EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
  433. .SubmitResources().
  434. **/
  435. VOID
  436. EFIAPI
  437. PciHostBridgeResourceConflict (
  438. EFI_HANDLE HostBridgeHandle,
  439. VOID *Configuration
  440. )
  441. {
  442. PciHostBridgeUtilityResourceConflict (Configuration);
  443. }