8259.c 17 KB

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  1. /** @file
  2. This contains the installation function for the driver.
  3. Copyright (c) 2005 - 2018, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "8259.h"
  7. //
  8. // Global for the Legacy 8259 Protocol that is produced by this driver
  9. //
  10. EFI_LEGACY_8259_PROTOCOL mInterrupt8259 = {
  11. Interrupt8259SetVectorBase,
  12. Interrupt8259GetMask,
  13. Interrupt8259SetMask,
  14. Interrupt8259SetMode,
  15. Interrupt8259GetVector,
  16. Interrupt8259EnableIrq,
  17. Interrupt8259DisableIrq,
  18. Interrupt8259GetInterruptLine,
  19. Interrupt8259EndOfInterrupt
  20. };
  21. //
  22. // Global for the handle that the Legacy 8259 Protocol is installed
  23. //
  24. EFI_HANDLE m8259Handle = NULL;
  25. UINT8 mMasterBase = 0xff;
  26. UINT8 mSlaveBase = 0xff;
  27. EFI_8259_MODE mMode = Efi8259ProtectedMode;
  28. UINT16 mProtectedModeMask = 0xffff;
  29. UINT16 mLegacyModeMask;
  30. UINT16 mProtectedModeEdgeLevel = 0x0000;
  31. UINT16 mLegacyModeEdgeLevel;
  32. //
  33. // Worker Functions
  34. //
  35. /**
  36. Write to mask and edge/level triggered registers of master and slave PICs.
  37. @param[in] Mask low byte for master PIC mask register,
  38. high byte for slave PIC mask register.
  39. @param[in] EdgeLevel low byte for master PIC edge/level triggered register,
  40. high byte for slave PIC edge/level triggered register.
  41. **/
  42. VOID
  43. Interrupt8259WriteMask (
  44. IN UINT16 Mask,
  45. IN UINT16 EdgeLevel
  46. )
  47. {
  48. IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8)Mask);
  49. IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8)(Mask >> 8));
  50. IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8)EdgeLevel);
  51. IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8)(EdgeLevel >> 8));
  52. }
  53. /**
  54. Read from mask and edge/level triggered registers of master and slave PICs.
  55. @param[out] Mask low byte for master PIC mask register,
  56. high byte for slave PIC mask register.
  57. @param[out] EdgeLevel low byte for master PIC edge/level triggered register,
  58. high byte for slave PIC edge/level triggered register.
  59. **/
  60. VOID
  61. Interrupt8259ReadMask (
  62. OUT UINT16 *Mask,
  63. OUT UINT16 *EdgeLevel
  64. )
  65. {
  66. UINT16 MasterValue;
  67. UINT16 SlaveValue;
  68. if (Mask != NULL) {
  69. MasterValue = IoRead8 (LEGACY_8259_MASK_REGISTER_MASTER);
  70. SlaveValue = IoRead8 (LEGACY_8259_MASK_REGISTER_SLAVE);
  71. *Mask = (UINT16)(MasterValue | (SlaveValue << 8));
  72. }
  73. if (EdgeLevel != NULL) {
  74. MasterValue = IoRead8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER);
  75. SlaveValue = IoRead8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE);
  76. *EdgeLevel = (UINT16)(MasterValue | (SlaveValue << 8));
  77. }
  78. }
  79. //
  80. // Legacy 8259 Protocol Interface Functions
  81. //
  82. /**
  83. Sets the base address for the 8259 master and slave PICs.
  84. @param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
  85. @param[in] MasterBase Interrupt vectors for IRQ0-IRQ7.
  86. @param[in] SlaveBase Interrupt vectors for IRQ8-IRQ15.
  87. @retval EFI_SUCCESS The 8259 PIC was programmed successfully.
  88. @retval EFI_DEVICE_ERROR There was an error while writing to the 8259 PIC.
  89. **/
  90. EFI_STATUS
  91. EFIAPI
  92. Interrupt8259SetVectorBase (
  93. IN EFI_LEGACY_8259_PROTOCOL *This,
  94. IN UINT8 MasterBase,
  95. IN UINT8 SlaveBase
  96. )
  97. {
  98. UINT8 Mask;
  99. EFI_TPL OriginalTpl;
  100. OriginalTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
  101. //
  102. // Set vector base for slave PIC
  103. //
  104. if (SlaveBase != mSlaveBase) {
  105. mSlaveBase = SlaveBase;
  106. //
  107. // Initialization sequence is needed for setting vector base.
  108. //
  109. //
  110. // Preserve interrtup mask register before initialization sequence
  111. // because it will be cleared during initialization
  112. //
  113. Mask = IoRead8 (LEGACY_8259_MASK_REGISTER_SLAVE);
  114. //
  115. // ICW1: cascade mode, ICW4 write required
  116. //
  117. IoWrite8 (LEGACY_8259_CONTROL_REGISTER_SLAVE, 0x11);
  118. //
  119. // ICW2: new vector base (must be multiple of 8)
  120. //
  121. IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, mSlaveBase);
  122. //
  123. // ICW3: slave indentification code must be 2
  124. //
  125. IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, 0x02);
  126. //
  127. // ICW4: fully nested mode, non-buffered mode, normal EOI, IA processor
  128. //
  129. IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, 0x01);
  130. //
  131. // Restore interrupt mask register
  132. //
  133. IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, Mask);
  134. }
  135. //
  136. // Set vector base for master PIC
  137. //
  138. if (MasterBase != mMasterBase) {
  139. mMasterBase = MasterBase;
  140. //
  141. // Initialization sequence is needed for setting vector base.
  142. //
  143. //
  144. // Preserve interrtup mask register before initialization sequence
  145. // because it will be cleared during initialization
  146. //
  147. Mask = IoRead8 (LEGACY_8259_MASK_REGISTER_MASTER);
  148. //
  149. // ICW1: cascade mode, ICW4 write required
  150. //
  151. IoWrite8 (LEGACY_8259_CONTROL_REGISTER_MASTER, 0x11);
  152. //
  153. // ICW2: new vector base (must be multiple of 8)
  154. //
  155. IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, mMasterBase);
  156. //
  157. // ICW3: slave PIC is cascaded on IRQ2
  158. //
  159. IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, 0x04);
  160. //
  161. // ICW4: fully nested mode, non-buffered mode, normal EOI, IA processor
  162. //
  163. IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, 0x01);
  164. //
  165. // Restore interrupt mask register
  166. //
  167. IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, Mask);
  168. }
  169. IoWrite8 (LEGACY_8259_CONTROL_REGISTER_SLAVE, LEGACY_8259_EOI);
  170. IoWrite8 (LEGACY_8259_CONTROL_REGISTER_MASTER, LEGACY_8259_EOI);
  171. gBS->RestoreTPL (OriginalTpl);
  172. return EFI_SUCCESS;
  173. }
  174. /**
  175. Gets the current 16-bit real mode and 32-bit protected-mode IRQ masks.
  176. @param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
  177. @param[out] LegacyMask 16-bit mode interrupt mask for IRQ0-IRQ15.
  178. @param[out] LegacyEdgeLevel 16-bit mode edge/level mask for IRQ-IRQ15.
  179. @param[out] ProtectedMask 32-bit mode interrupt mask for IRQ0-IRQ15.
  180. @param[out] ProtectedEdgeLevel 32-bit mode edge/level mask for IRQ0-IRQ15.
  181. @retval EFI_SUCCESS The 8259 PIC was programmed successfully.
  182. @retval EFI_DEVICE_ERROR There was an error while reading the 8259 PIC.
  183. **/
  184. EFI_STATUS
  185. EFIAPI
  186. Interrupt8259GetMask (
  187. IN EFI_LEGACY_8259_PROTOCOL *This,
  188. OUT UINT16 *LegacyMask OPTIONAL,
  189. OUT UINT16 *LegacyEdgeLevel OPTIONAL,
  190. OUT UINT16 *ProtectedMask OPTIONAL,
  191. OUT UINT16 *ProtectedEdgeLevel OPTIONAL
  192. )
  193. {
  194. if (LegacyMask != NULL) {
  195. *LegacyMask = mLegacyModeMask;
  196. }
  197. if (LegacyEdgeLevel != NULL) {
  198. *LegacyEdgeLevel = mLegacyModeEdgeLevel;
  199. }
  200. if (ProtectedMask != NULL) {
  201. *ProtectedMask = mProtectedModeMask;
  202. }
  203. if (ProtectedEdgeLevel != NULL) {
  204. *ProtectedEdgeLevel = mProtectedModeEdgeLevel;
  205. }
  206. return EFI_SUCCESS;
  207. }
  208. /**
  209. Sets the current 16-bit real mode and 32-bit protected-mode IRQ masks.
  210. @param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
  211. @param[in] LegacyMask 16-bit mode interrupt mask for IRQ0-IRQ15.
  212. @param[in] LegacyEdgeLevel 16-bit mode edge/level mask for IRQ-IRQ15.
  213. @param[in] ProtectedMask 32-bit mode interrupt mask for IRQ0-IRQ15.
  214. @param[in] ProtectedEdgeLevel 32-bit mode edge/level mask for IRQ0-IRQ15.
  215. @retval EFI_SUCCESS The 8259 PIC was programmed successfully.
  216. @retval EFI_DEVICE_ERROR There was an error while writing the 8259 PIC.
  217. **/
  218. EFI_STATUS
  219. EFIAPI
  220. Interrupt8259SetMask (
  221. IN EFI_LEGACY_8259_PROTOCOL *This,
  222. IN UINT16 *LegacyMask OPTIONAL,
  223. IN UINT16 *LegacyEdgeLevel OPTIONAL,
  224. IN UINT16 *ProtectedMask OPTIONAL,
  225. IN UINT16 *ProtectedEdgeLevel OPTIONAL
  226. )
  227. {
  228. if (LegacyMask != NULL) {
  229. mLegacyModeMask = *LegacyMask;
  230. }
  231. if (LegacyEdgeLevel != NULL) {
  232. mLegacyModeEdgeLevel = *LegacyEdgeLevel;
  233. }
  234. if (ProtectedMask != NULL) {
  235. mProtectedModeMask = *ProtectedMask;
  236. }
  237. if (ProtectedEdgeLevel != NULL) {
  238. mProtectedModeEdgeLevel = *ProtectedEdgeLevel;
  239. }
  240. return EFI_SUCCESS;
  241. }
  242. /**
  243. Sets the mode of the PICs.
  244. @param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
  245. @param[in] Mode 16-bit real or 32-bit protected mode.
  246. @param[in] Mask The value with which to set the interrupt mask.
  247. @param[in] EdgeLevel The value with which to set the edge/level mask.
  248. @retval EFI_SUCCESS The mode was set successfully.
  249. @retval EFI_INVALID_PARAMETER The mode was not set.
  250. **/
  251. EFI_STATUS
  252. EFIAPI
  253. Interrupt8259SetMode (
  254. IN EFI_LEGACY_8259_PROTOCOL *This,
  255. IN EFI_8259_MODE Mode,
  256. IN UINT16 *Mask OPTIONAL,
  257. IN UINT16 *EdgeLevel OPTIONAL
  258. )
  259. {
  260. if (Mode == mMode) {
  261. return EFI_SUCCESS;
  262. }
  263. if (Mode == Efi8259LegacyMode) {
  264. //
  265. // In Efi8259ProtectedMode, mask and edge/level trigger registers should
  266. // be changed through this protocol, so we can track them in the
  267. // corresponding module variables.
  268. //
  269. Interrupt8259ReadMask (&mProtectedModeMask, &mProtectedModeEdgeLevel);
  270. if (Mask != NULL) {
  271. //
  272. // Update the Mask for the new mode
  273. //
  274. mLegacyModeMask = *Mask;
  275. }
  276. if (EdgeLevel != NULL) {
  277. //
  278. // Update the Edge/Level triggered mask for the new mode
  279. //
  280. mLegacyModeEdgeLevel = *EdgeLevel;
  281. }
  282. mMode = Mode;
  283. //
  284. // Write new legacy mode mask/trigger level
  285. //
  286. Interrupt8259WriteMask (mLegacyModeMask, mLegacyModeEdgeLevel);
  287. return EFI_SUCCESS;
  288. }
  289. if (Mode == Efi8259ProtectedMode) {
  290. //
  291. // Save the legacy mode mask/trigger level
  292. //
  293. Interrupt8259ReadMask (&mLegacyModeMask, &mLegacyModeEdgeLevel);
  294. //
  295. // Always force Timer to be enabled after return from 16-bit code.
  296. // This always insures that on next entry, timer is counting.
  297. //
  298. mLegacyModeMask &= 0xFFFE;
  299. if (Mask != NULL) {
  300. //
  301. // Update the Mask for the new mode
  302. //
  303. mProtectedModeMask = *Mask;
  304. }
  305. if (EdgeLevel != NULL) {
  306. //
  307. // Update the Edge/Level triggered mask for the new mode
  308. //
  309. mProtectedModeEdgeLevel = *EdgeLevel;
  310. }
  311. mMode = Mode;
  312. //
  313. // Write new protected mode mask/trigger level
  314. //
  315. Interrupt8259WriteMask (mProtectedModeMask, mProtectedModeEdgeLevel);
  316. return EFI_SUCCESS;
  317. }
  318. return EFI_INVALID_PARAMETER;
  319. }
  320. /**
  321. Translates the IRQ into a vector.
  322. @param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
  323. @param[in] Irq IRQ0-IRQ15.
  324. @param[out] Vector The vector that is assigned to the IRQ.
  325. @retval EFI_SUCCESS The Vector that matches Irq was returned.
  326. @retval EFI_INVALID_PARAMETER Irq is not valid.
  327. **/
  328. EFI_STATUS
  329. EFIAPI
  330. Interrupt8259GetVector (
  331. IN EFI_LEGACY_8259_PROTOCOL *This,
  332. IN EFI_8259_IRQ Irq,
  333. OUT UINT8 *Vector
  334. )
  335. {
  336. if ((UINT32)Irq > Efi8259Irq15) {
  337. return EFI_INVALID_PARAMETER;
  338. }
  339. if (Irq <= Efi8259Irq7) {
  340. *Vector = (UINT8)(mMasterBase + Irq);
  341. } else {
  342. *Vector = (UINT8)(mSlaveBase + (Irq - Efi8259Irq8));
  343. }
  344. return EFI_SUCCESS;
  345. }
  346. /**
  347. Enables the specified IRQ.
  348. @param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
  349. @param[in] Irq IRQ0-IRQ15.
  350. @param[in] LevelTriggered 0 = Edge triggered; 1 = Level triggered.
  351. @retval EFI_SUCCESS The Irq was enabled on the 8259 PIC.
  352. @retval EFI_INVALID_PARAMETER The Irq is not valid.
  353. **/
  354. EFI_STATUS
  355. EFIAPI
  356. Interrupt8259EnableIrq (
  357. IN EFI_LEGACY_8259_PROTOCOL *This,
  358. IN EFI_8259_IRQ Irq,
  359. IN BOOLEAN LevelTriggered
  360. )
  361. {
  362. if ((UINT32)Irq > Efi8259Irq15) {
  363. return EFI_INVALID_PARAMETER;
  364. }
  365. mProtectedModeMask = (UINT16)(mProtectedModeMask & ~(1 << Irq));
  366. if (LevelTriggered) {
  367. mProtectedModeEdgeLevel = (UINT16)(mProtectedModeEdgeLevel | (1 << Irq));
  368. } else {
  369. mProtectedModeEdgeLevel = (UINT16)(mProtectedModeEdgeLevel & ~(1 << Irq));
  370. }
  371. Interrupt8259WriteMask (mProtectedModeMask, mProtectedModeEdgeLevel);
  372. return EFI_SUCCESS;
  373. }
  374. /**
  375. Disables the specified IRQ.
  376. @param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
  377. @param[in] Irq IRQ0-IRQ15.
  378. @retval EFI_SUCCESS The Irq was disabled on the 8259 PIC.
  379. @retval EFI_INVALID_PARAMETER The Irq is not valid.
  380. **/
  381. EFI_STATUS
  382. EFIAPI
  383. Interrupt8259DisableIrq (
  384. IN EFI_LEGACY_8259_PROTOCOL *This,
  385. IN EFI_8259_IRQ Irq
  386. )
  387. {
  388. if ((UINT32)Irq > Efi8259Irq15) {
  389. return EFI_INVALID_PARAMETER;
  390. }
  391. mProtectedModeMask = (UINT16)(mProtectedModeMask | (1 << Irq));
  392. mProtectedModeEdgeLevel = (UINT16)(mProtectedModeEdgeLevel & ~(1 << Irq));
  393. Interrupt8259WriteMask (mProtectedModeMask, mProtectedModeEdgeLevel);
  394. return EFI_SUCCESS;
  395. }
  396. /**
  397. Reads the PCI configuration space to get the interrupt number that is assigned to the card.
  398. @param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
  399. @param[in] PciHandle PCI function for which to return the vector.
  400. @param[out] Vector IRQ number that corresponds to the interrupt line.
  401. @retval EFI_SUCCESS The interrupt line value was read successfully.
  402. **/
  403. EFI_STATUS
  404. EFIAPI
  405. Interrupt8259GetInterruptLine (
  406. IN EFI_LEGACY_8259_PROTOCOL *This,
  407. IN EFI_HANDLE PciHandle,
  408. OUT UINT8 *Vector
  409. )
  410. {
  411. EFI_PCI_IO_PROTOCOL *PciIo;
  412. UINT8 InterruptLine;
  413. EFI_STATUS Status;
  414. Status = gBS->HandleProtocol (
  415. PciHandle,
  416. &gEfiPciIoProtocolGuid,
  417. (VOID **)&PciIo
  418. );
  419. if (EFI_ERROR (Status)) {
  420. return EFI_INVALID_PARAMETER;
  421. }
  422. PciIo->Pci.Read (
  423. PciIo,
  424. EfiPciIoWidthUint8,
  425. PCI_INT_LINE_OFFSET,
  426. 1,
  427. &InterruptLine
  428. );
  429. //
  430. // Interrupt line is same location for standard PCI cards, standard
  431. // bridge and CardBus bridge.
  432. //
  433. *Vector = InterruptLine;
  434. return EFI_SUCCESS;
  435. }
  436. /**
  437. Issues the End of Interrupt (EOI) commands to PICs.
  438. @param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
  439. @param[in] Irq The interrupt for which to issue the EOI command.
  440. @retval EFI_SUCCESS The EOI command was issued.
  441. @retval EFI_INVALID_PARAMETER The Irq is not valid.
  442. **/
  443. EFI_STATUS
  444. EFIAPI
  445. Interrupt8259EndOfInterrupt (
  446. IN EFI_LEGACY_8259_PROTOCOL *This,
  447. IN EFI_8259_IRQ Irq
  448. )
  449. {
  450. if ((UINT32)Irq > Efi8259Irq15) {
  451. return EFI_INVALID_PARAMETER;
  452. }
  453. if (Irq >= Efi8259Irq8) {
  454. IoWrite8 (LEGACY_8259_CONTROL_REGISTER_SLAVE, LEGACY_8259_EOI);
  455. }
  456. IoWrite8 (LEGACY_8259_CONTROL_REGISTER_MASTER, LEGACY_8259_EOI);
  457. return EFI_SUCCESS;
  458. }
  459. /**
  460. Driver Entry point.
  461. @param[in] ImageHandle ImageHandle of the loaded driver.
  462. @param[in] SystemTable Pointer to the EFI System Table.
  463. @retval EFI_SUCCESS One or more of the drivers returned a success code.
  464. @retval !EFI_SUCCESS Error installing Legacy 8259 Protocol.
  465. **/
  466. EFI_STATUS
  467. EFIAPI
  468. Install8259 (
  469. IN EFI_HANDLE ImageHandle,
  470. IN EFI_SYSTEM_TABLE *SystemTable
  471. )
  472. {
  473. EFI_STATUS Status;
  474. EFI_8259_IRQ Irq;
  475. //
  476. // Initialze mask values from PCDs
  477. //
  478. mLegacyModeMask = PcdGet16 (Pcd8259LegacyModeMask);
  479. mLegacyModeEdgeLevel = PcdGet16 (Pcd8259LegacyModeEdgeLevel);
  480. //
  481. // Clear all pending interrupt
  482. //
  483. for (Irq = Efi8259Irq0; Irq <= Efi8259Irq15; Irq++) {
  484. Interrupt8259EndOfInterrupt (&mInterrupt8259, Irq);
  485. }
  486. //
  487. // Set the 8259 Master base to 0x68 and the 8259 Slave base to 0x70
  488. //
  489. Status = Interrupt8259SetVectorBase (&mInterrupt8259, PROTECTED_MODE_BASE_VECTOR_MASTER, PROTECTED_MODE_BASE_VECTOR_SLAVE);
  490. //
  491. // Set all 8259 interrupts to edge triggered and disabled
  492. //
  493. Interrupt8259WriteMask (mProtectedModeMask, mProtectedModeEdgeLevel);
  494. //
  495. // Install 8259 Protocol onto a new handle
  496. //
  497. Status = gBS->InstallProtocolInterface (
  498. &m8259Handle,
  499. &gEfiLegacy8259ProtocolGuid,
  500. EFI_NATIVE_INTERFACE,
  501. &mInterrupt8259
  502. );
  503. return Status;
  504. }