ArmV7.h 3.3 KB

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  1. /** @file
  2. Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
  3. Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef __ARM_V7_H__
  7. #define __ARM_V7_H__
  8. #include <Chipset/ArmV7Mmu.h>
  9. // ARM Interrupt ID in Exception Table
  10. #define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ
  11. // ID_PFR1 - ARM Processor Feature Register 1 definitions
  12. #define ARM_PFR1_SEC (0xFUL << 4)
  13. #define ARM_PFR1_TIMER (0xFUL << 16)
  14. #define ARM_PFR1_GIC (0xFUL << 28)
  15. // Domain Access Control Register
  16. #define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
  17. #define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))
  18. #define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))
  19. #define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
  20. #define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
  21. // CPSR - Coprocessor Status Register definitions
  22. #define CPSR_MODE_USER 0x10
  23. #define CPSR_MODE_FIQ 0x11
  24. #define CPSR_MODE_IRQ 0x12
  25. #define CPSR_MODE_SVC 0x13
  26. #define CPSR_MODE_ABORT 0x17
  27. #define CPSR_MODE_HYP 0x1A
  28. #define CPSR_MODE_UNDEFINED 0x1B
  29. #define CPSR_MODE_SYSTEM 0x1F
  30. #define CPSR_MODE_MASK 0x1F
  31. #define CPSR_ASYNC_ABORT (1 << 8)
  32. #define CPSR_IRQ (1 << 7)
  33. #define CPSR_FIQ (1 << 6)
  34. // CPACR - Coprocessor Access Control Register definitions
  35. #define CPACR_CP_DENIED(cp) 0x00
  36. #define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
  37. #define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
  38. #define CPACR_ASEDIS (1 << 31)
  39. #define CPACR_D32DIS (1 << 30)
  40. #define CPACR_CP_FULL_ACCESS 0x0FFFFFFF
  41. // NSACR - Non-Secure Access Control Register definitions
  42. #define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)
  43. #define NSACR_NSD32DIS (1 << 14)
  44. #define NSACR_NSASEDIS (1 << 15)
  45. #define NSACR_PLE (1 << 16)
  46. #define NSACR_TL (1 << 17)
  47. #define NSACR_NS_SMP (1 << 18)
  48. #define NSACR_RFR (1 << 19)
  49. // SCR - Secure Configuration Register definitions
  50. #define SCR_NS (1 << 0)
  51. #define SCR_IRQ (1 << 1)
  52. #define SCR_FIQ (1 << 2)
  53. #define SCR_EA (1 << 3)
  54. #define SCR_FW (1 << 4)
  55. #define SCR_AW (1 << 5)
  56. // MIDR - Main ID Register definitions
  57. #define ARM_CPU_TYPE_SHIFT 4
  58. #define ARM_CPU_TYPE_MASK 0xFFF
  59. #define ARM_CPU_TYPE_AEMV8 0xD0F
  60. #define ARM_CPU_TYPE_A53 0xD03
  61. #define ARM_CPU_TYPE_A57 0xD07
  62. #define ARM_CPU_TYPE_A15 0xC0F
  63. #define ARM_CPU_TYPE_A12 0xC0D
  64. #define ARM_CPU_TYPE_A9 0xC09
  65. #define ARM_CPU_TYPE_A7 0xC07
  66. #define ARM_CPU_TYPE_A5 0xC05
  67. #define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
  68. #define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
  69. #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
  70. VOID
  71. EFIAPI
  72. ArmEnableSWPInstruction (
  73. VOID
  74. );
  75. UINTN
  76. EFIAPI
  77. ArmReadCbar (
  78. VOID
  79. );
  80. UINTN
  81. EFIAPI
  82. ArmReadTpidrurw (
  83. VOID
  84. );
  85. VOID
  86. EFIAPI
  87. ArmWriteTpidrurw (
  88. UINTN Value
  89. );
  90. UINT32
  91. EFIAPI
  92. ArmReadNsacr (
  93. VOID
  94. );
  95. VOID
  96. EFIAPI
  97. ArmWriteNsacr (
  98. IN UINT32 Nsacr
  99. );
  100. #endif // __ARM_V7_H__