AArch64Mmu.h 9.3 KB

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  1. /** @file
  2. *
  3. * Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
  4. *
  5. * SPDX-License-Identifier: BSD-2-Clause-Patent
  6. *
  7. **/
  8. #ifndef __AARCH64_MMU_H_
  9. #define __AARCH64_MMU_H_
  10. //
  11. // Memory Attribute Indirection register Definitions
  12. //
  13. #define MAIR_ATTR_DEVICE_MEMORY 0x0ULL
  14. #define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE 0x44ULL
  15. #define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH 0xBBULL
  16. #define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK 0xFFULL
  17. #define MAIR_ATTR(n,value) ((value) << (((n) >> 2)*8))
  18. //
  19. // Long-descriptor Translation Table format
  20. //
  21. // Return the smallest offset from the table level.
  22. // The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0
  23. #define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel) (12 + ((3 - (TableLevel)) * 9))
  24. #define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level))
  25. // Get the associated entry in the given Translation Table
  26. #define TT_GET_ENTRY_FOR_ADDRESS(TranslationTable, Level, Address) \
  27. ((UINTN)(TranslationTable) + ((((UINTN)(Address) >> TT_ADDRESS_OFFSET_AT_LEVEL(Level)) & (BIT9-1)) * sizeof(UINT64)))
  28. // Return the smallest address granularity from the table level.
  29. // The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0
  30. #define TT_ADDRESS_AT_LEVEL(TableLevel) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))
  31. #define TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount) \
  32. ((UINT64*)((EFI_PHYSICAL_ADDRESS)(TranslationTable) + (((EntryCount) - 1) * sizeof(UINT64))))
  33. // There are 512 entries per table when 4K Granularity
  34. #define TT_ENTRY_COUNT 512
  35. #define TT_ALIGNMENT_BLOCK_ENTRY BIT12
  36. #define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12
  37. #define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12)
  38. #define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12)
  39. #define TT_TYPE_MASK 0x3
  40. #define TT_TYPE_TABLE_ENTRY 0x3
  41. #define TT_TYPE_BLOCK_ENTRY 0x1
  42. #define TT_TYPE_BLOCK_ENTRY_LEVEL3 0x3
  43. #define TT_ATTR_INDX_MASK (0x7 << 2)
  44. #define TT_ATTR_INDX_DEVICE_MEMORY (0x0 << 2)
  45. #define TT_ATTR_INDX_MEMORY_NON_CACHEABLE (0x1 << 2)
  46. #define TT_ATTR_INDX_MEMORY_WRITE_THROUGH (0x2 << 2)
  47. #define TT_ATTR_INDX_MEMORY_WRITE_BACK (0x3 << 2)
  48. #define TT_AP_MASK (0x3UL << 6)
  49. #define TT_AP_NO_RW (0x0UL << 6)
  50. #define TT_AP_RW_RW (0x1UL << 6)
  51. #define TT_AP_NO_RO (0x2UL << 6)
  52. #define TT_AP_RO_RO (0x3UL << 6)
  53. #define TT_NS BIT5
  54. #define TT_AF BIT10
  55. #define TT_SH_NON_SHAREABLE (0x0 << 8)
  56. #define TT_SH_OUTER_SHAREABLE (0x2 << 8)
  57. #define TT_SH_INNER_SHAREABLE (0x3 << 8)
  58. #define TT_SH_MASK (0x3 << 8)
  59. #define TT_PXN_MASK BIT53
  60. #define TT_UXN_MASK BIT54 // EL1&0
  61. #define TT_XN_MASK BIT54 // EL2 / EL3
  62. #define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL << 2))
  63. #define TT_TABLE_PXN BIT59
  64. #define TT_TABLE_UXN BIT60 // EL1&0
  65. #define TT_TABLE_XN BIT60 // EL2 / EL3
  66. #define TT_TABLE_NS BIT63
  67. #define TT_TABLE_AP_MASK (BIT62 | BIT61)
  68. #define TT_TABLE_AP_NO_PERMISSION (0x0ULL << 61)
  69. #define TT_TABLE_AP_EL0_NO_ACCESS (0x1ULL << 61)
  70. #define TT_TABLE_AP_NO_WRITE_ACCESS (0x2ULL << 61)
  71. //
  72. // Translation Control Register
  73. //
  74. #define TCR_T0SZ_MASK 0x3FUL
  75. #define TCR_PS_4GB (0UL << 16)
  76. #define TCR_PS_64GB (1UL << 16)
  77. #define TCR_PS_1TB (2UL << 16)
  78. #define TCR_PS_4TB (3UL << 16)
  79. #define TCR_PS_16TB (4UL << 16)
  80. #define TCR_PS_256TB (5UL << 16)
  81. #define TCR_TG0_4KB (0UL << 14)
  82. #define TCR_TG1_4KB (2UL << 30)
  83. #define TCR_IPS_4GB (0ULL << 32)
  84. #define TCR_IPS_64GB (1ULL << 32)
  85. #define TCR_IPS_1TB (2ULL << 32)
  86. #define TCR_IPS_4TB (3ULL << 32)
  87. #define TCR_IPS_16TB (4ULL << 32)
  88. #define TCR_IPS_256TB (5ULL << 32)
  89. #define TCR_EPD1 (1UL << 23)
  90. #define TTBR_ASID_FIELD (48)
  91. #define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD)
  92. #define TTBR_BADDR_MASK (0xFFFFFFFFFFFF ) // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits
  93. #define TCR_EL1_T0SZ_FIELD (0)
  94. #define TCR_EL1_EPD0_FIELD (7)
  95. #define TCR_EL1_IRGN0_FIELD (8)
  96. #define TCR_EL1_ORGN0_FIELD (10)
  97. #define TCR_EL1_SH0_FIELD (12)
  98. #define TCR_EL1_TG0_FIELD (14)
  99. #define TCR_EL1_T1SZ_FIELD (16)
  100. #define TCR_EL1_A1_FIELD (22)
  101. #define TCR_EL1_EPD1_FIELD (23)
  102. #define TCR_EL1_IRGN1_FIELD (24)
  103. #define TCR_EL1_ORGN1_FIELD (26)
  104. #define TCR_EL1_SH1_FIELD (28)
  105. #define TCR_EL1_TG1_FIELD (30)
  106. #define TCR_EL1_IPS_FIELD (32)
  107. #define TCR_EL1_AS_FIELD (36)
  108. #define TCR_EL1_TBI0_FIELD (37)
  109. #define TCR_EL1_TBI1_FIELD (38)
  110. #define TCR_EL1_T0SZ_MASK (0x1FUL << TCR_EL1_T0SZ_FIELD)
  111. #define TCR_EL1_EPD0_MASK (0x01UL << TCR_EL1_EPD0_FIELD)
  112. #define TCR_EL1_IRGN0_MASK (0x03UL << TCR_EL1_IRGN0_FIELD)
  113. #define TCR_EL1_ORGN0_MASK (0x03UL << TCR_EL1_ORGN0_FIELD)
  114. #define TCR_EL1_SH0_MASK (0x03UL << TCR_EL1_SH0_FIELD)
  115. #define TCR_EL1_TG0_MASK (0x01UL << TCR_EL1_TG0_FIELD)
  116. #define TCR_EL1_T1SZ_MASK (0x1FUL << TCR_EL1_T1SZ_FIELD)
  117. #define TCR_EL1_A1_MASK (0x01UL << TCR_EL1_A1_FIELD)
  118. #define TCR_EL1_EPD1_MASK (0x01UL << TCR_EL1_EPD1_FIELD)
  119. #define TCR_EL1_IRGN1_MASK (0x03UL << TCR_EL1_IRGN1_FIELD)
  120. #define TCR_EL1_ORGN1_MASK (0x03UL << TCR_EL1_ORGN1_FIELD)
  121. #define TCR_EL1_SH1_MASK (0x03UL << TCR_EL1_SH1_FIELD)
  122. #define TCR_EL1_TG1_MASK (0x01UL << TCR_EL1_TG1_FIELD)
  123. #define TCR_EL1_IPS_MASK (0x07UL << TCR_EL1_IPS_FIELD)
  124. #define TCR_EL1_AS_MASK (0x01UL << TCR_EL1_AS_FIELD)
  125. #define TCR_EL1_TBI0_MASK (0x01UL << TCR_EL1_TBI0_FIELD)
  126. #define TCR_EL1_TBI1_MASK (0x01UL << TCR_EL1_TBI1_FIELD)
  127. #define TCR_EL23_T0SZ_FIELD (0)
  128. #define TCR_EL23_IRGN0_FIELD (8)
  129. #define TCR_EL23_ORGN0_FIELD (10)
  130. #define TCR_EL23_SH0_FIELD (12)
  131. #define TCR_EL23_TG0_FIELD (14)
  132. #define TCR_EL23_PS_FIELD (16)
  133. #define TCR_EL23_T0SZ_MASK (0x1FUL << TCR_EL23_T0SZ_FIELD)
  134. #define TCR_EL23_IRGN0_MASK (0x03UL << TCR_EL23_IRGN0_FIELD)
  135. #define TCR_EL23_ORGN0_MASK (0x03UL << TCR_EL23_ORGN0_FIELD)
  136. #define TCR_EL23_SH0_MASK (0x03UL << TCR_EL23_SH0_FIELD)
  137. #define TCR_EL23_TG0_MASK (0x01UL << TCR_EL23_TG0_FIELD)
  138. #define TCR_EL23_PS_MASK (0x07UL << TCR_EL23_PS_FIELD)
  139. #define TCR_RGN_OUTER_NON_CACHEABLE (0x0UL << 10)
  140. #define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1UL << 10)
  141. #define TCR_RGN_OUTER_WRITE_THROUGH (0x2UL << 10)
  142. #define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3UL << 10)
  143. #define TCR_RGN_INNER_NON_CACHEABLE (0x0UL << 8)
  144. #define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1UL << 8)
  145. #define TCR_RGN_INNER_WRITE_THROUGH (0x2UL << 8)
  146. #define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3UL << 8)
  147. #define TCR_SH_NON_SHAREABLE (0x0UL << 12)
  148. #define TCR_SH_OUTER_SHAREABLE (0x2UL << 12)
  149. #define TCR_SH_INNER_SHAREABLE (0x3UL << 12)
  150. #define TCR_PASZ_32BITS_4GB (0x0UL)
  151. #define TCR_PASZ_36BITS_64GB (0x1UL)
  152. #define TCR_PASZ_40BITS_1TB (0x2UL)
  153. #define TCR_PASZ_42BITS_4TB (0x3UL)
  154. #define TCR_PASZ_44BITS_16TB (0x4UL)
  155. #define TCR_PASZ_48BITS_256TB (0x5UL)
  156. // The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit
  157. // Virtual address range for 512GB of virtual space sets T*SZ to 25
  158. #define INPUT_ADDRESS_SIZE_TO_TXSZ(a) (64 - a)
  159. // Uses LPAE Page Table format
  160. #endif // __AARCH64_MMU_H_