AArch64.h 5.0 KB

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  1. /** @file
  2. Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
  3. Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef __AARCH64_H__
  7. #define __AARCH64_H__
  8. #include <Chipset/AArch64Mmu.h>
  9. // ARM Interrupt ID in Exception Table
  10. #define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ
  11. // CPACR - Coprocessor Access Control Register definitions
  12. #define CPACR_TTA_EN (1UL << 28)
  13. #define CPACR_FPEN_EL1 (1UL << 20)
  14. #define CPACR_FPEN_FULL (3UL << 20)
  15. #define CPACR_CP_FULL_ACCESS 0x300000
  16. // Coprocessor Trap Register (CPTR)
  17. #define AARCH64_CPTR_TFP (1 << 10)
  18. // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
  19. #define AARCH64_PFR0_FP (0xF << 16)
  20. #define AARCH64_PFR0_GIC (0xF << 24)
  21. // SCR - Secure Configuration Register definitions
  22. #define SCR_NS (1 << 0)
  23. #define SCR_IRQ (1 << 1)
  24. #define SCR_FIQ (1 << 2)
  25. #define SCR_EA (1 << 3)
  26. #define SCR_FW (1 << 4)
  27. #define SCR_AW (1 << 5)
  28. // MIDR - Main ID Register definitions
  29. #define ARM_CPU_TYPE_SHIFT 4
  30. #define ARM_CPU_TYPE_MASK 0xFFF
  31. #define ARM_CPU_TYPE_AEMV8 0xD0F
  32. #define ARM_CPU_TYPE_A53 0xD03
  33. #define ARM_CPU_TYPE_A57 0xD07
  34. #define ARM_CPU_TYPE_A72 0xD08
  35. #define ARM_CPU_TYPE_A15 0xC0F
  36. #define ARM_CPU_TYPE_A9 0xC09
  37. #define ARM_CPU_TYPE_A7 0xC07
  38. #define ARM_CPU_TYPE_A5 0xC05
  39. #define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
  40. #define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
  41. // Hypervisor Configuration Register
  42. #define ARM_HCR_FMO BIT3
  43. #define ARM_HCR_IMO BIT4
  44. #define ARM_HCR_AMO BIT5
  45. #define ARM_HCR_TSC BIT19
  46. #define ARM_HCR_TGE BIT27
  47. // Exception Syndrome Register
  48. #define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))
  49. #define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr))
  50. #define AARCH64_ESR_EC_SMC32 (0x13 << 26)
  51. #define AARCH64_ESR_EC_SMC64 (0x17 << 26)
  52. // AArch64 Exception Level
  53. #define AARCH64_EL3 0xC
  54. #define AARCH64_EL2 0x8
  55. #define AARCH64_EL1 0x4
  56. // Saved Program Status Register definitions
  57. #define SPSR_A BIT8
  58. #define SPSR_I BIT7
  59. #define SPSR_F BIT6
  60. #define SPSR_AARCH32 BIT4
  61. #define SPSR_AARCH32_MODE_USER 0x0
  62. #define SPSR_AARCH32_MODE_FIQ 0x1
  63. #define SPSR_AARCH32_MODE_IRQ 0x2
  64. #define SPSR_AARCH32_MODE_SVC 0x3
  65. #define SPSR_AARCH32_MODE_ABORT 0x7
  66. #define SPSR_AARCH32_MODE_UNDEF 0xB
  67. #define SPSR_AARCH32_MODE_SYS 0xF
  68. // Counter-timer Hypervisor Control register definitions
  69. #define CNTHCTL_EL2_EL1PCTEN BIT0
  70. #define CNTHCTL_EL2_EL1PCEN BIT1
  71. #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
  72. // Vector table offset definitions
  73. #define ARM_VECTOR_CUR_SP0_SYNC 0x000
  74. #define ARM_VECTOR_CUR_SP0_IRQ 0x080
  75. #define ARM_VECTOR_CUR_SP0_FIQ 0x100
  76. #define ARM_VECTOR_CUR_SP0_SERR 0x180
  77. #define ARM_VECTOR_CUR_SPX_SYNC 0x200
  78. #define ARM_VECTOR_CUR_SPX_IRQ 0x280
  79. #define ARM_VECTOR_CUR_SPX_FIQ 0x300
  80. #define ARM_VECTOR_CUR_SPX_SERR 0x380
  81. #define ARM_VECTOR_LOW_A64_SYNC 0x400
  82. #define ARM_VECTOR_LOW_A64_IRQ 0x480
  83. #define ARM_VECTOR_LOW_A64_FIQ 0x500
  84. #define ARM_VECTOR_LOW_A64_SERR 0x580
  85. #define ARM_VECTOR_LOW_A32_SYNC 0x600
  86. #define ARM_VECTOR_LOW_A32_IRQ 0x680
  87. #define ARM_VECTOR_LOW_A32_FIQ 0x700
  88. #define ARM_VECTOR_LOW_A32_SERR 0x780
  89. // The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we
  90. // build for ARMv8.0, we need to define the register here.
  91. #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
  92. #define VECTOR_BASE(tbl) \
  93. .section .text.##tbl##,"ax"; \
  94. .align 11; \
  95. .org 0x0; \
  96. GCC_ASM_EXPORT(tbl); \
  97. ASM_PFX(tbl): \
  98. #define VECTOR_ENTRY(tbl, off) \
  99. .org off
  100. #define VECTOR_END(tbl) \
  101. .org 0x800; \
  102. .previous
  103. VOID
  104. EFIAPI
  105. ArmEnableSWPInstruction (
  106. VOID
  107. );
  108. UINTN
  109. EFIAPI
  110. ArmReadCbar (
  111. VOID
  112. );
  113. UINTN
  114. EFIAPI
  115. ArmReadTpidrurw (
  116. VOID
  117. );
  118. VOID
  119. EFIAPI
  120. ArmWriteTpidrurw (
  121. UINTN Value
  122. );
  123. UINTN
  124. EFIAPI
  125. ArmGetTCR (
  126. VOID
  127. );
  128. VOID
  129. EFIAPI
  130. ArmSetTCR (
  131. UINTN Value
  132. );
  133. UINTN
  134. EFIAPI
  135. ArmGetMAIR (
  136. VOID
  137. );
  138. VOID
  139. EFIAPI
  140. ArmSetMAIR (
  141. UINTN Value
  142. );
  143. VOID
  144. EFIAPI
  145. ArmDisableAlignmentCheck (
  146. VOID
  147. );
  148. VOID
  149. EFIAPI
  150. ArmEnableAlignmentCheck (
  151. VOID
  152. );
  153. VOID
  154. EFIAPI
  155. ArmDisableStackAlignmentCheck (
  156. VOID
  157. );
  158. VOID
  159. EFIAPI
  160. ArmEnableStackAlignmentCheck (
  161. VOID
  162. );
  163. VOID
  164. EFIAPI
  165. ArmDisableAllExceptions (
  166. VOID
  167. );
  168. VOID
  169. ArmWriteHcr (
  170. IN UINTN Hcr
  171. );
  172. UINTN
  173. ArmReadHcr (
  174. VOID
  175. );
  176. UINTN
  177. ArmReadCurrentEL (
  178. VOID
  179. );
  180. UINTN
  181. ArmWriteCptr (
  182. IN UINT64 Cptr
  183. );
  184. UINT32
  185. ArmReadCntHctl (
  186. VOID
  187. );
  188. VOID
  189. ArmWriteCntHctl (
  190. IN UINT32 CntHctl
  191. );
  192. #endif // __AARCH64_H__