IdeMode.c 83 KB

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  1. /** @file
  2. Header file for AHCI mode of ATA host controller.
  3. Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "AtaAtapiPassThru.h"
  7. /**
  8. read a one-byte data from a IDE port.
  9. @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure
  10. @param Port The IDE Port number
  11. @return the one-byte data read from IDE port
  12. **/
  13. UINT8
  14. EFIAPI
  15. IdeReadPortB (
  16. IN EFI_PCI_IO_PROTOCOL *PciIo,
  17. IN UINT16 Port
  18. )
  19. {
  20. UINT8 Data;
  21. ASSERT (PciIo != NULL);
  22. Data = 0;
  23. //
  24. // perform 1-byte data read from register
  25. //
  26. PciIo->Io.Read (
  27. PciIo,
  28. EfiPciIoWidthUint8,
  29. EFI_PCI_IO_PASS_THROUGH_BAR,
  30. (UINT64) Port,
  31. 1,
  32. &Data
  33. );
  34. return Data;
  35. }
  36. /**
  37. write a 1-byte data to a specific IDE port.
  38. @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure
  39. @param Port The IDE port to be writen
  40. @param Data The data to write to the port
  41. **/
  42. VOID
  43. EFIAPI
  44. IdeWritePortB (
  45. IN EFI_PCI_IO_PROTOCOL *PciIo,
  46. IN UINT16 Port,
  47. IN UINT8 Data
  48. )
  49. {
  50. ASSERT (PciIo != NULL);
  51. //
  52. // perform 1-byte data write to register
  53. //
  54. PciIo->Io.Write (
  55. PciIo,
  56. EfiPciIoWidthUint8,
  57. EFI_PCI_IO_PASS_THROUGH_BAR,
  58. (UINT64) Port,
  59. 1,
  60. &Data
  61. );
  62. }
  63. /**
  64. write a 1-word data to a specific IDE port.
  65. @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure
  66. @param Port The IDE port to be writen
  67. @param Data The data to write to the port
  68. **/
  69. VOID
  70. EFIAPI
  71. IdeWritePortW (
  72. IN EFI_PCI_IO_PROTOCOL *PciIo,
  73. IN UINT16 Port,
  74. IN UINT16 Data
  75. )
  76. {
  77. ASSERT (PciIo != NULL);
  78. //
  79. // perform 1-word data write to register
  80. //
  81. PciIo->Io.Write (
  82. PciIo,
  83. EfiPciIoWidthUint16,
  84. EFI_PCI_IO_PASS_THROUGH_BAR,
  85. (UINT64) Port,
  86. 1,
  87. &Data
  88. );
  89. }
  90. /**
  91. write a 2-word data to a specific IDE port.
  92. @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure
  93. @param Port The IDE port to be writen
  94. @param Data The data to write to the port
  95. **/
  96. VOID
  97. EFIAPI
  98. IdeWritePortDW (
  99. IN EFI_PCI_IO_PROTOCOL *PciIo,
  100. IN UINT16 Port,
  101. IN UINT32 Data
  102. )
  103. {
  104. ASSERT (PciIo != NULL);
  105. //
  106. // perform 2-word data write to register
  107. //
  108. PciIo->Io.Write (
  109. PciIo,
  110. EfiPciIoWidthUint32,
  111. EFI_PCI_IO_PASS_THROUGH_BAR,
  112. (UINT64) Port,
  113. 1,
  114. &Data
  115. );
  116. }
  117. /**
  118. Write multiple words of data to the IDE data port.
  119. Call the IO abstraction once to do the complete read,
  120. not one word at a time
  121. @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure
  122. @param Port IO port to read
  123. @param Count No. of UINT16's to read
  124. @param Buffer Pointer to the data buffer for read
  125. **/
  126. VOID
  127. EFIAPI
  128. IdeWritePortWMultiple (
  129. IN EFI_PCI_IO_PROTOCOL *PciIo,
  130. IN UINT16 Port,
  131. IN UINTN Count,
  132. IN VOID *Buffer
  133. )
  134. {
  135. ASSERT (PciIo != NULL);
  136. ASSERT (Buffer != NULL);
  137. //
  138. // perform UINT16 data write to the FIFO
  139. //
  140. PciIo->Io.Write (
  141. PciIo,
  142. EfiPciIoWidthFifoUint16,
  143. EFI_PCI_IO_PASS_THROUGH_BAR,
  144. (UINT64) Port,
  145. Count,
  146. (UINT16 *) Buffer
  147. );
  148. }
  149. /**
  150. Reads multiple words of data from the IDE data port.
  151. Call the IO abstraction once to do the complete read,
  152. not one word at a time
  153. @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure
  154. @param Port IO port to read
  155. @param Count Number of UINT16's to read
  156. @param Buffer Pointer to the data buffer for read
  157. **/
  158. VOID
  159. EFIAPI
  160. IdeReadPortWMultiple (
  161. IN EFI_PCI_IO_PROTOCOL *PciIo,
  162. IN UINT16 Port,
  163. IN UINTN Count,
  164. IN VOID *Buffer
  165. )
  166. {
  167. ASSERT (PciIo != NULL);
  168. ASSERT (Buffer != NULL);
  169. //
  170. // Perform UINT16 data read from FIFO
  171. //
  172. PciIo->Io.Read (
  173. PciIo,
  174. EfiPciIoWidthFifoUint16,
  175. EFI_PCI_IO_PASS_THROUGH_BAR,
  176. (UINT64) Port,
  177. Count,
  178. (UINT16 *) Buffer
  179. );
  180. }
  181. /**
  182. This function is used to analyze the Status Register and print out
  183. some debug information and if there is ERR bit set in the Status
  184. Register, the Error Register's value is also be parsed and print out.
  185. @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
  186. @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
  187. @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
  188. **/
  189. VOID
  190. EFIAPI
  191. DumpAllIdeRegisters (
  192. IN EFI_PCI_IO_PROTOCOL *PciIo,
  193. IN EFI_IDE_REGISTERS *IdeRegisters,
  194. IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
  195. )
  196. {
  197. EFI_ATA_STATUS_BLOCK StatusBlock;
  198. ASSERT (PciIo != NULL);
  199. ASSERT (IdeRegisters != NULL);
  200. ZeroMem (&StatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
  201. StatusBlock.AtaStatus = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
  202. StatusBlock.AtaError = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
  203. StatusBlock.AtaSectorCount = IdeReadPortB (PciIo, IdeRegisters->SectorCount);
  204. StatusBlock.AtaSectorCountExp = IdeReadPortB (PciIo, IdeRegisters->SectorCount);
  205. StatusBlock.AtaSectorNumber = IdeReadPortB (PciIo, IdeRegisters->SectorNumber);
  206. StatusBlock.AtaSectorNumberExp = IdeReadPortB (PciIo, IdeRegisters->SectorNumber);
  207. StatusBlock.AtaCylinderLow = IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);
  208. StatusBlock.AtaCylinderLowExp = IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);
  209. StatusBlock.AtaCylinderHigh = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb);
  210. StatusBlock.AtaCylinderHighExp = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb);
  211. StatusBlock.AtaDeviceHead = IdeReadPortB (PciIo, IdeRegisters->Head);
  212. if (AtaStatusBlock != NULL) {
  213. //
  214. // Dump the content of all ATA registers.
  215. //
  216. CopyMem (AtaStatusBlock, &StatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
  217. }
  218. DEBUG_CODE_BEGIN ();
  219. if ((StatusBlock.AtaStatus & ATA_STSREG_DWF) != 0) {
  220. DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Write Fault\n", StatusBlock.AtaStatus));
  221. }
  222. if ((StatusBlock.AtaStatus & ATA_STSREG_CORR) != 0) {
  223. DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Corrected Data\n", StatusBlock.AtaStatus));
  224. }
  225. if ((StatusBlock.AtaStatus & ATA_STSREG_ERR) != 0) {
  226. if ((StatusBlock.AtaError & ATA_ERRREG_BBK) != 0) {
  227. DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Bad Block Detected\n", StatusBlock.AtaError));
  228. }
  229. if ((StatusBlock.AtaError & ATA_ERRREG_UNC) != 0) {
  230. DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Uncorrectable Data\n", StatusBlock.AtaError));
  231. }
  232. if ((StatusBlock.AtaError & ATA_ERRREG_MC) != 0) {
  233. DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Media Change\n", StatusBlock.AtaError));
  234. }
  235. if ((StatusBlock.AtaError & ATA_ERRREG_ABRT) != 0) {
  236. DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Abort\n", StatusBlock.AtaError));
  237. }
  238. if ((StatusBlock.AtaError & ATA_ERRREG_TK0NF) != 0) {
  239. DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Track 0 Not Found\n", StatusBlock.AtaError));
  240. }
  241. if ((StatusBlock.AtaError & ATA_ERRREG_AMNF) != 0) {
  242. DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Address Mark Not Found\n", StatusBlock.AtaError));
  243. }
  244. }
  245. DEBUG_CODE_END ();
  246. }
  247. /**
  248. This function is used to analyze the Status Register at the condition that BSY is zero.
  249. if there is ERR bit set in the Status Register, then return error.
  250. @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
  251. @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
  252. @retval EFI_SUCCESS No err information in the Status Register.
  253. @retval EFI_DEVICE_ERROR Any err information in the Status Register.
  254. **/
  255. EFI_STATUS
  256. EFIAPI
  257. CheckStatusRegister (
  258. IN EFI_PCI_IO_PROTOCOL *PciIo,
  259. IN EFI_IDE_REGISTERS *IdeRegisters
  260. )
  261. {
  262. UINT8 StatusRegister;
  263. ASSERT (PciIo != NULL);
  264. ASSERT (IdeRegisters != NULL);
  265. StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
  266. if ((StatusRegister & ATA_STSREG_BSY) == 0) {
  267. if ((StatusRegister & (ATA_STSREG_ERR | ATA_STSREG_DWF | ATA_STSREG_CORR)) == 0) {
  268. return EFI_SUCCESS;
  269. } else {
  270. return EFI_DEVICE_ERROR;
  271. }
  272. }
  273. return EFI_SUCCESS;
  274. }
  275. /**
  276. This function is used to poll for the DRQ bit clear in the Status
  277. Register. DRQ is cleared when the device is finished transferring data.
  278. So this function is called after data transfer is finished.
  279. @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
  280. @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
  281. @param Timeout The time to complete the command, uses 100ns as a unit.
  282. @retval EFI_SUCCESS DRQ bit clear within the time out.
  283. @retval EFI_TIMEOUT DRQ bit not clear within the time out.
  284. @note
  285. Read Status Register will clear interrupt status.
  286. **/
  287. EFI_STATUS
  288. EFIAPI
  289. DRQClear (
  290. IN EFI_PCI_IO_PROTOCOL *PciIo,
  291. IN EFI_IDE_REGISTERS *IdeRegisters,
  292. IN UINT64 Timeout
  293. )
  294. {
  295. UINT64 Delay;
  296. UINT8 StatusRegister;
  297. BOOLEAN InfiniteWait;
  298. ASSERT (PciIo != NULL);
  299. ASSERT (IdeRegisters != NULL);
  300. if (Timeout == 0) {
  301. InfiniteWait = TRUE;
  302. } else {
  303. InfiniteWait = FALSE;
  304. }
  305. Delay = DivU64x32(Timeout, 1000) + 1;
  306. do {
  307. StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
  308. //
  309. // Wait for BSY == 0, then judge if DRQ is clear
  310. //
  311. if ((StatusRegister & ATA_STSREG_BSY) == 0) {
  312. if ((StatusRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {
  313. return EFI_DEVICE_ERROR;
  314. } else {
  315. return EFI_SUCCESS;
  316. }
  317. }
  318. //
  319. // Stall for 100 microseconds.
  320. //
  321. MicroSecondDelay (100);
  322. Delay--;
  323. } while (InfiniteWait || (Delay > 0));
  324. return EFI_TIMEOUT;
  325. }
  326. /**
  327. This function is used to poll for the DRQ bit clear in the Alternate
  328. Status Register. DRQ is cleared when the device is finished
  329. transferring data. So this function is called after data transfer
  330. is finished.
  331. @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
  332. @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
  333. @param Timeout The time to complete the command, uses 100ns as a unit.
  334. @retval EFI_SUCCESS DRQ bit clear within the time out.
  335. @retval EFI_TIMEOUT DRQ bit not clear within the time out.
  336. @note Read Alternate Status Register will not clear interrupt status.
  337. **/
  338. EFI_STATUS
  339. EFIAPI
  340. DRQClear2 (
  341. IN EFI_PCI_IO_PROTOCOL *PciIo,
  342. IN EFI_IDE_REGISTERS *IdeRegisters,
  343. IN UINT64 Timeout
  344. )
  345. {
  346. UINT64 Delay;
  347. UINT8 AltRegister;
  348. BOOLEAN InfiniteWait;
  349. ASSERT (PciIo != NULL);
  350. ASSERT (IdeRegisters != NULL);
  351. if (Timeout == 0) {
  352. InfiniteWait = TRUE;
  353. } else {
  354. InfiniteWait = FALSE;
  355. }
  356. Delay = DivU64x32(Timeout, 1000) + 1;
  357. do {
  358. AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
  359. //
  360. // Wait for BSY == 0, then judge if DRQ is clear
  361. //
  362. if ((AltRegister & ATA_STSREG_BSY) == 0) {
  363. if ((AltRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {
  364. return EFI_DEVICE_ERROR;
  365. } else {
  366. return EFI_SUCCESS;
  367. }
  368. }
  369. //
  370. // Stall for 100 microseconds.
  371. //
  372. MicroSecondDelay (100);
  373. Delay--;
  374. } while (InfiniteWait || (Delay > 0));
  375. return EFI_TIMEOUT;
  376. }
  377. /**
  378. This function is used to poll for the DRQ bit set in the
  379. Status Register.
  380. DRQ is set when the device is ready to transfer data. So this function
  381. is called after the command is sent to the device and before required
  382. data is transferred.
  383. @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
  384. @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
  385. @param Timeout The time to complete the command, uses 100ns as a unit.
  386. @retval EFI_SUCCESS BSY bit cleared and DRQ bit set within the
  387. timeout.
  388. @retval EFI_TIMEOUT BSY bit not cleared within the timeout.
  389. @retval EFI_ABORTED Polling abandoned due to command abort.
  390. @retval EFI_DEVICE_ERROR Polling abandoned due to a non-abort error.
  391. @retval EFI_NOT_READY BSY bit cleared within timeout, and device
  392. reported "command complete" by clearing DRQ
  393. bit.
  394. @note Read Status Register will clear interrupt status.
  395. **/
  396. EFI_STATUS
  397. EFIAPI
  398. DRQReady (
  399. IN EFI_PCI_IO_PROTOCOL *PciIo,
  400. IN EFI_IDE_REGISTERS *IdeRegisters,
  401. IN UINT64 Timeout
  402. )
  403. {
  404. UINT64 Delay;
  405. UINT8 StatusRegister;
  406. UINT8 ErrorRegister;
  407. BOOLEAN InfiniteWait;
  408. ASSERT (PciIo != NULL);
  409. ASSERT (IdeRegisters != NULL);
  410. if (Timeout == 0) {
  411. InfiniteWait = TRUE;
  412. } else {
  413. InfiniteWait = FALSE;
  414. }
  415. Delay = DivU64x32(Timeout, 1000) + 1;
  416. do {
  417. //
  418. // Read Status Register will clear interrupt
  419. //
  420. StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
  421. //
  422. // Wait for BSY == 0, then judge if DRQ is clear or ERR is set
  423. //
  424. if ((StatusRegister & ATA_STSREG_BSY) == 0) {
  425. if ((StatusRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {
  426. ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
  427. if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
  428. return EFI_ABORTED;
  429. }
  430. return EFI_DEVICE_ERROR;
  431. }
  432. if ((StatusRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {
  433. return EFI_SUCCESS;
  434. } else {
  435. return EFI_NOT_READY;
  436. }
  437. }
  438. //
  439. // Stall for 100 microseconds.
  440. //
  441. MicroSecondDelay (100);
  442. Delay--;
  443. } while (InfiniteWait || (Delay > 0));
  444. return EFI_TIMEOUT;
  445. }
  446. /**
  447. This function is used to poll for the DRQ bit set in the Alternate Status Register.
  448. DRQ is set when the device is ready to transfer data. So this function is called after
  449. the command is sent to the device and before required data is transferred.
  450. @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
  451. @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
  452. @param Timeout The time to complete the command, uses 100ns as a unit.
  453. @retval EFI_SUCCESS BSY bit cleared and DRQ bit set within the
  454. timeout.
  455. @retval EFI_TIMEOUT BSY bit not cleared within the timeout.
  456. @retval EFI_ABORTED Polling abandoned due to command abort.
  457. @retval EFI_DEVICE_ERROR Polling abandoned due to a non-abort error.
  458. @retval EFI_NOT_READY BSY bit cleared within timeout, and device
  459. reported "command complete" by clearing DRQ
  460. bit.
  461. @note Read Alternate Status Register will not clear interrupt status.
  462. **/
  463. EFI_STATUS
  464. EFIAPI
  465. DRQReady2 (
  466. IN EFI_PCI_IO_PROTOCOL *PciIo,
  467. IN EFI_IDE_REGISTERS *IdeRegisters,
  468. IN UINT64 Timeout
  469. )
  470. {
  471. UINT64 Delay;
  472. UINT8 AltRegister;
  473. UINT8 ErrorRegister;
  474. BOOLEAN InfiniteWait;
  475. ASSERT (PciIo != NULL);
  476. ASSERT (IdeRegisters != NULL);
  477. if (Timeout == 0) {
  478. InfiniteWait = TRUE;
  479. } else {
  480. InfiniteWait = FALSE;
  481. }
  482. Delay = DivU64x32(Timeout, 1000) + 1;
  483. do {
  484. //
  485. // Read Alternate Status Register will not clear interrupt status
  486. //
  487. AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
  488. //
  489. // Wait for BSY == 0, then judge if DRQ is clear or ERR is set
  490. //
  491. if ((AltRegister & ATA_STSREG_BSY) == 0) {
  492. if ((AltRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {
  493. ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
  494. if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
  495. return EFI_ABORTED;
  496. }
  497. return EFI_DEVICE_ERROR;
  498. }
  499. if ((AltRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {
  500. return EFI_SUCCESS;
  501. } else {
  502. return EFI_NOT_READY;
  503. }
  504. }
  505. //
  506. // Stall for 100 microseconds.
  507. //
  508. MicroSecondDelay (100);
  509. Delay--;
  510. } while (InfiniteWait || (Delay > 0));
  511. return EFI_TIMEOUT;
  512. }
  513. /**
  514. This function is used to poll for the BSY bit clear in the Status Register. BSY
  515. is clear when the device is not busy. Every command must be sent after device is not busy.
  516. @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
  517. @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
  518. @param Timeout The time to complete the command, uses 100ns as a unit.
  519. @retval EFI_SUCCESS BSY bit clear within the time out.
  520. @retval EFI_TIMEOUT BSY bit not clear within the time out.
  521. @note Read Status Register will clear interrupt status.
  522. **/
  523. EFI_STATUS
  524. EFIAPI
  525. WaitForBSYClear (
  526. IN EFI_PCI_IO_PROTOCOL *PciIo,
  527. IN EFI_IDE_REGISTERS *IdeRegisters,
  528. IN UINT64 Timeout
  529. )
  530. {
  531. UINT64 Delay;
  532. UINT8 StatusRegister;
  533. BOOLEAN InfiniteWait;
  534. ASSERT (PciIo != NULL);
  535. ASSERT (IdeRegisters != NULL);
  536. if (Timeout == 0) {
  537. InfiniteWait = TRUE;
  538. } else {
  539. InfiniteWait = FALSE;
  540. }
  541. Delay = DivU64x32(Timeout, 1000) + 1;
  542. do {
  543. StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
  544. if ((StatusRegister & ATA_STSREG_BSY) == 0x00) {
  545. return EFI_SUCCESS;
  546. }
  547. //
  548. // Stall for 100 microseconds.
  549. //
  550. MicroSecondDelay (100);
  551. Delay--;
  552. } while (InfiniteWait || (Delay > 0));
  553. return EFI_TIMEOUT;
  554. }
  555. /**
  556. Get IDE i/o port registers' base addresses by mode.
  557. In 'Compatibility' mode, use fixed addresses.
  558. In Native-PCI mode, get base addresses from BARs in the PCI IDE controller's
  559. Configuration Space.
  560. The steps to get IDE i/o port registers' base addresses for each channel
  561. as follows:
  562. 1. Examine the Programming Interface byte of the Class Code fields in PCI IDE
  563. controller's Configuration Space to determine the operating mode.
  564. 2. a) In 'Compatibility' mode, use fixed addresses shown in the Table 1 below.
  565. ___________________________________________
  566. | | Command Block | Control Block |
  567. | Channel | Registers | Registers |
  568. |___________|_______________|_______________|
  569. | Primary | 1F0h - 1F7h | 3F6h - 3F7h |
  570. |___________|_______________|_______________|
  571. | Secondary | 170h - 177h | 376h - 377h |
  572. |___________|_______________|_______________|
  573. Table 1. Compatibility resource mappings
  574. b) In Native-PCI mode, IDE registers are mapped into IO space using the BARs
  575. in IDE controller's PCI Configuration Space, shown in the Table 2 below.
  576. ___________________________________________________
  577. | | Command Block | Control Block |
  578. | Channel | Registers | Registers |
  579. |___________|___________________|___________________|
  580. | Primary | BAR at offset 0x10| BAR at offset 0x14|
  581. |___________|___________________|___________________|
  582. | Secondary | BAR at offset 0x18| BAR at offset 0x1C|
  583. |___________|___________________|___________________|
  584. Table 2. BARs for Register Mapping
  585. @param[in] PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance
  586. @param[in, out] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to
  587. store the IDE i/o port registers' base addresses
  588. @retval EFI_UNSUPPORTED Return this value when the BARs is not IO type
  589. @retval EFI_SUCCESS Get the Base address successfully
  590. @retval Other Read the pci configureation data error
  591. **/
  592. EFI_STATUS
  593. EFIAPI
  594. GetIdeRegisterIoAddr (
  595. IN EFI_PCI_IO_PROTOCOL *PciIo,
  596. IN OUT EFI_IDE_REGISTERS *IdeRegisters
  597. )
  598. {
  599. EFI_STATUS Status;
  600. PCI_TYPE00 PciData;
  601. UINT16 CommandBlockBaseAddr;
  602. UINT16 ControlBlockBaseAddr;
  603. UINT16 BusMasterBaseAddr;
  604. if ((PciIo == NULL) || (IdeRegisters == NULL)) {
  605. return EFI_INVALID_PARAMETER;
  606. }
  607. Status = PciIo->Pci.Read (
  608. PciIo,
  609. EfiPciIoWidthUint8,
  610. 0,
  611. sizeof (PciData),
  612. &PciData
  613. );
  614. if (EFI_ERROR (Status)) {
  615. return Status;
  616. }
  617. BusMasterBaseAddr = (UINT16) ((PciData.Device.Bar[4] & 0x0000fff0));
  618. if ((PciData.Hdr.ClassCode[0] & IDE_PRIMARY_OPERATING_MODE) == 0) {
  619. CommandBlockBaseAddr = 0x1f0;
  620. ControlBlockBaseAddr = 0x3f6;
  621. } else {
  622. //
  623. // The BARs should be of IO type
  624. //
  625. if ((PciData.Device.Bar[0] & BIT0) == 0 ||
  626. (PciData.Device.Bar[1] & BIT0) == 0) {
  627. return EFI_UNSUPPORTED;
  628. }
  629. CommandBlockBaseAddr = (UINT16) (PciData.Device.Bar[0] & 0x0000fff8);
  630. ControlBlockBaseAddr = (UINT16) ((PciData.Device.Bar[1] & 0x0000fffc) + 2);
  631. }
  632. //
  633. // Calculate IDE primary channel I/O register base address.
  634. //
  635. IdeRegisters[EfiIdePrimary].Data = CommandBlockBaseAddr;
  636. IdeRegisters[EfiIdePrimary].ErrOrFeature = (UINT16) (CommandBlockBaseAddr + 0x01);
  637. IdeRegisters[EfiIdePrimary].SectorCount = (UINT16) (CommandBlockBaseAddr + 0x02);
  638. IdeRegisters[EfiIdePrimary].SectorNumber = (UINT16) (CommandBlockBaseAddr + 0x03);
  639. IdeRegisters[EfiIdePrimary].CylinderLsb = (UINT16) (CommandBlockBaseAddr + 0x04);
  640. IdeRegisters[EfiIdePrimary].CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x05);
  641. IdeRegisters[EfiIdePrimary].Head = (UINT16) (CommandBlockBaseAddr + 0x06);
  642. IdeRegisters[EfiIdePrimary].CmdOrStatus = (UINT16) (CommandBlockBaseAddr + 0x07);
  643. IdeRegisters[EfiIdePrimary].AltOrDev = ControlBlockBaseAddr;
  644. IdeRegisters[EfiIdePrimary].BusMasterBaseAddr = BusMasterBaseAddr;
  645. if ((PciData.Hdr.ClassCode[0] & IDE_SECONDARY_OPERATING_MODE) == 0) {
  646. CommandBlockBaseAddr = 0x170;
  647. ControlBlockBaseAddr = 0x376;
  648. } else {
  649. //
  650. // The BARs should be of IO type
  651. //
  652. if ((PciData.Device.Bar[2] & BIT0) == 0 ||
  653. (PciData.Device.Bar[3] & BIT0) == 0) {
  654. return EFI_UNSUPPORTED;
  655. }
  656. CommandBlockBaseAddr = (UINT16) (PciData.Device.Bar[2] & 0x0000fff8);
  657. ControlBlockBaseAddr = (UINT16) ((PciData.Device.Bar[3] & 0x0000fffc) + 2);
  658. }
  659. //
  660. // Calculate IDE secondary channel I/O register base address.
  661. //
  662. IdeRegisters[EfiIdeSecondary].Data = CommandBlockBaseAddr;
  663. IdeRegisters[EfiIdeSecondary].ErrOrFeature = (UINT16) (CommandBlockBaseAddr + 0x01);
  664. IdeRegisters[EfiIdeSecondary].SectorCount = (UINT16) (CommandBlockBaseAddr + 0x02);
  665. IdeRegisters[EfiIdeSecondary].SectorNumber = (UINT16) (CommandBlockBaseAddr + 0x03);
  666. IdeRegisters[EfiIdeSecondary].CylinderLsb = (UINT16) (CommandBlockBaseAddr + 0x04);
  667. IdeRegisters[EfiIdeSecondary].CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x05);
  668. IdeRegisters[EfiIdeSecondary].Head = (UINT16) (CommandBlockBaseAddr + 0x06);
  669. IdeRegisters[EfiIdeSecondary].CmdOrStatus = (UINT16) (CommandBlockBaseAddr + 0x07);
  670. IdeRegisters[EfiIdeSecondary].AltOrDev = ControlBlockBaseAddr;
  671. IdeRegisters[EfiIdeSecondary].BusMasterBaseAddr = (UINT16) (BusMasterBaseAddr + 0x8);
  672. return EFI_SUCCESS;
  673. }
  674. /**
  675. Send ATA Ext command into device with NON_DATA protocol.
  676. @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
  677. @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
  678. @param AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data structure.
  679. @param Timeout The time to complete the command, uses 100ns as a unit.
  680. @retval EFI_SUCCESS Reading succeed
  681. @retval EFI_DEVICE_ERROR Error executing commands on this device.
  682. **/
  683. EFI_STATUS
  684. EFIAPI
  685. AtaIssueCommand (
  686. IN EFI_PCI_IO_PROTOCOL *PciIo,
  687. IN EFI_IDE_REGISTERS *IdeRegisters,
  688. IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
  689. IN UINT64 Timeout
  690. )
  691. {
  692. EFI_STATUS Status;
  693. UINT8 DeviceHead;
  694. UINT8 AtaCommand;
  695. ASSERT (PciIo != NULL);
  696. ASSERT (IdeRegisters != NULL);
  697. ASSERT (AtaCommandBlock != NULL);
  698. DeviceHead = AtaCommandBlock->AtaDeviceHead;
  699. AtaCommand = AtaCommandBlock->AtaCommand;
  700. Status = WaitForBSYClear (PciIo, IdeRegisters, Timeout);
  701. if (EFI_ERROR (Status)) {
  702. return EFI_DEVICE_ERROR;
  703. }
  704. //
  705. // Select device (bit4), set LBA mode(bit6) (use 0xe0 for compatibility)
  706. //
  707. IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8) (0xe0 | DeviceHead));
  708. //
  709. // set all the command parameters
  710. // Before write to all the following registers, BSY and DRQ must be 0.
  711. //
  712. Status = DRQClear2 (PciIo, IdeRegisters, Timeout);
  713. if (EFI_ERROR (Status)) {
  714. return EFI_DEVICE_ERROR;
  715. }
  716. //
  717. // Fill the feature register, which is a two-byte FIFO. Need write twice.
  718. //
  719. IdeWritePortB (PciIo, IdeRegisters->ErrOrFeature, AtaCommandBlock->AtaFeaturesExp);
  720. IdeWritePortB (PciIo, IdeRegisters->ErrOrFeature, AtaCommandBlock->AtaFeatures);
  721. //
  722. // Fill the sector count register, which is a two-byte FIFO. Need write twice.
  723. //
  724. IdeWritePortB (PciIo, IdeRegisters->SectorCount, AtaCommandBlock->AtaSectorCountExp);
  725. IdeWritePortB (PciIo, IdeRegisters->SectorCount, AtaCommandBlock->AtaSectorCount);
  726. //
  727. // Fill the start LBA registers, which are also two-byte FIFO
  728. //
  729. IdeWritePortB (PciIo, IdeRegisters->SectorNumber, AtaCommandBlock->AtaSectorNumberExp);
  730. IdeWritePortB (PciIo, IdeRegisters->SectorNumber, AtaCommandBlock->AtaSectorNumber);
  731. IdeWritePortB (PciIo, IdeRegisters->CylinderLsb, AtaCommandBlock->AtaCylinderLowExp);
  732. IdeWritePortB (PciIo, IdeRegisters->CylinderLsb, AtaCommandBlock->AtaCylinderLow);
  733. IdeWritePortB (PciIo, IdeRegisters->CylinderMsb, AtaCommandBlock->AtaCylinderHighExp);
  734. IdeWritePortB (PciIo, IdeRegisters->CylinderMsb, AtaCommandBlock->AtaCylinderHigh);
  735. //
  736. // Send command via Command Register
  737. //
  738. IdeWritePortB (PciIo, IdeRegisters->CmdOrStatus, AtaCommand);
  739. //
  740. // Stall at least 400 microseconds.
  741. //
  742. MicroSecondDelay (400);
  743. return EFI_SUCCESS;
  744. }
  745. /**
  746. This function is used to send out ATA commands conforms to the PIO Data In Protocol.
  747. @param[in] PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data
  748. structure.
  749. @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
  750. @param[in, out] Buffer A pointer to the source buffer for the data.
  751. @param[in] ByteCount The length of the data.
  752. @param[in] Read Flag used to determine the data transfer direction.
  753. Read equals 1, means data transferred from device
  754. to host;Read equals 0, means data transferred
  755. from host to device.
  756. @param[in] AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data structure.
  757. @param[in, out] AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
  758. @param[in] Timeout The time to complete the command, uses 100ns as a unit.
  759. @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
  760. used by non-blocking mode.
  761. @retval EFI_SUCCESS send out the ATA command and device send required data successfully.
  762. @retval EFI_DEVICE_ERROR command sent failed.
  763. **/
  764. EFI_STATUS
  765. EFIAPI
  766. AtaPioDataInOut (
  767. IN EFI_PCI_IO_PROTOCOL *PciIo,
  768. IN EFI_IDE_REGISTERS *IdeRegisters,
  769. IN OUT VOID *Buffer,
  770. IN UINT64 ByteCount,
  771. IN BOOLEAN Read,
  772. IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
  773. IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
  774. IN UINT64 Timeout,
  775. IN ATA_NONBLOCK_TASK *Task
  776. )
  777. {
  778. UINTN WordCount;
  779. UINTN Increment;
  780. UINT16 *Buffer16;
  781. EFI_STATUS Status;
  782. if ((PciIo == NULL) || (IdeRegisters == NULL) || (Buffer == NULL) || (AtaCommandBlock == NULL)) {
  783. return EFI_INVALID_PARAMETER;
  784. }
  785. //
  786. // Issue ATA command
  787. //
  788. Status = AtaIssueCommand (PciIo, IdeRegisters, AtaCommandBlock, Timeout);
  789. if (EFI_ERROR (Status)) {
  790. Status = EFI_DEVICE_ERROR;
  791. goto Exit;
  792. }
  793. Buffer16 = (UINT16 *) Buffer;
  794. //
  795. // According to PIO data in protocol, host can perform a series of reads to
  796. // the data register after each time device set DRQ ready;
  797. // The data size of "a series of read" is command specific.
  798. // For most ATA command, data size received from device will not exceed
  799. // 1 sector, hence the data size for "a series of read" can be the whole data
  800. // size of one command request.
  801. // For ATA command such as Read Sector command, the data size of one ATA
  802. // command request is often larger than 1 sector, according to the
  803. // Read Sector command, the data size of "a series of read" is exactly 1
  804. // sector.
  805. // Here for simplification reason, we specify the data size for
  806. // "a series of read" to 1 sector (256 words) if data size of one ATA command
  807. // request is larger than 256 words.
  808. //
  809. Increment = 256;
  810. //
  811. // used to record bytes of currently transfered data
  812. //
  813. WordCount = 0;
  814. while (WordCount < RShiftU64(ByteCount, 1)) {
  815. //
  816. // Poll DRQ bit set, data transfer can be performed only when DRQ is ready
  817. //
  818. Status = DRQReady2 (PciIo, IdeRegisters, Timeout);
  819. if (EFI_ERROR (Status)) {
  820. Status = EFI_DEVICE_ERROR;
  821. goto Exit;
  822. }
  823. //
  824. // Get the byte count for one series of read
  825. //
  826. if ((WordCount + Increment) > RShiftU64(ByteCount, 1)) {
  827. Increment = (UINTN)(RShiftU64(ByteCount, 1) - WordCount);
  828. }
  829. if (Read) {
  830. IdeReadPortWMultiple (
  831. PciIo,
  832. IdeRegisters->Data,
  833. Increment,
  834. Buffer16
  835. );
  836. } else {
  837. IdeWritePortWMultiple (
  838. PciIo,
  839. IdeRegisters->Data,
  840. Increment,
  841. Buffer16
  842. );
  843. }
  844. Status = CheckStatusRegister (PciIo, IdeRegisters);
  845. if (EFI_ERROR (Status)) {
  846. Status = EFI_DEVICE_ERROR;
  847. goto Exit;
  848. }
  849. WordCount += Increment;
  850. Buffer16 += Increment;
  851. }
  852. Status = DRQClear (PciIo, IdeRegisters, Timeout);
  853. if (EFI_ERROR (Status)) {
  854. Status = EFI_DEVICE_ERROR;
  855. goto Exit;
  856. }
  857. Exit:
  858. //
  859. // Dump All Ide registers to ATA_STATUS_BLOCK
  860. //
  861. DumpAllIdeRegisters (PciIo, IdeRegisters, AtaStatusBlock);
  862. //
  863. // Not support the Non-blocking now,just do the blocking process.
  864. //
  865. return Status;
  866. }
  867. /**
  868. Send ATA command into device with NON_DATA protocol
  869. @param[in] PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE
  870. data structure.
  871. @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
  872. @param[in] AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data
  873. structure.
  874. @param[in, out] AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
  875. @param[in] Timeout The time to complete the command, uses 100ns as a unit.
  876. @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
  877. used by non-blocking mode.
  878. @retval EFI_SUCCESS Reading succeed
  879. @retval EFI_ABORTED Command failed
  880. @retval EFI_DEVICE_ERROR Device status error.
  881. **/
  882. EFI_STATUS
  883. EFIAPI
  884. AtaNonDataCommandIn (
  885. IN EFI_PCI_IO_PROTOCOL *PciIo,
  886. IN EFI_IDE_REGISTERS *IdeRegisters,
  887. IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
  888. IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
  889. IN UINT64 Timeout,
  890. IN ATA_NONBLOCK_TASK *Task
  891. )
  892. {
  893. EFI_STATUS Status;
  894. if ((PciIo == NULL) || (IdeRegisters == NULL) || (AtaCommandBlock == NULL)) {
  895. return EFI_INVALID_PARAMETER;
  896. }
  897. //
  898. // Issue ATA command
  899. //
  900. Status = AtaIssueCommand (PciIo, IdeRegisters, AtaCommandBlock, Timeout);
  901. if (EFI_ERROR (Status)) {
  902. Status = EFI_DEVICE_ERROR;
  903. goto Exit;
  904. }
  905. //
  906. // Wait for command completion
  907. //
  908. Status = WaitForBSYClear (PciIo, IdeRegisters, Timeout);
  909. if (EFI_ERROR (Status)) {
  910. Status = EFI_DEVICE_ERROR;
  911. goto Exit;
  912. }
  913. Status = CheckStatusRegister (PciIo, IdeRegisters);
  914. if (EFI_ERROR (Status)) {
  915. Status = EFI_DEVICE_ERROR;
  916. goto Exit;
  917. }
  918. Exit:
  919. //
  920. // Dump All Ide registers to ATA_STATUS_BLOCK
  921. //
  922. DumpAllIdeRegisters (PciIo, IdeRegisters, AtaStatusBlock);
  923. //
  924. // Not support the Non-blocking now,just do the blocking process.
  925. //
  926. return Status;
  927. }
  928. /**
  929. Wait for memory to be set.
  930. @param[in] PciIo The PCI IO protocol instance.
  931. @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
  932. @param[in] Timeout The time to complete the command, uses 100ns as a unit.
  933. @retval EFI_DEVICE_ERROR The memory is not set.
  934. @retval EFI_TIMEOUT The memory setting is time out.
  935. @retval EFI_SUCCESS The memory is correct set.
  936. **/
  937. EFI_STATUS
  938. AtaUdmStatusWait (
  939. IN EFI_PCI_IO_PROTOCOL *PciIo,
  940. IN EFI_IDE_REGISTERS *IdeRegisters,
  941. IN UINT64 Timeout
  942. )
  943. {
  944. UINT8 RegisterValue;
  945. EFI_STATUS Status;
  946. UINT16 IoPortForBmis;
  947. UINT64 Delay;
  948. BOOLEAN InfiniteWait;
  949. if (Timeout == 0) {
  950. InfiniteWait = TRUE;
  951. } else {
  952. InfiniteWait = FALSE;
  953. }
  954. Delay = DivU64x32 (Timeout, 1000) + 1;
  955. do {
  956. Status = CheckStatusRegister (PciIo, IdeRegisters);
  957. if (EFI_ERROR (Status)) {
  958. Status = EFI_DEVICE_ERROR;
  959. break;
  960. }
  961. IoPortForBmis = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);
  962. RegisterValue = IdeReadPortB (PciIo, IoPortForBmis);
  963. if (((RegisterValue & BMIS_ERROR) != 0) || (Timeout == 0)) {
  964. DEBUG ((EFI_D_ERROR, "ATA UDMA operation fails\n"));
  965. Status = EFI_DEVICE_ERROR;
  966. break;
  967. }
  968. if ((RegisterValue & BMIS_INTERRUPT) != 0) {
  969. Status = EFI_SUCCESS;
  970. break;
  971. }
  972. //
  973. // Stall for 100 microseconds.
  974. //
  975. MicroSecondDelay (100);
  976. Delay--;
  977. } while (InfiniteWait || (Delay > 0));
  978. return Status;
  979. }
  980. /**
  981. Check if the memory to be set.
  982. @param[in] PciIo The PCI IO protocol instance.
  983. @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
  984. used by non-blocking mode.
  985. @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
  986. @retval EFI_DEVICE_ERROR The memory setting met a issue.
  987. @retval EFI_NOT_READY The memory is not set.
  988. @retval EFI_TIMEOUT The memory setting is time out.
  989. @retval EFI_SUCCESS The memory is correct set.
  990. **/
  991. EFI_STATUS
  992. AtaUdmStatusCheck (
  993. IN EFI_PCI_IO_PROTOCOL *PciIo,
  994. IN ATA_NONBLOCK_TASK *Task,
  995. IN EFI_IDE_REGISTERS *IdeRegisters
  996. )
  997. {
  998. UINT8 RegisterValue;
  999. UINT16 IoPortForBmis;
  1000. EFI_STATUS Status;
  1001. Task->RetryTimes--;
  1002. Status = CheckStatusRegister (PciIo, IdeRegisters);
  1003. if (EFI_ERROR (Status)) {
  1004. return EFI_DEVICE_ERROR;
  1005. }
  1006. IoPortForBmis = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);
  1007. RegisterValue = IdeReadPortB (PciIo, IoPortForBmis);
  1008. if ((RegisterValue & BMIS_ERROR) != 0) {
  1009. DEBUG ((EFI_D_ERROR, "ATA UDMA operation fails\n"));
  1010. return EFI_DEVICE_ERROR;
  1011. }
  1012. if ((RegisterValue & BMIS_INTERRUPT) != 0) {
  1013. return EFI_SUCCESS;
  1014. }
  1015. if (!Task->InfiniteWait && (Task->RetryTimes == 0)) {
  1016. return EFI_TIMEOUT;
  1017. } else {
  1018. //
  1019. // The memory is not set.
  1020. //
  1021. return EFI_NOT_READY;
  1022. }
  1023. }
  1024. /**
  1025. Perform an ATA Udma operation (Read, ReadExt, Write, WriteExt).
  1026. @param[in] Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data
  1027. structure.
  1028. @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
  1029. @param[in] Read Flag used to determine the data transfer
  1030. direction. Read equals 1, means data transferred
  1031. from device to host;Read equals 0, means data
  1032. transferred from host to device.
  1033. @param[in] DataBuffer A pointer to the source buffer for the data.
  1034. @param[in] DataLength The length of the data.
  1035. @param[in] AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data structure.
  1036. @param[in, out] AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
  1037. @param[in] Timeout The time to complete the command, uses 100ns as a unit.
  1038. @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
  1039. used by non-blocking mode.
  1040. @retval EFI_SUCCESS the operation is successful.
  1041. @retval EFI_OUT_OF_RESOURCES Build PRD table failed
  1042. @retval EFI_UNSUPPORTED Unknown channel or operations command
  1043. @retval EFI_DEVICE_ERROR Ata command execute failed
  1044. **/
  1045. EFI_STATUS
  1046. EFIAPI
  1047. AtaUdmaInOut (
  1048. IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
  1049. IN EFI_IDE_REGISTERS *IdeRegisters,
  1050. IN BOOLEAN Read,
  1051. IN VOID *DataBuffer,
  1052. IN UINT64 DataLength,
  1053. IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
  1054. IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
  1055. IN UINT64 Timeout,
  1056. IN ATA_NONBLOCK_TASK *Task
  1057. )
  1058. {
  1059. EFI_STATUS Status;
  1060. UINT16 IoPortForBmic;
  1061. UINT16 IoPortForBmis;
  1062. UINT16 IoPortForBmid;
  1063. UINTN PrdTableSize;
  1064. EFI_PHYSICAL_ADDRESS PrdTableMapAddr;
  1065. VOID *PrdTableMap;
  1066. EFI_PHYSICAL_ADDRESS PrdTableBaseAddr;
  1067. EFI_ATA_DMA_PRD *TempPrdBaseAddr;
  1068. UINTN PrdTableNum;
  1069. UINT8 RegisterValue;
  1070. UINTN PageCount;
  1071. UINTN ByteCount;
  1072. UINTN ByteRemaining;
  1073. UINT8 DeviceControl;
  1074. VOID *BufferMap;
  1075. EFI_PHYSICAL_ADDRESS BufferMapAddress;
  1076. EFI_PCI_IO_PROTOCOL_OPERATION PciIoOperation;
  1077. UINT8 DeviceHead;
  1078. EFI_PCI_IO_PROTOCOL *PciIo;
  1079. EFI_TPL OldTpl;
  1080. UINTN AlignmentMask;
  1081. UINTN RealPageCount;
  1082. EFI_PHYSICAL_ADDRESS BaseAddr;
  1083. EFI_PHYSICAL_ADDRESS BaseMapAddr;
  1084. Status = EFI_SUCCESS;
  1085. PrdTableMap = NULL;
  1086. BufferMap = NULL;
  1087. PageCount = 0;
  1088. RealPageCount = 0;
  1089. BaseAddr = 0;
  1090. PciIo = Instance->PciIo;
  1091. if ((PciIo == NULL) || (IdeRegisters == NULL) || (DataBuffer == NULL) || (AtaCommandBlock == NULL)) {
  1092. return EFI_INVALID_PARAMETER;
  1093. }
  1094. //
  1095. // Before starting the Blocking BlockIO operation, push to finish all non-blocking
  1096. // BlockIO tasks.
  1097. // Delay 1ms to simulate the blocking time out checking.
  1098. //
  1099. OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
  1100. while ((Task == NULL) && (!IsListEmpty (&Instance->NonBlockingTaskList))) {
  1101. AsyncNonBlockingTransferRoutine (NULL, Instance);
  1102. //
  1103. // Stall for 1 milliseconds.
  1104. //
  1105. MicroSecondDelay (1000);
  1106. }
  1107. gBS->RestoreTPL (OldTpl);
  1108. //
  1109. // The data buffer should be even alignment
  1110. //
  1111. if (((UINTN)DataBuffer & 0x1) != 0) {
  1112. return EFI_INVALID_PARAMETER;
  1113. }
  1114. //
  1115. // Set relevant IO Port address.
  1116. //
  1117. IoPortForBmic = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIC_OFFSET);
  1118. IoPortForBmis = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);
  1119. IoPortForBmid = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMID_OFFSET);
  1120. //
  1121. // For Blocking mode, start the command.
  1122. // For non-blocking mode, when the command is not started, start it, otherwise
  1123. // go to check the status.
  1124. //
  1125. if (((Task != NULL) && (!Task->IsStart)) || (Task == NULL)) {
  1126. //
  1127. // Calculate the number of PRD entry.
  1128. // Every entry in PRD table can specify a 64K memory region.
  1129. //
  1130. PrdTableNum = (UINTN)(RShiftU64(DataLength, 16) + 1);
  1131. //
  1132. // Make sure that the memory region of PRD table is not cross 64K boundary
  1133. //
  1134. PrdTableSize = PrdTableNum * sizeof (EFI_ATA_DMA_PRD);
  1135. if (PrdTableSize > 0x10000) {
  1136. return EFI_INVALID_PARAMETER;
  1137. }
  1138. //
  1139. // Allocate buffer for PRD table initialization.
  1140. // Note Ide Bus Master spec said the descriptor table must be aligned on a 4 byte
  1141. // boundary and the table cannot cross a 64K boundary in memory.
  1142. //
  1143. PageCount = EFI_SIZE_TO_PAGES (PrdTableSize);
  1144. RealPageCount = PageCount + EFI_SIZE_TO_PAGES (SIZE_64KB);
  1145. //
  1146. // Make sure that PageCount plus EFI_SIZE_TO_PAGES (SIZE_64KB) does not overflow.
  1147. //
  1148. ASSERT (RealPageCount > PageCount);
  1149. Status = PciIo->AllocateBuffer (
  1150. PciIo,
  1151. AllocateAnyPages,
  1152. EfiBootServicesData,
  1153. RealPageCount,
  1154. (VOID **)&BaseAddr,
  1155. 0
  1156. );
  1157. if (EFI_ERROR (Status)) {
  1158. return EFI_OUT_OF_RESOURCES;
  1159. }
  1160. ByteCount = EFI_PAGES_TO_SIZE (RealPageCount);
  1161. Status = PciIo->Map (
  1162. PciIo,
  1163. EfiPciIoOperationBusMasterCommonBuffer,
  1164. (VOID*)(UINTN)BaseAddr,
  1165. &ByteCount,
  1166. &BaseMapAddr,
  1167. &PrdTableMap
  1168. );
  1169. if (EFI_ERROR (Status) || (ByteCount != EFI_PAGES_TO_SIZE (RealPageCount))) {
  1170. //
  1171. // If the data length actually mapped is not equal to the requested amount,
  1172. // it means the DMA operation may be broken into several discontinuous smaller chunks.
  1173. // Can't handle this case.
  1174. //
  1175. PciIo->FreeBuffer (PciIo, RealPageCount, (VOID*)(UINTN)BaseAddr);
  1176. return EFI_OUT_OF_RESOURCES;
  1177. }
  1178. ZeroMem ((VOID *) ((UINTN) BaseAddr), ByteCount);
  1179. //
  1180. // Calculate the 64K align address as PRD Table base address.
  1181. //
  1182. AlignmentMask = SIZE_64KB - 1;
  1183. PrdTableBaseAddr = ((UINTN) BaseAddr + AlignmentMask) & ~AlignmentMask;
  1184. PrdTableMapAddr = ((UINTN) BaseMapAddr + AlignmentMask) & ~AlignmentMask;
  1185. //
  1186. // Map the host address of DataBuffer to DMA master address.
  1187. //
  1188. if (Read) {
  1189. PciIoOperation = EfiPciIoOperationBusMasterWrite;
  1190. } else {
  1191. PciIoOperation = EfiPciIoOperationBusMasterRead;
  1192. }
  1193. ByteCount = (UINTN)DataLength;
  1194. Status = PciIo->Map (
  1195. PciIo,
  1196. PciIoOperation,
  1197. DataBuffer,
  1198. &ByteCount,
  1199. &BufferMapAddress,
  1200. &BufferMap
  1201. );
  1202. if (EFI_ERROR (Status) || (ByteCount != DataLength)) {
  1203. PciIo->Unmap (PciIo, PrdTableMap);
  1204. PciIo->FreeBuffer (PciIo, RealPageCount, (VOID*)(UINTN)BaseAddr);
  1205. return EFI_OUT_OF_RESOURCES;
  1206. }
  1207. //
  1208. // According to Ata spec, it requires the buffer address and size to be even.
  1209. //
  1210. ASSERT ((BufferMapAddress & 0x1) == 0);
  1211. ASSERT ((ByteCount & 0x1) == 0);
  1212. //
  1213. // Fill the PRD table with appropriate bus master address of data buffer and data length.
  1214. //
  1215. ByteRemaining = ByteCount;
  1216. TempPrdBaseAddr = (EFI_ATA_DMA_PRD*)(UINTN)PrdTableBaseAddr;
  1217. while (ByteRemaining != 0) {
  1218. if (ByteRemaining <= 0x10000) {
  1219. TempPrdBaseAddr->RegionBaseAddr = (UINT32) ((UINTN) BufferMapAddress);
  1220. TempPrdBaseAddr->ByteCount = (UINT16) ByteRemaining;
  1221. TempPrdBaseAddr->EndOfTable = 0x8000;
  1222. break;
  1223. }
  1224. TempPrdBaseAddr->RegionBaseAddr = (UINT32) ((UINTN) BufferMapAddress);
  1225. TempPrdBaseAddr->ByteCount = (UINT16) 0x0;
  1226. ByteRemaining -= 0x10000;
  1227. BufferMapAddress += 0x10000;
  1228. TempPrdBaseAddr++;
  1229. }
  1230. //
  1231. // Start to enable the DMA operation
  1232. //
  1233. DeviceHead = AtaCommandBlock->AtaDeviceHead;
  1234. IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)(0xe0 | DeviceHead));
  1235. //
  1236. // Enable interrupt to support UDMA
  1237. //
  1238. DeviceControl = 0;
  1239. IdeWritePortB (PciIo, IdeRegisters->AltOrDev, DeviceControl);
  1240. //
  1241. // Read BMIS register and clear ERROR and INTR bit
  1242. //
  1243. RegisterValue = IdeReadPortB(PciIo, IoPortForBmis);
  1244. RegisterValue |= (BMIS_INTERRUPT | BMIS_ERROR);
  1245. IdeWritePortB (PciIo, IoPortForBmis, RegisterValue);
  1246. //
  1247. // Set the base address to BMID register
  1248. //
  1249. IdeWritePortDW (PciIo, IoPortForBmid, (UINT32)PrdTableMapAddr);
  1250. //
  1251. // Set BMIC register to identify the operation direction
  1252. //
  1253. RegisterValue = IdeReadPortB(PciIo, IoPortForBmic);
  1254. if (Read) {
  1255. RegisterValue |= BMIC_NREAD;
  1256. } else {
  1257. RegisterValue &= ~((UINT8) BMIC_NREAD);
  1258. }
  1259. IdeWritePortB (PciIo, IoPortForBmic, RegisterValue);
  1260. if (Task != NULL) {
  1261. Task->Map = BufferMap;
  1262. Task->TableMap = PrdTableMap;
  1263. Task->MapBaseAddress = (EFI_ATA_DMA_PRD*)(UINTN)BaseAddr;
  1264. Task->PageCount = RealPageCount;
  1265. Task->IsStart = TRUE;
  1266. }
  1267. //
  1268. // Issue ATA command
  1269. //
  1270. Status = AtaIssueCommand (PciIo, IdeRegisters, AtaCommandBlock, Timeout);
  1271. if (EFI_ERROR (Status)) {
  1272. Status = EFI_DEVICE_ERROR;
  1273. goto Exit;
  1274. }
  1275. Status = CheckStatusRegister (PciIo, IdeRegisters);
  1276. if (EFI_ERROR (Status)) {
  1277. Status = EFI_DEVICE_ERROR;
  1278. goto Exit;
  1279. }
  1280. //
  1281. // Set START bit of BMIC register
  1282. //
  1283. RegisterValue = IdeReadPortB(PciIo, IoPortForBmic);
  1284. RegisterValue |= BMIC_START;
  1285. IdeWritePortB(PciIo, IoPortForBmic, RegisterValue);
  1286. }
  1287. //
  1288. // Check the INTERRUPT and ERROR bit of BMIS
  1289. //
  1290. if (Task != NULL) {
  1291. Status = AtaUdmStatusCheck (PciIo, Task, IdeRegisters);
  1292. } else {
  1293. Status = AtaUdmStatusWait (PciIo, IdeRegisters, Timeout);
  1294. }
  1295. //
  1296. // For blocking mode, clear registers and free buffers.
  1297. // For non blocking mode, when the related registers have been set or time
  1298. // out, or a error has been happened, it needs to clear the register and free
  1299. // buffer.
  1300. //
  1301. if ((Task == NULL) || Status != EFI_NOT_READY) {
  1302. //
  1303. // Read BMIS register and clear ERROR and INTR bit
  1304. //
  1305. RegisterValue = IdeReadPortB (PciIo, IoPortForBmis);
  1306. RegisterValue |= (BMIS_INTERRUPT | BMIS_ERROR);
  1307. IdeWritePortB (PciIo, IoPortForBmis, RegisterValue);
  1308. //
  1309. // Read Status Register of IDE device to clear interrupt
  1310. //
  1311. RegisterValue = IdeReadPortB(PciIo, IdeRegisters->CmdOrStatus);
  1312. //
  1313. // Clear START bit of BMIC register
  1314. //
  1315. RegisterValue = IdeReadPortB(PciIo, IoPortForBmic);
  1316. RegisterValue &= ~((UINT8) BMIC_START);
  1317. IdeWritePortB (PciIo, IoPortForBmic, RegisterValue);
  1318. //
  1319. // Disable interrupt of Select device
  1320. //
  1321. DeviceControl = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
  1322. DeviceControl |= ATA_CTLREG_IEN_L;
  1323. IdeWritePortB (PciIo, IdeRegisters->AltOrDev, DeviceControl);
  1324. //
  1325. // Stall for 10 milliseconds.
  1326. //
  1327. MicroSecondDelay (10000);
  1328. }
  1329. Exit:
  1330. //
  1331. // Free all allocated resource
  1332. //
  1333. if ((Task == NULL) || Status != EFI_NOT_READY) {
  1334. if (Task != NULL) {
  1335. PciIo->Unmap (PciIo, Task->TableMap);
  1336. PciIo->FreeBuffer (PciIo, Task->PageCount, Task->MapBaseAddress);
  1337. PciIo->Unmap (PciIo, Task->Map);
  1338. } else {
  1339. PciIo->Unmap (PciIo, PrdTableMap);
  1340. PciIo->FreeBuffer (PciIo, RealPageCount, (VOID*)(UINTN)BaseAddr);
  1341. PciIo->Unmap (PciIo, BufferMap);
  1342. }
  1343. //
  1344. // Dump All Ide registers to ATA_STATUS_BLOCK
  1345. //
  1346. DumpAllIdeRegisters (PciIo, IdeRegisters, AtaStatusBlock);
  1347. }
  1348. return Status;
  1349. }
  1350. /**
  1351. This function reads the pending data in the device.
  1352. @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
  1353. @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
  1354. @retval EFI_SUCCESS Successfully read.
  1355. @retval EFI_NOT_READY The BSY is set avoiding reading.
  1356. **/
  1357. EFI_STATUS
  1358. EFIAPI
  1359. AtaPacketReadPendingData (
  1360. IN EFI_PCI_IO_PROTOCOL *PciIo,
  1361. IN EFI_IDE_REGISTERS *IdeRegisters
  1362. )
  1363. {
  1364. UINT8 AltRegister;
  1365. UINT16 TempWordBuffer;
  1366. AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
  1367. if ((AltRegister & ATA_STSREG_BSY) == ATA_STSREG_BSY) {
  1368. return EFI_NOT_READY;
  1369. }
  1370. if ((AltRegister & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {
  1371. TempWordBuffer = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
  1372. while ((TempWordBuffer & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {
  1373. IdeReadPortWMultiple (
  1374. PciIo,
  1375. IdeRegisters->Data,
  1376. 1,
  1377. &TempWordBuffer
  1378. );
  1379. TempWordBuffer = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
  1380. }
  1381. }
  1382. return EFI_SUCCESS;
  1383. }
  1384. /**
  1385. This function is called by AtaPacketCommandExecute().
  1386. It is used to transfer data between host and device. The data direction is specified
  1387. by the fourth parameter.
  1388. @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
  1389. @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
  1390. @param Buffer Buffer contained data transferred between host and device.
  1391. @param ByteCount Data size in byte unit of the buffer.
  1392. @param Read Flag used to determine the data transfer direction.
  1393. Read equals 1, means data transferred from device to host;
  1394. Read equals 0, means data transferred from host to device.
  1395. @param Timeout Timeout value for wait DRQ ready before each data stream's transfer
  1396. , uses 100ns as a unit.
  1397. @retval EFI_SUCCESS data is transferred successfully.
  1398. @retval EFI_DEVICE_ERROR the device failed to transfer data.
  1399. **/
  1400. EFI_STATUS
  1401. EFIAPI
  1402. AtaPacketReadWrite (
  1403. IN EFI_PCI_IO_PROTOCOL *PciIo,
  1404. IN EFI_IDE_REGISTERS *IdeRegisters,
  1405. IN OUT VOID *Buffer,
  1406. IN OUT UINT32 *ByteCount,
  1407. IN BOOLEAN Read,
  1408. IN UINT64 Timeout
  1409. )
  1410. {
  1411. UINT32 RequiredWordCount;
  1412. UINT32 ActualWordCount;
  1413. UINT32 WordCount;
  1414. EFI_STATUS Status;
  1415. UINT16 *PtrBuffer;
  1416. PtrBuffer = Buffer;
  1417. RequiredWordCount = *ByteCount >> 1;
  1418. //
  1419. // No data transfer is premitted.
  1420. //
  1421. if (RequiredWordCount == 0) {
  1422. return EFI_SUCCESS;
  1423. }
  1424. //
  1425. // ActualWordCount means the word count of data really transferred.
  1426. //
  1427. ActualWordCount = 0;
  1428. while (ActualWordCount < RequiredWordCount) {
  1429. //
  1430. // before each data transfer stream, the host should poll DRQ bit ready,
  1431. // to see whether indicates device is ready to transfer data.
  1432. //
  1433. Status = DRQReady2 (PciIo, IdeRegisters, Timeout);
  1434. if (EFI_ERROR (Status)) {
  1435. if (Status == EFI_NOT_READY) {
  1436. //
  1437. // Device provided less data than we intended to read, or wanted less
  1438. // data than we intended to write, but it may still be successful.
  1439. //
  1440. break;
  1441. } else {
  1442. return Status;
  1443. }
  1444. }
  1445. //
  1446. // get current data transfer size from Cylinder Registers.
  1447. //
  1448. WordCount = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb) << 8;
  1449. WordCount = WordCount | IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);
  1450. WordCount = WordCount & 0xffff;
  1451. WordCount /= 2;
  1452. WordCount = MIN (WordCount, (RequiredWordCount - ActualWordCount));
  1453. if (Read) {
  1454. IdeReadPortWMultiple (
  1455. PciIo,
  1456. IdeRegisters->Data,
  1457. WordCount,
  1458. PtrBuffer
  1459. );
  1460. } else {
  1461. IdeWritePortWMultiple (
  1462. PciIo,
  1463. IdeRegisters->Data,
  1464. WordCount,
  1465. PtrBuffer
  1466. );
  1467. }
  1468. //
  1469. // read status register to check whether error happens.
  1470. //
  1471. Status = CheckStatusRegister (PciIo, IdeRegisters);
  1472. if (EFI_ERROR (Status)) {
  1473. return EFI_DEVICE_ERROR;
  1474. }
  1475. PtrBuffer += WordCount;
  1476. ActualWordCount += WordCount;
  1477. }
  1478. if (Read) {
  1479. //
  1480. // In the case where the drive wants to send more data than we need to read,
  1481. // the DRQ bit will be set and cause delays from DRQClear2().
  1482. // We need to read data from the drive until it clears DRQ so we can move on.
  1483. //
  1484. AtaPacketReadPendingData (PciIo, IdeRegisters);
  1485. }
  1486. //
  1487. // read status register to check whether error happens.
  1488. //
  1489. Status = CheckStatusRegister (PciIo, IdeRegisters);
  1490. if (EFI_ERROR (Status)) {
  1491. return EFI_DEVICE_ERROR;
  1492. }
  1493. //
  1494. // After data transfer is completed, normally, DRQ bit should clear.
  1495. //
  1496. Status = DRQClear (PciIo, IdeRegisters, Timeout);
  1497. if (EFI_ERROR (Status)) {
  1498. return EFI_DEVICE_ERROR;
  1499. }
  1500. *ByteCount = ActualWordCount << 1;
  1501. return Status;
  1502. }
  1503. /**
  1504. This function is used to send out ATAPI commands conforms to the Packet Command
  1505. with PIO Data In Protocol.
  1506. @param[in] PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance
  1507. @param[in] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to
  1508. store the IDE i/o port registers' base addresses
  1509. @param[in] Channel The channel number of device.
  1510. @param[in] Device The device number of device.
  1511. @param[in] Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET data structure.
  1512. @retval EFI_SUCCESS send out the ATAPI packet command successfully
  1513. and device sends data successfully.
  1514. @retval EFI_DEVICE_ERROR the device failed to send data.
  1515. **/
  1516. EFI_STATUS
  1517. EFIAPI
  1518. AtaPacketCommandExecute (
  1519. IN EFI_PCI_IO_PROTOCOL *PciIo,
  1520. IN EFI_IDE_REGISTERS *IdeRegisters,
  1521. IN UINT8 Channel,
  1522. IN UINT8 Device,
  1523. IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet
  1524. )
  1525. {
  1526. EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
  1527. EFI_STATUS Status;
  1528. UINT8 Count;
  1529. UINT8 PacketCommand[12];
  1530. ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
  1531. //
  1532. // Fill ATAPI Command Packet according to CDB.
  1533. // For Atapi cmd, its length should be less than or equal to 12 bytes.
  1534. //
  1535. if (Packet->CdbLength > 12) {
  1536. return EFI_INVALID_PARAMETER;
  1537. }
  1538. ZeroMem (PacketCommand, 12);
  1539. CopyMem (PacketCommand, Packet->Cdb, Packet->CdbLength);
  1540. //
  1541. // No OVL; No DMA
  1542. //
  1543. AtaCommandBlock.AtaFeatures = 0x00;
  1544. //
  1545. // set the transfersize to ATAPI_MAX_BYTE_COUNT to let the device
  1546. // determine how many data should be transferred.
  1547. //
  1548. AtaCommandBlock.AtaCylinderLow = (UINT8) (ATAPI_MAX_BYTE_COUNT & 0x00ff);
  1549. AtaCommandBlock.AtaCylinderHigh = (UINT8) (ATAPI_MAX_BYTE_COUNT >> 8);
  1550. AtaCommandBlock.AtaDeviceHead = (UINT8) (Device << 0x4);
  1551. AtaCommandBlock.AtaCommand = ATA_CMD_PACKET;
  1552. IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)(0xe0 | (Device << 0x4)));
  1553. //
  1554. // Disable interrupt
  1555. //
  1556. IdeWritePortB (PciIo, IdeRegisters->AltOrDev, ATA_DEFAULT_CTL);
  1557. //
  1558. // Issue ATA PACKET command firstly
  1559. //
  1560. Status = AtaIssueCommand (PciIo, IdeRegisters, &AtaCommandBlock, Packet->Timeout);
  1561. if (EFI_ERROR (Status)) {
  1562. return Status;
  1563. }
  1564. Status = DRQReady (PciIo, IdeRegisters, Packet->Timeout);
  1565. if (EFI_ERROR (Status)) {
  1566. return Status;
  1567. }
  1568. //
  1569. // Send out ATAPI command packet
  1570. //
  1571. for (Count = 0; Count < 6; Count++) {
  1572. IdeWritePortW (PciIo, IdeRegisters->Data, *((UINT16*)PacketCommand + Count));
  1573. //
  1574. // Stall for 10 microseconds.
  1575. //
  1576. MicroSecondDelay (10);
  1577. }
  1578. //
  1579. // Read/Write the data of ATAPI Command
  1580. //
  1581. if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_READ) {
  1582. Status = AtaPacketReadWrite (
  1583. PciIo,
  1584. IdeRegisters,
  1585. Packet->InDataBuffer,
  1586. &Packet->InTransferLength,
  1587. TRUE,
  1588. Packet->Timeout
  1589. );
  1590. } else {
  1591. Status = AtaPacketReadWrite (
  1592. PciIo,
  1593. IdeRegisters,
  1594. Packet->OutDataBuffer,
  1595. &Packet->OutTransferLength,
  1596. FALSE,
  1597. Packet->Timeout
  1598. );
  1599. }
  1600. return Status;
  1601. }
  1602. /**
  1603. Set the calculated Best transfer mode to a detected device.
  1604. @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
  1605. @param Channel The channel number of device.
  1606. @param Device The device number of device.
  1607. @param TransferMode A pointer to EFI_ATA_TRANSFER_MODE data structure.
  1608. @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
  1609. @retval EFI_SUCCESS Set transfer mode successfully.
  1610. @retval EFI_DEVICE_ERROR Set transfer mode failed.
  1611. @retval EFI_OUT_OF_RESOURCES Allocate memory failed.
  1612. **/
  1613. EFI_STATUS
  1614. EFIAPI
  1615. SetDeviceTransferMode (
  1616. IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
  1617. IN UINT8 Channel,
  1618. IN UINT8 Device,
  1619. IN EFI_ATA_TRANSFER_MODE *TransferMode,
  1620. IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
  1621. )
  1622. {
  1623. EFI_STATUS Status;
  1624. EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
  1625. ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
  1626. AtaCommandBlock.AtaCommand = ATA_CMD_SET_FEATURES;
  1627. AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);
  1628. AtaCommandBlock.AtaFeatures = 0x03;
  1629. AtaCommandBlock.AtaSectorCount = *((UINT8 *)TransferMode);
  1630. //
  1631. // Send SET FEATURE command (sub command 0x03) to set pio mode.
  1632. //
  1633. Status = AtaNonDataCommandIn (
  1634. Instance->PciIo,
  1635. &Instance->IdeRegisters[Channel],
  1636. &AtaCommandBlock,
  1637. AtaStatusBlock,
  1638. ATA_ATAPI_TIMEOUT,
  1639. NULL
  1640. );
  1641. return Status;
  1642. }
  1643. /**
  1644. Set drive parameters for devices not support PACKETS command.
  1645. @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
  1646. @param Channel The channel number of device.
  1647. @param Device The device number of device.
  1648. @param DriveParameters A pointer to EFI_ATA_DRIVE_PARMS data structure.
  1649. @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
  1650. @retval EFI_SUCCESS Set drive parameter successfully.
  1651. @retval EFI_DEVICE_ERROR Set drive parameter failed.
  1652. @retval EFI_OUT_OF_RESOURCES Allocate memory failed.
  1653. **/
  1654. EFI_STATUS
  1655. EFIAPI
  1656. SetDriveParameters (
  1657. IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
  1658. IN UINT8 Channel,
  1659. IN UINT8 Device,
  1660. IN EFI_ATA_DRIVE_PARMS *DriveParameters,
  1661. IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
  1662. )
  1663. {
  1664. EFI_STATUS Status;
  1665. EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
  1666. ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
  1667. AtaCommandBlock.AtaCommand = ATA_CMD_INIT_DRIVE_PARAM;
  1668. AtaCommandBlock.AtaSectorCount = DriveParameters->Sector;
  1669. AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) + DriveParameters->Heads);
  1670. //
  1671. // Send Init drive parameters
  1672. //
  1673. Status = AtaNonDataCommandIn (
  1674. Instance->PciIo,
  1675. &Instance->IdeRegisters[Channel],
  1676. &AtaCommandBlock,
  1677. AtaStatusBlock,
  1678. ATA_ATAPI_TIMEOUT,
  1679. NULL
  1680. );
  1681. //
  1682. // Send Set Multiple parameters
  1683. //
  1684. AtaCommandBlock.AtaCommand = ATA_CMD_SET_MULTIPLE_MODE;
  1685. AtaCommandBlock.AtaSectorCount = DriveParameters->MultipleSector;
  1686. AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);
  1687. Status = AtaNonDataCommandIn (
  1688. Instance->PciIo,
  1689. &Instance->IdeRegisters[Channel],
  1690. &AtaCommandBlock,
  1691. AtaStatusBlock,
  1692. ATA_ATAPI_TIMEOUT,
  1693. NULL
  1694. );
  1695. return Status;
  1696. }
  1697. /**
  1698. Send SMART Return Status command to check if the execution of SMART cmd is successful or not.
  1699. @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
  1700. @param Channel The channel number of device.
  1701. @param Device The device number of device.
  1702. @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
  1703. @retval EFI_SUCCESS Successfully get the return status of S.M.A.R.T command execution.
  1704. @retval Others Fail to get return status data.
  1705. **/
  1706. EFI_STATUS
  1707. EFIAPI
  1708. IdeAtaSmartReturnStatusCheck (
  1709. IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
  1710. IN UINT8 Channel,
  1711. IN UINT8 Device,
  1712. IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
  1713. )
  1714. {
  1715. EFI_STATUS Status;
  1716. EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
  1717. UINT8 LBAMid;
  1718. UINT8 LBAHigh;
  1719. ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
  1720. AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
  1721. AtaCommandBlock.AtaFeatures = ATA_SMART_RETURN_STATUS;
  1722. AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
  1723. AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
  1724. AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) | 0xe0);
  1725. //
  1726. // Send S.M.A.R.T Read Return Status command to device
  1727. //
  1728. Status = AtaNonDataCommandIn (
  1729. Instance->PciIo,
  1730. &Instance->IdeRegisters[Channel],
  1731. &AtaCommandBlock,
  1732. AtaStatusBlock,
  1733. ATA_ATAPI_TIMEOUT,
  1734. NULL
  1735. );
  1736. if (EFI_ERROR (Status)) {
  1737. REPORT_STATUS_CODE (
  1738. EFI_ERROR_CODE | EFI_ERROR_MINOR,
  1739. (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLED)
  1740. );
  1741. return EFI_DEVICE_ERROR;
  1742. }
  1743. REPORT_STATUS_CODE (
  1744. EFI_PROGRESS_CODE,
  1745. (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_ENABLE)
  1746. );
  1747. LBAMid = IdeReadPortB (Instance->PciIo, Instance->IdeRegisters[Channel].CylinderLsb);
  1748. LBAHigh = IdeReadPortB (Instance->PciIo, Instance->IdeRegisters[Channel].CylinderMsb);
  1749. if ((LBAMid == 0x4f) && (LBAHigh == 0xc2)) {
  1750. //
  1751. // The threshold exceeded condition is not detected by the device
  1752. //
  1753. DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is not detected\n"));
  1754. REPORT_STATUS_CODE (
  1755. EFI_PROGRESS_CODE,
  1756. (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD)
  1757. );
  1758. } else if ((LBAMid == 0xf4) && (LBAHigh == 0x2c)) {
  1759. //
  1760. // The threshold exceeded condition is detected by the device
  1761. //
  1762. DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is detected\n"));
  1763. REPORT_STATUS_CODE (
  1764. EFI_PROGRESS_CODE,
  1765. (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD)
  1766. );
  1767. }
  1768. return EFI_SUCCESS;
  1769. }
  1770. /**
  1771. Enable SMART command of the disk if supported.
  1772. @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
  1773. @param Channel The channel number of device.
  1774. @param Device The device number of device.
  1775. @param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.
  1776. @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
  1777. **/
  1778. VOID
  1779. EFIAPI
  1780. IdeAtaSmartSupport (
  1781. IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
  1782. IN UINT8 Channel,
  1783. IN UINT8 Device,
  1784. IN EFI_IDENTIFY_DATA *IdentifyData,
  1785. IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
  1786. )
  1787. {
  1788. EFI_STATUS Status;
  1789. EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
  1790. //
  1791. // Detect if the device supports S.M.A.R.T.
  1792. //
  1793. if ((IdentifyData->AtaData.command_set_supported_82 & 0x0001) != 0x0001) {
  1794. //
  1795. // S.M.A.R.T is not supported by the device
  1796. //
  1797. DEBUG ((EFI_D_INFO, "S.M.A.R.T feature is not supported at [%a] channel [%a] device!\n",
  1798. (Channel == 1) ? "secondary" : "primary", (Device == 1) ? "slave" : "master"));
  1799. REPORT_STATUS_CODE (
  1800. EFI_ERROR_CODE | EFI_ERROR_MINOR,
  1801. (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_NOTSUPPORTED)
  1802. );
  1803. } else {
  1804. //
  1805. // Check if the feature is enabled. If not, then enable S.M.A.R.T.
  1806. //
  1807. if ((IdentifyData->AtaData.command_set_feature_enb_85 & 0x0001) != 0x0001) {
  1808. REPORT_STATUS_CODE (
  1809. EFI_PROGRESS_CODE,
  1810. (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLE)
  1811. );
  1812. ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
  1813. AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
  1814. AtaCommandBlock.AtaFeatures = ATA_SMART_ENABLE_OPERATION;
  1815. AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
  1816. AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
  1817. AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) | 0xe0);
  1818. //
  1819. // Send S.M.A.R.T Enable command to device
  1820. //
  1821. Status = AtaNonDataCommandIn (
  1822. Instance->PciIo,
  1823. &Instance->IdeRegisters[Channel],
  1824. &AtaCommandBlock,
  1825. AtaStatusBlock,
  1826. ATA_ATAPI_TIMEOUT,
  1827. NULL
  1828. );
  1829. if (!EFI_ERROR (Status)) {
  1830. //
  1831. // Send S.M.A.R.T AutoSave command to device
  1832. //
  1833. ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
  1834. AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
  1835. AtaCommandBlock.AtaFeatures = 0xD2;
  1836. AtaCommandBlock.AtaSectorCount = 0xF1;
  1837. AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
  1838. AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
  1839. AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) | 0xe0);
  1840. Status = AtaNonDataCommandIn (
  1841. Instance->PciIo,
  1842. &Instance->IdeRegisters[Channel],
  1843. &AtaCommandBlock,
  1844. AtaStatusBlock,
  1845. ATA_ATAPI_TIMEOUT,
  1846. NULL
  1847. );
  1848. if (!EFI_ERROR (Status)) {
  1849. Status = IdeAtaSmartReturnStatusCheck (
  1850. Instance,
  1851. Channel,
  1852. Device,
  1853. AtaStatusBlock
  1854. );
  1855. }
  1856. }
  1857. }
  1858. DEBUG ((EFI_D_INFO, "Enabled S.M.A.R.T feature at [%a] channel [%a] device!\n",
  1859. (Channel == 1) ? "secondary" : "primary", (Device == 1) ? "slave" : "master"));
  1860. }
  1861. return ;
  1862. }
  1863. /**
  1864. Sends out an ATA Identify Command to the specified device.
  1865. This function is called by DiscoverIdeDevice() during its device
  1866. identification. It sends out the ATA Identify Command to the
  1867. specified device. Only ATA device responses to this command. If
  1868. the command succeeds, it returns the Identify data structure which
  1869. contains information about the device. This function extracts the
  1870. information it needs to fill the IDE_BLK_IO_DEV data structure,
  1871. including device type, media block size, media capacity, and etc.
  1872. @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
  1873. @param Channel The channel number of device.
  1874. @param Device The device number of device.
  1875. @param Buffer A pointer to data buffer which is used to contain IDENTIFY data.
  1876. @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
  1877. @retval EFI_SUCCESS Identify ATA device successfully.
  1878. @retval EFI_DEVICE_ERROR ATA Identify Device Command failed or device is not ATA device.
  1879. @retval EFI_OUT_OF_RESOURCES Allocate memory failed.
  1880. **/
  1881. EFI_STATUS
  1882. EFIAPI
  1883. AtaIdentify (
  1884. IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
  1885. IN UINT8 Channel,
  1886. IN UINT8 Device,
  1887. IN OUT EFI_IDENTIFY_DATA *Buffer,
  1888. IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
  1889. )
  1890. {
  1891. EFI_STATUS Status;
  1892. EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
  1893. ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
  1894. AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DRIVE;
  1895. AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);
  1896. Status = AtaPioDataInOut (
  1897. Instance->PciIo,
  1898. &Instance->IdeRegisters[Channel],
  1899. Buffer,
  1900. sizeof (EFI_IDENTIFY_DATA),
  1901. TRUE,
  1902. &AtaCommandBlock,
  1903. AtaStatusBlock,
  1904. ATA_ATAPI_TIMEOUT,
  1905. NULL
  1906. );
  1907. return Status;
  1908. }
  1909. /**
  1910. This function is called by DiscoverIdeDevice() during its device
  1911. identification.
  1912. Its main purpose is to get enough information for the device media
  1913. to fill in the Media data structure of the Block I/O Protocol interface.
  1914. There are 5 steps to reach such objective:
  1915. 1. Sends out the ATAPI Identify Command to the specified device.
  1916. Only ATAPI device responses to this command. If the command succeeds,
  1917. it returns the Identify data structure which filled with information
  1918. about the device. Since the ATAPI device contains removable media,
  1919. the only meaningful information is the device module name.
  1920. 2. Sends out ATAPI Inquiry Packet Command to the specified device.
  1921. This command will return inquiry data of the device, which contains
  1922. the device type information.
  1923. 3. Allocate sense data space for future use. We don't detect the media
  1924. presence here to improvement boot performance, especially when CD
  1925. media is present. The media detection will be performed just before
  1926. each BLK_IO read/write
  1927. @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
  1928. @param Channel The channel number of device.
  1929. @param Device The device number of device.
  1930. @param Buffer A pointer to data buffer which is used to contain IDENTIFY data.
  1931. @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
  1932. @retval EFI_SUCCESS Identify ATAPI device successfully.
  1933. @retval EFI_DEVICE_ERROR ATA Identify Packet Device Command failed or device type
  1934. is not supported by this IDE driver.
  1935. @retval EFI_OUT_OF_RESOURCES Allocate memory failed.
  1936. **/
  1937. EFI_STATUS
  1938. EFIAPI
  1939. AtaIdentifyPacket (
  1940. IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
  1941. IN UINT8 Channel,
  1942. IN UINT8 Device,
  1943. IN OUT EFI_IDENTIFY_DATA *Buffer,
  1944. IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
  1945. )
  1946. {
  1947. EFI_STATUS Status;
  1948. EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
  1949. ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
  1950. AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DEVICE;
  1951. AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);
  1952. //
  1953. // Send ATAPI Identify Command to get IDENTIFY data.
  1954. //
  1955. Status = AtaPioDataInOut (
  1956. Instance->PciIo,
  1957. &Instance->IdeRegisters[Channel],
  1958. (VOID *) Buffer,
  1959. sizeof (EFI_IDENTIFY_DATA),
  1960. TRUE,
  1961. &AtaCommandBlock,
  1962. AtaStatusBlock,
  1963. ATA_ATAPI_TIMEOUT,
  1964. NULL
  1965. );
  1966. return Status;
  1967. }
  1968. /**
  1969. This function is used for detect whether the IDE device exists in the
  1970. specified Channel as the specified Device Number.
  1971. There is two IDE channels: one is Primary Channel, the other is
  1972. Secondary Channel.(Channel is the logical name for the physical "Cable".)
  1973. Different channel has different register group.
  1974. On each IDE channel, at most two IDE devices attach,
  1975. one is called Device 0 (Master device), the other is called Device 1
  1976. (Slave device). The devices on the same channel co-use the same register
  1977. group, so before sending out a command for a specified device via command
  1978. register, it is a must to select the current device to accept the command
  1979. by set the device number in the Head/Device Register.
  1980. @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
  1981. @param IdeChannel The channel number of device.
  1982. @retval EFI_SUCCESS successfully detects device.
  1983. @retval other any failure during detection process will return this value.
  1984. **/
  1985. EFI_STATUS
  1986. EFIAPI
  1987. DetectAndConfigIdeDevice (
  1988. IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
  1989. IN UINT8 IdeChannel
  1990. )
  1991. {
  1992. EFI_STATUS Status;
  1993. UINT8 SectorCountReg;
  1994. UINT8 LBALowReg;
  1995. UINT8 LBAMidReg;
  1996. UINT8 LBAHighReg;
  1997. EFI_ATA_DEVICE_TYPE DeviceType;
  1998. UINT8 IdeDevice;
  1999. EFI_IDE_REGISTERS *IdeRegisters;
  2000. EFI_IDENTIFY_DATA Buffer;
  2001. EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;
  2002. EFI_PCI_IO_PROTOCOL *PciIo;
  2003. EFI_ATA_COLLECTIVE_MODE *SupportedModes;
  2004. EFI_ATA_TRANSFER_MODE TransferMode;
  2005. EFI_ATA_DRIVE_PARMS DriveParameters;
  2006. IdeRegisters = &Instance->IdeRegisters[IdeChannel];
  2007. IdeInit = Instance->IdeControllerInit;
  2008. PciIo = Instance->PciIo;
  2009. for (IdeDevice = 0; IdeDevice < EfiIdeMaxDevice; IdeDevice++) {
  2010. //
  2011. // Select Master or Slave device to get the return signature for ATA DEVICE DIAGNOSTIC cmd.
  2012. //
  2013. IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)((IdeDevice << 4) | 0xe0));
  2014. //
  2015. // Send ATA Device Execut Diagnostic command.
  2016. // This command should work no matter DRDY is ready or not
  2017. //
  2018. IdeWritePortB (PciIo, IdeRegisters->CmdOrStatus, ATA_CMD_EXEC_DRIVE_DIAG);
  2019. Status = WaitForBSYClear (PciIo, IdeRegisters, 350000000);
  2020. if (EFI_ERROR (Status)) {
  2021. DEBUG((EFI_D_ERROR, "New detecting method: Send Execute Diagnostic Command: WaitForBSYClear: Status: %d\n", Status));
  2022. continue;
  2023. }
  2024. //
  2025. // Select Master or Slave device to get the return signature for ATA DEVICE DIAGNOSTIC cmd.
  2026. //
  2027. IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)((IdeDevice << 4) | 0xe0));
  2028. //
  2029. // Stall for 1 milliseconds.
  2030. //
  2031. MicroSecondDelay (1000);
  2032. SectorCountReg = IdeReadPortB (PciIo, IdeRegisters->SectorCount);
  2033. LBALowReg = IdeReadPortB (PciIo, IdeRegisters->SectorNumber);
  2034. LBAMidReg = IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);
  2035. LBAHighReg = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb);
  2036. //
  2037. // Refer to ATA/ATAPI 4 Spec, section 9.1
  2038. //
  2039. if ((SectorCountReg == 0x1) && (LBALowReg == 0x1) && (LBAMidReg == 0x0) && (LBAHighReg == 0x0)) {
  2040. DeviceType = EfiIdeHarddisk;
  2041. } else if ((LBAMidReg == 0x14) && (LBAHighReg == 0xeb)) {
  2042. DeviceType = EfiIdeCdrom;
  2043. } else {
  2044. continue;
  2045. }
  2046. //
  2047. // Send IDENTIFY cmd to the device to test if it is really attached.
  2048. //
  2049. if (DeviceType == EfiIdeHarddisk) {
  2050. Status = AtaIdentify (Instance, IdeChannel, IdeDevice, &Buffer, NULL);
  2051. //
  2052. // if identifying ata device is failure, then try to send identify packet cmd.
  2053. //
  2054. if (EFI_ERROR (Status)) {
  2055. REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED));
  2056. DeviceType = EfiIdeCdrom;
  2057. Status = AtaIdentifyPacket (Instance, IdeChannel, IdeDevice, &Buffer, NULL);
  2058. }
  2059. } else {
  2060. Status = AtaIdentifyPacket (Instance, IdeChannel, IdeDevice, &Buffer, NULL);
  2061. //
  2062. // if identifying atapi device is failure, then try to send identify cmd.
  2063. //
  2064. if (EFI_ERROR (Status)) {
  2065. DeviceType = EfiIdeHarddisk;
  2066. Status = AtaIdentify (Instance, IdeChannel, IdeDevice, &Buffer, NULL);
  2067. }
  2068. }
  2069. if (EFI_ERROR (Status)) {
  2070. //
  2071. // No device is found at this port
  2072. //
  2073. continue;
  2074. }
  2075. DEBUG ((EFI_D_INFO, "[%a] channel [%a] [%a] device\n",
  2076. (IdeChannel == 1) ? "secondary" : "primary ", (IdeDevice == 1) ? "slave " : "master",
  2077. DeviceType == EfiIdeCdrom ? "cdrom " : "harddisk"));
  2078. //
  2079. // If the device is a hard disk, then try to enable S.M.A.R.T feature
  2080. //
  2081. if ((DeviceType == EfiIdeHarddisk) && PcdGetBool (PcdAtaSmartEnable)) {
  2082. IdeAtaSmartSupport (
  2083. Instance,
  2084. IdeChannel,
  2085. IdeDevice,
  2086. &Buffer,
  2087. NULL
  2088. );
  2089. }
  2090. //
  2091. // Submit identify data to IDE controller init driver
  2092. //
  2093. IdeInit->SubmitData (IdeInit, IdeChannel, IdeDevice, &Buffer);
  2094. //
  2095. // Now start to config ide device parameter and transfer mode.
  2096. //
  2097. Status = IdeInit->CalculateMode (
  2098. IdeInit,
  2099. IdeChannel,
  2100. IdeDevice,
  2101. &SupportedModes
  2102. );
  2103. if (EFI_ERROR (Status)) {
  2104. DEBUG ((EFI_D_ERROR, "Calculate Mode Fail, Status = %r\n", Status));
  2105. continue;
  2106. }
  2107. //
  2108. // Set best supported PIO mode on this IDE device
  2109. //
  2110. if (SupportedModes->PioMode.Mode <= EfiAtaPioMode2) {
  2111. TransferMode.ModeCategory = EFI_ATA_MODE_DEFAULT_PIO;
  2112. } else {
  2113. TransferMode.ModeCategory = EFI_ATA_MODE_FLOW_PIO;
  2114. }
  2115. TransferMode.ModeNumber = (UINT8) (SupportedModes->PioMode.Mode);
  2116. if (SupportedModes->ExtModeCount == 0){
  2117. Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);
  2118. if (EFI_ERROR (Status)) {
  2119. DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));
  2120. continue;
  2121. }
  2122. }
  2123. //
  2124. // Set supported DMA mode on this IDE device. Note that UDMA & MDMA cann't
  2125. // be set together. Only one DMA mode can be set to a device. If setting
  2126. // DMA mode operation fails, we can continue moving on because we only use
  2127. // PIO mode at boot time. DMA modes are used by certain kind of OS booting
  2128. //
  2129. if (SupportedModes->UdmaMode.Valid) {
  2130. TransferMode.ModeCategory = EFI_ATA_MODE_UDMA;
  2131. TransferMode.ModeNumber = (UINT8) (SupportedModes->UdmaMode.Mode);
  2132. Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);
  2133. if (EFI_ERROR (Status)) {
  2134. DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));
  2135. continue;
  2136. }
  2137. } else if (SupportedModes->MultiWordDmaMode.Valid) {
  2138. TransferMode.ModeCategory = EFI_ATA_MODE_MDMA;
  2139. TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode;
  2140. Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);
  2141. if (EFI_ERROR (Status)) {
  2142. DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));
  2143. continue;
  2144. }
  2145. }
  2146. //
  2147. // Set Parameters for the device:
  2148. // 1) Init
  2149. // 2) Establish the block count for READ/WRITE MULTIPLE (EXT) command
  2150. //
  2151. if (DeviceType == EfiIdeHarddisk) {
  2152. //
  2153. // Init driver parameters
  2154. //
  2155. DriveParameters.Sector = (UINT8) ((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->sectors_per_track;
  2156. DriveParameters.Heads = (UINT8) (((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->heads - 1);
  2157. DriveParameters.MultipleSector = (UINT8) ((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->multi_sector_cmd_max_sct_cnt;
  2158. Status = SetDriveParameters (Instance, IdeChannel, IdeDevice, &DriveParameters, NULL);
  2159. }
  2160. //
  2161. // Set IDE controller Timing Blocks in the PCI Configuration Space
  2162. //
  2163. IdeInit->SetTiming (IdeInit, IdeChannel, IdeDevice, SupportedModes);
  2164. //
  2165. // IDE controller and IDE device timing is configured successfully.
  2166. // Now insert the device into device list.
  2167. //
  2168. Status = CreateNewDeviceInfo (Instance, IdeChannel, IdeDevice, DeviceType, &Buffer);
  2169. if (EFI_ERROR (Status)) {
  2170. continue;
  2171. }
  2172. if (DeviceType == EfiIdeHarddisk) {
  2173. REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_PC_ENABLE));
  2174. }
  2175. }
  2176. return EFI_SUCCESS;
  2177. }
  2178. /**
  2179. Initialize ATA host controller at IDE mode.
  2180. The function is designed to initialize ATA host controller.
  2181. @param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.
  2182. **/
  2183. EFI_STATUS
  2184. EFIAPI
  2185. IdeModeInitialization (
  2186. IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance
  2187. )
  2188. {
  2189. EFI_STATUS Status;
  2190. EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;
  2191. EFI_PCI_IO_PROTOCOL *PciIo;
  2192. UINT8 Channel;
  2193. UINT8 IdeChannel;
  2194. BOOLEAN ChannelEnabled;
  2195. UINT8 MaxDevices;
  2196. IdeInit = Instance->IdeControllerInit;
  2197. PciIo = Instance->PciIo;
  2198. Channel = IdeInit->ChannelCount;
  2199. //
  2200. // Obtain IDE IO port registers' base addresses
  2201. //
  2202. Status = GetIdeRegisterIoAddr (PciIo, Instance->IdeRegisters);
  2203. if (EFI_ERROR (Status)) {
  2204. goto ErrorExit;
  2205. }
  2206. for (IdeChannel = 0; IdeChannel < Channel; IdeChannel++) {
  2207. IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelEnumeration, IdeChannel);
  2208. //
  2209. // now obtain channel information fron IdeControllerInit protocol.
  2210. //
  2211. Status = IdeInit->GetChannelInfo (
  2212. IdeInit,
  2213. IdeChannel,
  2214. &ChannelEnabled,
  2215. &MaxDevices
  2216. );
  2217. if (EFI_ERROR (Status)) {
  2218. DEBUG ((EFI_D_ERROR, "[GetChannel, Status=%x]", Status));
  2219. continue;
  2220. }
  2221. if (!ChannelEnabled) {
  2222. continue;
  2223. }
  2224. ASSERT (MaxDevices <= 2);
  2225. //
  2226. // Now inform the IDE Controller Init Module.
  2227. //
  2228. IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelReset, IdeChannel);
  2229. //
  2230. // No reset channel function implemented.
  2231. //
  2232. IdeInit->NotifyPhase (IdeInit, EfiIdeAfterChannelReset, IdeChannel);
  2233. //
  2234. // Now inform the IDE Controller Init Module.
  2235. //
  2236. IdeInit->NotifyPhase (IdeInit, EfiIdeBusBeforeDevicePresenceDetection, IdeChannel);
  2237. //
  2238. // Detect all attached ATA devices and set the transfer mode for each device.
  2239. //
  2240. DetectAndConfigIdeDevice (Instance, IdeChannel);
  2241. }
  2242. //
  2243. // All configurations done! Notify IdeController to do post initialization
  2244. // work such as saving IDE controller PCI settings for S3 resume
  2245. //
  2246. IdeInit->NotifyPhase (IdeInit, EfiIdeBusPhaseMaximum, 0);
  2247. ErrorExit:
  2248. return Status;
  2249. }