AhciMode.h 15 KB

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  1. /** @file
  2. Header file for AHCI mode of ATA host controller.
  3. Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef __ATA_HC_AHCI_MODE_H__
  7. #define __ATA_HC_AHCI_MODE_H__
  8. #define EFI_AHCI_BAR_INDEX 0x05
  9. #define EFI_AHCI_CAPABILITY_OFFSET 0x0000
  10. #define EFI_AHCI_CAP_SAM BIT18
  11. #define EFI_AHCI_CAP_SSS BIT27
  12. #define EFI_AHCI_CAP_S64A BIT31
  13. #define EFI_AHCI_GHC_OFFSET 0x0004
  14. #define EFI_AHCI_GHC_RESET BIT0
  15. #define EFI_AHCI_GHC_IE BIT1
  16. #define EFI_AHCI_GHC_ENABLE BIT31
  17. #define EFI_AHCI_IS_OFFSET 0x0008
  18. #define EFI_AHCI_PI_OFFSET 0x000C
  19. #define EFI_AHCI_MAX_PORTS 32
  20. #define AHCI_CAPABILITY2_OFFSET 0x0024
  21. #define AHCI_CAP2_SDS BIT3
  22. #define AHCI_CAP2_SADM BIT4
  23. typedef struct {
  24. UINT32 Lower32;
  25. UINT32 Upper32;
  26. } DATA_32;
  27. typedef union {
  28. DATA_32 Uint32;
  29. UINT64 Uint64;
  30. } DATA_64;
  31. //
  32. // Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.
  33. // Add a bit of margin for robustness.
  34. //
  35. #define EFI_AHCI_BUS_PHY_DETECT_TIMEOUT 15
  36. //
  37. // Refer SATA1.0a spec, the FIS enable time should be less than 500ms.
  38. //
  39. #define EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT EFI_TIMER_PERIOD_MILLISECONDS(500)
  40. //
  41. // Refer SATA1.0a spec, the bus reset time should be less than 1s.
  42. //
  43. #define EFI_AHCI_BUS_RESET_TIMEOUT EFI_TIMER_PERIOD_SECONDS(1)
  44. #define EFI_AHCI_ATAPI_DEVICE_SIG 0xEB140000
  45. #define EFI_AHCI_ATA_DEVICE_SIG 0x00000000
  46. #define EFI_AHCI_PORT_MULTIPLIER_SIG 0x96690000
  47. #define EFI_AHCI_ATAPI_SIG_MASK 0xFFFF0000
  48. //
  49. // Each PRDT entry can point to a memory block up to 4M byte
  50. //
  51. #define EFI_AHCI_MAX_DATA_PER_PRDT 0x400000
  52. #define EFI_AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device
  53. #define EFI_AHCI_FIS_REGISTER_H2D_LENGTH 20
  54. #define EFI_AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host
  55. #define EFI_AHCI_FIS_REGISTER_D2H_LENGTH 20
  56. #define EFI_AHCI_FIS_DMA_ACTIVATE 0x39 //DMA Activate FIS - Device to Host
  57. #define EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH 4
  58. #define EFI_AHCI_FIS_DMA_SETUP 0x41 //DMA Setup FIS - Bi-directional
  59. #define EFI_AHCI_FIS_DMA_SETUP_LENGTH 28
  60. #define EFI_AHCI_FIS_DATA 0x46 //Data FIS - Bi-directional
  61. #define EFI_AHCI_FIS_BIST 0x58 //BIST Activate FIS - Bi-directional
  62. #define EFI_AHCI_FIS_BIST_LENGTH 12
  63. #define EFI_AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host
  64. #define EFI_AHCI_FIS_PIO_SETUP_LENGTH 20
  65. #define EFI_AHCI_FIS_SET_DEVICE 0xA1 //Set Device Bits FIS - Device to Host
  66. #define EFI_AHCI_FIS_SET_DEVICE_LENGTH 8
  67. #define EFI_AHCI_D2H_FIS_OFFSET 0x40
  68. #define EFI_AHCI_DMA_FIS_OFFSET 0x00
  69. #define EFI_AHCI_PIO_FIS_OFFSET 0x20
  70. #define EFI_AHCI_SDB_FIS_OFFSET 0x58
  71. #define EFI_AHCI_FIS_TYPE_MASK 0xFF
  72. #define EFI_AHCI_U_FIS_OFFSET 0x60
  73. //
  74. // Port register
  75. //
  76. #define EFI_AHCI_PORT_START 0x0100
  77. #define EFI_AHCI_PORT_REG_WIDTH 0x0080
  78. #define EFI_AHCI_PORT_CLB 0x0000
  79. #define EFI_AHCI_PORT_CLBU 0x0004
  80. #define EFI_AHCI_PORT_FB 0x0008
  81. #define EFI_AHCI_PORT_FBU 0x000C
  82. #define EFI_AHCI_PORT_IS 0x0010
  83. #define EFI_AHCI_PORT_IS_DHRS BIT0
  84. #define EFI_AHCI_PORT_IS_PSS BIT1
  85. #define EFI_AHCI_PORT_IS_SSS BIT2
  86. #define EFI_AHCI_PORT_IS_SDBS BIT3
  87. #define EFI_AHCI_PORT_IS_UFS BIT4
  88. #define EFI_AHCI_PORT_IS_DPS BIT5
  89. #define EFI_AHCI_PORT_IS_PCS BIT6
  90. #define EFI_AHCI_PORT_IS_DIS BIT7
  91. #define EFI_AHCI_PORT_IS_PRCS BIT22
  92. #define EFI_AHCI_PORT_IS_IPMS BIT23
  93. #define EFI_AHCI_PORT_IS_OFS BIT24
  94. #define EFI_AHCI_PORT_IS_INFS BIT26
  95. #define EFI_AHCI_PORT_IS_IFS BIT27
  96. #define EFI_AHCI_PORT_IS_HBDS BIT28
  97. #define EFI_AHCI_PORT_IS_HBFS BIT29
  98. #define EFI_AHCI_PORT_IS_TFES BIT30
  99. #define EFI_AHCI_PORT_IS_CPDS BIT31
  100. #define EFI_AHCI_PORT_IS_CLEAR 0xFFFFFFFF
  101. #define EFI_AHCI_PORT_IS_FIS_CLEAR 0x0000000F
  102. #define EFI_AHCI_PORT_IE 0x0014
  103. #define EFI_AHCI_PORT_CMD 0x0018
  104. #define EFI_AHCI_PORT_CMD_ST_MASK 0xFFFFFFFE
  105. #define EFI_AHCI_PORT_CMD_ST BIT0
  106. #define EFI_AHCI_PORT_CMD_SUD BIT1
  107. #define EFI_AHCI_PORT_CMD_POD BIT2
  108. #define EFI_AHCI_PORT_CMD_CLO BIT3
  109. #define EFI_AHCI_PORT_CMD_CR BIT15
  110. #define EFI_AHCI_PORT_CMD_FRE BIT4
  111. #define EFI_AHCI_PORT_CMD_FR BIT14
  112. #define EFI_AHCI_PORT_CMD_MASK ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)
  113. #define EFI_AHCI_PORT_CMD_PMA BIT17
  114. #define EFI_AHCI_PORT_CMD_HPCP BIT18
  115. #define EFI_AHCI_PORT_CMD_MPSP BIT19
  116. #define EFI_AHCI_PORT_CMD_CPD BIT20
  117. #define EFI_AHCI_PORT_CMD_ESP BIT21
  118. #define EFI_AHCI_PORT_CMD_ATAPI BIT24
  119. #define EFI_AHCI_PORT_CMD_DLAE BIT25
  120. #define EFI_AHCI_PORT_CMD_ALPE BIT26
  121. #define EFI_AHCI_PORT_CMD_ASP BIT27
  122. #define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
  123. #define EFI_AHCI_PORT_CMD_ACTIVE (1 << 28 )
  124. #define EFI_AHCI_PORT_TFD 0x0020
  125. #define EFI_AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0)
  126. #define EFI_AHCI_PORT_TFD_BSY BIT7
  127. #define EFI_AHCI_PORT_TFD_DRQ BIT3
  128. #define EFI_AHCI_PORT_TFD_ERR BIT0
  129. #define EFI_AHCI_PORT_TFD_ERR_MASK 0x00FF00
  130. #define EFI_AHCI_PORT_SIG 0x0024
  131. #define EFI_AHCI_PORT_SSTS 0x0028
  132. #define EFI_AHCI_PORT_SSTS_DET_MASK 0x000F
  133. #define EFI_AHCI_PORT_SSTS_DET 0x0001
  134. #define EFI_AHCI_PORT_SSTS_DET_PCE 0x0003
  135. #define EFI_AHCI_PORT_SSTS_SPD_MASK 0x00F0
  136. #define EFI_AHCI_PORT_SCTL 0x002C
  137. #define EFI_AHCI_PORT_SCTL_DET_MASK 0x000F
  138. #define EFI_AHCI_PORT_SCTL_MASK (~EFI_AHCI_PORT_SCTL_DET_MASK)
  139. #define EFI_AHCI_PORT_SCTL_DET_INIT 0x0001
  140. #define EFI_AHCI_PORT_SCTL_DET_PHYCOMM 0x0003
  141. #define EFI_AHCI_PORT_SCTL_SPD_MASK 0x00F0
  142. #define EFI_AHCI_PORT_SCTL_IPM_MASK 0x0F00
  143. #define EFI_AHCI_PORT_SCTL_IPM_INIT 0x0300
  144. #define EFI_AHCI_PORT_SCTL_IPM_PSD 0x0100
  145. #define EFI_AHCI_PORT_SCTL_IPM_SSD 0x0200
  146. #define EFI_AHCI_PORT_SERR 0x0030
  147. #define EFI_AHCI_PORT_SERR_RDIE BIT0
  148. #define EFI_AHCI_PORT_SERR_RCE BIT1
  149. #define EFI_AHCI_PORT_SERR_TDIE BIT8
  150. #define EFI_AHCI_PORT_SERR_PCDIE BIT9
  151. #define EFI_AHCI_PORT_SERR_PE BIT10
  152. #define EFI_AHCI_PORT_SERR_IE BIT11
  153. #define EFI_AHCI_PORT_SERR_PRC BIT16
  154. #define EFI_AHCI_PORT_SERR_PIE BIT17
  155. #define EFI_AHCI_PORT_SERR_CW BIT18
  156. #define EFI_AHCI_PORT_SERR_BDE BIT19
  157. #define EFI_AHCI_PORT_SERR_DE BIT20
  158. #define EFI_AHCI_PORT_SERR_CRCE BIT21
  159. #define EFI_AHCI_PORT_SERR_HE BIT22
  160. #define EFI_AHCI_PORT_SERR_LSE BIT23
  161. #define EFI_AHCI_PORT_SERR_TSTE BIT24
  162. #define EFI_AHCI_PORT_SERR_UFT BIT25
  163. #define EFI_AHCI_PORT_SERR_EX BIT26
  164. #define EFI_AHCI_PORT_ERR_CLEAR 0xFFFFFFFF
  165. #define EFI_AHCI_PORT_SACT 0x0034
  166. #define EFI_AHCI_PORT_CI 0x0038
  167. #define EFI_AHCI_PORT_SNTF 0x003C
  168. #define AHCI_PORT_DEVSLP 0x0044
  169. #define AHCI_PORT_DEVSLP_ADSE BIT0
  170. #define AHCI_PORT_DEVSLP_DSP BIT1
  171. #define AHCI_PORT_DEVSLP_DETO_MASK 0x000003FC
  172. #define AHCI_PORT_DEVSLP_MDAT_MASK 0x00007C00
  173. #define AHCI_PORT_DEVSLP_DITO_MASK 0x01FF8000
  174. #define AHCI_PORT_DEVSLP_DM_MASK 0x1E000000
  175. #pragma pack(1)
  176. //
  177. // Command List structure includes total 32 entries.
  178. // The entry data structure is listed at the following.
  179. //
  180. typedef struct {
  181. UINT32 AhciCmdCfl:5; //Command FIS Length
  182. UINT32 AhciCmdA:1; //ATAPI
  183. UINT32 AhciCmdW:1; //Write
  184. UINT32 AhciCmdP:1; //Prefetchable
  185. UINT32 AhciCmdR:1; //Reset
  186. UINT32 AhciCmdB:1; //BIST
  187. UINT32 AhciCmdC:1; //Clear Busy upon R_OK
  188. UINT32 AhciCmdRsvd:1;
  189. UINT32 AhciCmdPmp:4; //Port Multiplier Port
  190. UINT32 AhciCmdPrdtl:16; //Physical Region Descriptor Table Length
  191. UINT32 AhciCmdPrdbc; //Physical Region Descriptor Byte Count
  192. UINT32 AhciCmdCtba; //Command Table Descriptor Base Address
  193. UINT32 AhciCmdCtbau; //Command Table Descriptor Base Address Upper 32-BITs
  194. UINT32 AhciCmdRsvd1[4];
  195. } EFI_AHCI_COMMAND_LIST;
  196. //
  197. // This is a software constructed FIS.
  198. // For data transfer operations, this is the H2D Register FIS format as
  199. // specified in the Serial ATA Revision 2.6 specification.
  200. //
  201. typedef struct {
  202. UINT8 AhciCFisType;
  203. UINT8 AhciCFisPmNum:4;
  204. UINT8 AhciCFisRsvd:1;
  205. UINT8 AhciCFisRsvd1:1;
  206. UINT8 AhciCFisRsvd2:1;
  207. UINT8 AhciCFisCmdInd:1;
  208. UINT8 AhciCFisCmd;
  209. UINT8 AhciCFisFeature;
  210. UINT8 AhciCFisSecNum;
  211. UINT8 AhciCFisClyLow;
  212. UINT8 AhciCFisClyHigh;
  213. UINT8 AhciCFisDevHead;
  214. UINT8 AhciCFisSecNumExp;
  215. UINT8 AhciCFisClyLowExp;
  216. UINT8 AhciCFisClyHighExp;
  217. UINT8 AhciCFisFeatureExp;
  218. UINT8 AhciCFisSecCount;
  219. UINT8 AhciCFisSecCountExp;
  220. UINT8 AhciCFisRsvd3;
  221. UINT8 AhciCFisControl;
  222. UINT8 AhciCFisRsvd4[4];
  223. UINT8 AhciCFisRsvd5[44];
  224. } EFI_AHCI_COMMAND_FIS;
  225. //
  226. // ACMD: ATAPI command (12 or 16 bytes)
  227. //
  228. typedef struct {
  229. UINT8 AtapiCmd[0x10];
  230. } EFI_AHCI_ATAPI_COMMAND;
  231. //
  232. // Physical Region Descriptor Table includes up to 65535 entries
  233. // The entry data structure is listed at the following.
  234. // the actual entry number comes from the PRDTL field in the command
  235. // list entry for this command slot.
  236. //
  237. typedef struct {
  238. UINT32 AhciPrdtDba; //Data Base Address
  239. UINT32 AhciPrdtDbau; //Data Base Address Upper 32-BITs
  240. UINT32 AhciPrdtRsvd;
  241. UINT32 AhciPrdtDbc:22; //Data Byte Count
  242. UINT32 AhciPrdtRsvd1:9;
  243. UINT32 AhciPrdtIoc:1; //Interrupt on Completion
  244. } EFI_AHCI_COMMAND_PRDT;
  245. //
  246. // Command table data strucute which is pointed to by the entry in the command list
  247. //
  248. typedef struct {
  249. EFI_AHCI_COMMAND_FIS CommandFis; // A software constructed FIS.
  250. EFI_AHCI_ATAPI_COMMAND AtapiCmd; // 12 or 16 bytes ATAPI cmd.
  251. UINT8 Reserved[0x30];
  252. EFI_AHCI_COMMAND_PRDT PrdtTable[65535]; // The scatter/gather list for data transfer
  253. } EFI_AHCI_COMMAND_TABLE;
  254. //
  255. // Received FIS structure
  256. //
  257. typedef struct {
  258. UINT8 AhciDmaSetupFis[0x1C]; // Dma Setup Fis: offset 0x00
  259. UINT8 AhciDmaSetupFisRsvd[0x04];
  260. UINT8 AhciPioSetupFis[0x14]; // Pio Setup Fis: offset 0x20
  261. UINT8 AhciPioSetupFisRsvd[0x0C];
  262. UINT8 AhciD2HRegisterFis[0x14]; // D2H Register Fis: offset 0x40
  263. UINT8 AhciD2HRegisterFisRsvd[0x04];
  264. UINT64 AhciSetDeviceBitsFis; // Set Device Bits Fix: offset 0x58
  265. UINT8 AhciUnknownFis[0x40]; // Unkonwn Fis: offset 0x60
  266. UINT8 AhciUnknownFisRsvd[0x60];
  267. } EFI_AHCI_RECEIVED_FIS;
  268. typedef struct {
  269. UINT8 Madt : 5;
  270. UINT8 Reserved_5 : 3;
  271. UINT8 Deto;
  272. UINT16 Reserved_16;
  273. UINT32 Reserved_32 : 31;
  274. UINT32 Supported : 1;
  275. } DEVSLP_TIMING_VARIABLES;
  276. #pragma pack()
  277. typedef struct {
  278. EFI_AHCI_RECEIVED_FIS *AhciRFis;
  279. EFI_AHCI_COMMAND_LIST *AhciCmdList;
  280. EFI_AHCI_COMMAND_TABLE *AhciCommandTable;
  281. EFI_AHCI_RECEIVED_FIS *AhciRFisPciAddr;
  282. EFI_AHCI_COMMAND_LIST *AhciCmdListPciAddr;
  283. EFI_AHCI_COMMAND_TABLE *AhciCommandTablePciAddr;
  284. UINT64 MaxCommandListSize;
  285. UINT64 MaxCommandTableSize;
  286. UINT64 MaxReceiveFisSize;
  287. VOID *MapRFis;
  288. VOID *MapCmdList;
  289. VOID *MapCommandTable;
  290. } EFI_AHCI_REGISTERS;
  291. /**
  292. This function is used to send out ATAPI commands conforms to the Packet Command
  293. with PIO Protocol.
  294. @param PciIo The PCI IO protocol instance.
  295. @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
  296. @param Port The number of port.
  297. @param PortMultiplier The number of port multiplier.
  298. @param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.
  299. @retval EFI_SUCCESS send out the ATAPI packet command successfully
  300. and device sends data successfully.
  301. @retval EFI_DEVICE_ERROR the device failed to send data.
  302. **/
  303. EFI_STATUS
  304. EFIAPI
  305. AhciPacketCommandExecute (
  306. IN EFI_PCI_IO_PROTOCOL *PciIo,
  307. IN EFI_AHCI_REGISTERS *AhciRegisters,
  308. IN UINT8 Port,
  309. IN UINT8 PortMultiplier,
  310. IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet
  311. );
  312. /**
  313. Start command for give slot on specific port.
  314. @param PciIo The PCI IO protocol instance.
  315. @param Port The number of port.
  316. @param CommandSlot The number of CommandSlot.
  317. @param Timeout The timeout value of start, uses 100ns as a unit.
  318. @retval EFI_DEVICE_ERROR The command start unsuccessfully.
  319. @retval EFI_TIMEOUT The operation is time out.
  320. @retval EFI_SUCCESS The command start successfully.
  321. **/
  322. EFI_STATUS
  323. EFIAPI
  324. AhciStartCommand (
  325. IN EFI_PCI_IO_PROTOCOL *PciIo,
  326. IN UINT8 Port,
  327. IN UINT8 CommandSlot,
  328. IN UINT64 Timeout
  329. );
  330. /**
  331. Stop command running for giving port
  332. @param PciIo The PCI IO protocol instance.
  333. @param Port The number of port.
  334. @param Timeout The timeout value of stop, uses 100ns as a unit.
  335. @retval EFI_DEVICE_ERROR The command stop unsuccessfully.
  336. @retval EFI_TIMEOUT The operation is time out.
  337. @retval EFI_SUCCESS The command stop successfully.
  338. **/
  339. EFI_STATUS
  340. EFIAPI
  341. AhciStopCommand (
  342. IN EFI_PCI_IO_PROTOCOL *PciIo,
  343. IN UINT8 Port,
  344. IN UINT64 Timeout
  345. );
  346. #endif