PrePi.c 3.9 KB

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  1. /** @file
  2. *
  3. * Copyright (c) 2011-2014, ARM Limited. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: BSD-2-Clause-Patent
  6. *
  7. **/
  8. #include <PiPei.h>
  9. #include <Pi/PiBootMode.h>
  10. #include <Library/PrePiLib.h>
  11. #include <Library/PrintLib.h>
  12. #include <Library/PrePiHobListPointerLib.h>
  13. #include <Library/TimerLib.h>
  14. #include <Library/PerformanceLib.h>
  15. #include <Library/CacheMaintenanceLib.h>
  16. #include <Ppi/GuidedSectionExtraction.h>
  17. #include <Ppi/ArmMpCoreInfo.h>
  18. #include "PrePi.h"
  19. VOID
  20. EFIAPI
  21. ProcessLibraryConstructorList (
  22. VOID
  23. );
  24. VOID
  25. PrePiMain (
  26. IN UINTN UefiMemoryBase,
  27. IN UINTN StacksBase,
  28. IN UINT64 StartTimeStamp
  29. )
  30. {
  31. EFI_HOB_HANDOFF_INFO_TABLE* HobList;
  32. EFI_STATUS Status;
  33. CHAR8 Buffer[100];
  34. UINTN CharCount;
  35. UINTN StacksSize;
  36. // Initialize the architecture specific bits
  37. ArchInitialize ();
  38. // Declare the PI/UEFI memory region
  39. HobList = HobConstructor (
  40. (VOID*)UefiMemoryBase,
  41. FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),
  42. (VOID*)UefiMemoryBase,
  43. (VOID*)StacksBase // The top of the UEFI Memory is reserved for the stacks
  44. );
  45. PrePeiSetHobList (HobList);
  46. //
  47. // Ensure that the loaded image is invalidated in the caches, so that any
  48. // modifications we made with the caches and MMU off (such as the applied
  49. // relocations) don't become invisible once we turn them on.
  50. //
  51. InvalidateDataCacheRange((VOID *)(UINTN)PcdGet64 (PcdFdBaseAddress), PcdGet32 (PcdFdSize));
  52. // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)
  53. Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));
  54. ASSERT_EFI_ERROR (Status);
  55. // Initialize the Serial Port
  56. SerialPortInitialize ();
  57. CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware (version %s built at %a on %a)\n\r",
  58. (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
  59. SerialPortWrite ((UINT8 *) Buffer, CharCount);
  60. // Create the Stacks HOB (reserve the memory for all stacks)
  61. StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);
  62. BuildStackHob (StacksBase, StacksSize);
  63. //TODO: Call CpuPei as a library
  64. BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));
  65. // Set the Boot Mode
  66. SetBootMode (BOOT_WITH_FULL_CONFIGURATION);
  67. // Initialize Platform HOBs (CpuHob and FvHob)
  68. Status = PlatformPeim ();
  69. ASSERT_EFI_ERROR (Status);
  70. // Now, the HOB List has been initialized, we can register performance information
  71. PERF_START (NULL, "PEI", NULL, StartTimeStamp);
  72. // SEC phase needs to run library constructors by hand.
  73. ProcessLibraryConstructorList ();
  74. // Assume the FV that contains the SEC (our code) also contains a compressed FV.
  75. Status = DecompressFirstFv ();
  76. ASSERT_EFI_ERROR (Status);
  77. // Load the DXE Core and transfer control to it
  78. Status = LoadDxeCoreFromFv (NULL, 0);
  79. ASSERT_EFI_ERROR (Status);
  80. }
  81. VOID
  82. CEntryPoint (
  83. IN UINTN MpId,
  84. IN UINTN UefiMemoryBase,
  85. IN UINTN StacksBase
  86. )
  87. {
  88. UINT64 StartTimeStamp;
  89. if (PerformanceMeasurementEnabled ()) {
  90. // Initialize the Timer Library to setup the Timer HW controller
  91. TimerConstructor ();
  92. // We cannot call yet the PerformanceLib because the HOB List has not been initialized
  93. StartTimeStamp = GetPerformanceCounter ();
  94. } else {
  95. StartTimeStamp = 0;
  96. }
  97. // Data Cache enabled on Primary core when MMU is enabled.
  98. ArmDisableDataCache ();
  99. // Invalidate instruction cache
  100. ArmInvalidateInstructionCache ();
  101. // Enable Instruction Caches on all cores.
  102. ArmEnableInstructionCache ();
  103. PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);
  104. // DXE Core should always load and never return
  105. ASSERT (FALSE);
  106. }