FdtPciHostBridgeLib.c 15 KB

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  1. /** @file
  2. PCI Host Bridge Library instance for pci-ecam-generic DT nodes
  3. Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <PiDxe.h>
  7. #include <Library/PciHostBridgeLib.h>
  8. #include <Library/DebugLib.h>
  9. #include <Library/DevicePathLib.h>
  10. #include <Library/DxeServicesTableLib.h>
  11. #include <Library/MemoryAllocationLib.h>
  12. #include <Library/PcdLib.h>
  13. #include <Library/UefiBootServicesTableLib.h>
  14. #include <Protocol/FdtClient.h>
  15. #include <Protocol/PciRootBridgeIo.h>
  16. #include <Protocol/PciHostBridgeResourceAllocation.h>
  17. #pragma pack(1)
  18. typedef struct {
  19. ACPI_HID_DEVICE_PATH AcpiDevicePath;
  20. EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
  21. } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
  22. #pragma pack ()
  23. STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = {
  24. {
  25. {
  26. ACPI_DEVICE_PATH,
  27. ACPI_DP,
  28. {
  29. (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  30. (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  31. }
  32. },
  33. EISA_PNP_ID(0x0A03),
  34. 0
  35. },
  36. {
  37. END_DEVICE_PATH_TYPE,
  38. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  39. {
  40. END_DEVICE_PATH_LENGTH,
  41. 0
  42. }
  43. }
  44. };
  45. GLOBAL_REMOVE_IF_UNREFERENCED
  46. CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
  47. L"Mem", L"I/O", L"Bus"
  48. };
  49. //
  50. // We expect the "ranges" property of "pci-host-ecam-generic" to consist of
  51. // records like this.
  52. //
  53. #pragma pack (1)
  54. typedef struct {
  55. UINT32 Type;
  56. UINT64 ChildBase;
  57. UINT64 CpuBase;
  58. UINT64 Size;
  59. } DTB_PCI_HOST_RANGE_RECORD;
  60. #pragma pack ()
  61. #define DTB_PCI_HOST_RANGE_RELOCATABLE BIT31
  62. #define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
  63. #define DTB_PCI_HOST_RANGE_ALIASED BIT29
  64. #define DTB_PCI_HOST_RANGE_MMIO32 BIT25
  65. #define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24)
  66. #define DTB_PCI_HOST_RANGE_IO BIT24
  67. #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
  68. STATIC
  69. EFI_STATUS
  70. MapGcdMmioSpace (
  71. IN UINT64 Base,
  72. IN UINT64 Size
  73. )
  74. {
  75. EFI_STATUS Status;
  76. Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo, Base, Size,
  77. EFI_MEMORY_UC);
  78. if (EFI_ERROR (Status)) {
  79. DEBUG ((DEBUG_ERROR,
  80. "%a: failed to add GCD memory space for region [0x%Lx+0x%Lx)\n",
  81. __FUNCTION__, Base, Size));
  82. return Status;
  83. }
  84. Status = gDS->SetMemorySpaceAttributes (Base, Size, EFI_MEMORY_UC);
  85. if (EFI_ERROR (Status)) {
  86. DEBUG ((DEBUG_ERROR,
  87. "%a: failed to set memory space attributes for region [0x%Lx+0x%Lx)\n",
  88. __FUNCTION__, Base, Size));
  89. }
  90. return Status;
  91. }
  92. STATIC
  93. EFI_STATUS
  94. ProcessPciHost (
  95. OUT UINT64 *IoBase,
  96. OUT UINT64 *IoSize,
  97. OUT UINT64 *Mmio32Base,
  98. OUT UINT64 *Mmio32Size,
  99. OUT UINT64 *Mmio64Base,
  100. OUT UINT64 *Mmio64Size,
  101. OUT UINT32 *BusMin,
  102. OUT UINT32 *BusMax
  103. )
  104. {
  105. FDT_CLIENT_PROTOCOL *FdtClient;
  106. INT32 Node;
  107. UINT64 ConfigBase, ConfigSize;
  108. CONST VOID *Prop;
  109. UINT32 Len;
  110. UINT32 RecordIdx;
  111. EFI_STATUS Status;
  112. UINT64 IoTranslation;
  113. UINT64 Mmio32Translation;
  114. UINT64 Mmio64Translation;
  115. //
  116. // The following output arguments are initialized only in
  117. // order to suppress '-Werror=maybe-uninitialized' warnings
  118. // *incorrectly* emitted by some gcc versions.
  119. //
  120. *IoBase = 0;
  121. *Mmio32Base = 0;
  122. *Mmio64Base = MAX_UINT64;
  123. *BusMin = 0;
  124. *BusMax = 0;
  125. //
  126. // *IoSize, *Mmio##Size and IoTranslation are initialized to zero because the
  127. // logic below requires it. However, since they are also affected by the issue
  128. // reported above, they are initialized early.
  129. //
  130. *IoSize = 0;
  131. *Mmio32Size = 0;
  132. *Mmio64Size = 0;
  133. IoTranslation = 0;
  134. Status = gBS->LocateProtocol (&gFdtClientProtocolGuid, NULL,
  135. (VOID **)&FdtClient);
  136. ASSERT_EFI_ERROR (Status);
  137. Status = FdtClient->FindCompatibleNode (FdtClient, "pci-host-ecam-generic",
  138. &Node);
  139. if (EFI_ERROR (Status)) {
  140. DEBUG ((EFI_D_INFO,
  141. "%a: No 'pci-host-ecam-generic' compatible DT node found\n",
  142. __FUNCTION__));
  143. return EFI_NOT_FOUND;
  144. }
  145. DEBUG_CODE (
  146. INT32 Tmp;
  147. //
  148. // A DT can legally describe multiple PCI host bridges, but we are not
  149. // equipped to deal with that. So assert that there is only one.
  150. //
  151. Status = FdtClient->FindNextCompatibleNode (FdtClient,
  152. "pci-host-ecam-generic", Node, &Tmp);
  153. ASSERT (Status == EFI_NOT_FOUND);
  154. );
  155. Status = FdtClient->GetNodeProperty (FdtClient, Node, "reg", &Prop, &Len);
  156. if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT64)) {
  157. DEBUG ((EFI_D_ERROR, "%a: 'reg' property not found or invalid\n",
  158. __FUNCTION__));
  159. return EFI_PROTOCOL_ERROR;
  160. }
  161. //
  162. // Fetch the ECAM window.
  163. //
  164. ConfigBase = SwapBytes64 (((CONST UINT64 *)Prop)[0]);
  165. ConfigSize = SwapBytes64 (((CONST UINT64 *)Prop)[1]);
  166. //
  167. // Fetch the bus range (note: inclusive).
  168. //
  169. Status = FdtClient->GetNodeProperty (FdtClient, Node, "bus-range", &Prop,
  170. &Len);
  171. if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT32)) {
  172. DEBUG ((EFI_D_ERROR, "%a: 'bus-range' not found or invalid\n",
  173. __FUNCTION__));
  174. return EFI_PROTOCOL_ERROR;
  175. }
  176. *BusMin = SwapBytes32 (((CONST UINT32 *)Prop)[0]);
  177. *BusMax = SwapBytes32 (((CONST UINT32 *)Prop)[1]);
  178. //
  179. // Sanity check: the config space must accommodate all 4K register bytes of
  180. // all 8 functions of all 32 devices of all buses.
  181. //
  182. if (*BusMax < *BusMin || *BusMax - *BusMin == MAX_UINT32 ||
  183. DivU64x32 (ConfigSize, SIZE_4KB * 8 * 32) < *BusMax - *BusMin + 1) {
  184. DEBUG ((EFI_D_ERROR, "%a: invalid 'bus-range' and/or 'reg'\n",
  185. __FUNCTION__));
  186. return EFI_PROTOCOL_ERROR;
  187. }
  188. //
  189. // Iterate over "ranges".
  190. //
  191. Status = FdtClient->GetNodeProperty (FdtClient, Node, "ranges", &Prop, &Len);
  192. if (EFI_ERROR (Status) || Len == 0 ||
  193. Len % sizeof (DTB_PCI_HOST_RANGE_RECORD) != 0) {
  194. DEBUG ((EFI_D_ERROR, "%a: 'ranges' not found or invalid\n", __FUNCTION__));
  195. return EFI_PROTOCOL_ERROR;
  196. }
  197. for (RecordIdx = 0; RecordIdx < Len / sizeof (DTB_PCI_HOST_RANGE_RECORD);
  198. ++RecordIdx) {
  199. CONST DTB_PCI_HOST_RANGE_RECORD *Record;
  200. Record = (CONST DTB_PCI_HOST_RANGE_RECORD *)Prop + RecordIdx;
  201. switch (SwapBytes32 (Record->Type) & DTB_PCI_HOST_RANGE_TYPEMASK) {
  202. case DTB_PCI_HOST_RANGE_IO:
  203. *IoBase = SwapBytes64 (Record->ChildBase);
  204. *IoSize = SwapBytes64 (Record->Size);
  205. IoTranslation = SwapBytes64 (Record->CpuBase) - *IoBase;
  206. ASSERT (PcdGet64 (PcdPciIoTranslation) == IoTranslation);
  207. break;
  208. case DTB_PCI_HOST_RANGE_MMIO32:
  209. *Mmio32Base = SwapBytes64 (Record->ChildBase);
  210. *Mmio32Size = SwapBytes64 (Record->Size);
  211. Mmio32Translation = SwapBytes64 (Record->CpuBase) - *Mmio32Base;
  212. if (*Mmio32Base > MAX_UINT32 || *Mmio32Size > MAX_UINT32 ||
  213. *Mmio32Base + *Mmio32Size > SIZE_4GB) {
  214. DEBUG ((EFI_D_ERROR, "%a: MMIO32 space invalid\n", __FUNCTION__));
  215. return EFI_PROTOCOL_ERROR;
  216. }
  217. ASSERT (PcdGet64 (PcdPciMmio32Translation) == Mmio32Translation);
  218. if (Mmio32Translation != 0) {
  219. DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO32 translation "
  220. "0x%Lx\n", __FUNCTION__, Mmio32Translation));
  221. return EFI_UNSUPPORTED;
  222. }
  223. break;
  224. case DTB_PCI_HOST_RANGE_MMIO64:
  225. *Mmio64Base = SwapBytes64 (Record->ChildBase);
  226. *Mmio64Size = SwapBytes64 (Record->Size);
  227. Mmio64Translation = SwapBytes64 (Record->CpuBase) - *Mmio64Base;
  228. ASSERT (PcdGet64 (PcdPciMmio64Translation) == Mmio64Translation);
  229. if (Mmio64Translation != 0) {
  230. DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO64 translation "
  231. "0x%Lx\n", __FUNCTION__, Mmio64Translation));
  232. return EFI_UNSUPPORTED;
  233. }
  234. break;
  235. }
  236. }
  237. if (*IoSize == 0 || *Mmio32Size == 0) {
  238. DEBUG ((EFI_D_ERROR, "%a: %a space empty\n", __FUNCTION__,
  239. (*IoSize == 0) ? "IO" : "MMIO32"));
  240. return EFI_PROTOCOL_ERROR;
  241. }
  242. //
  243. // The dynamic PCD PcdPciExpressBaseAddress should have already been set,
  244. // and should match the value we found in the DT node.
  245. //
  246. ASSERT (PcdGet64 (PcdPciExpressBaseAddress) == ConfigBase);
  247. DEBUG ((EFI_D_INFO, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] "
  248. "Io[0x%Lx+0x%Lx)@0x%Lx Mem32[0x%Lx+0x%Lx)@0x0 Mem64[0x%Lx+0x%Lx)@0x0\n",
  249. __FUNCTION__, ConfigBase, ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize,
  250. IoTranslation, *Mmio32Base, *Mmio32Size, *Mmio64Base, *Mmio64Size));
  251. // Map the ECAM space in the GCD memory map
  252. Status = MapGcdMmioSpace (ConfigBase, ConfigSize);
  253. ASSERT_EFI_ERROR (Status);
  254. if (EFI_ERROR (Status)) {
  255. return Status;
  256. }
  257. //
  258. // Map the MMIO window that provides I/O access - the PCI host bridge code
  259. // is not aware of this translation and so it will only map the I/O view
  260. // in the GCD I/O map.
  261. //
  262. Status = MapGcdMmioSpace (*IoBase + IoTranslation, *IoSize);
  263. ASSERT_EFI_ERROR (Status);
  264. return Status;
  265. }
  266. STATIC PCI_ROOT_BRIDGE mRootBridge;
  267. /**
  268. Return all the root bridge instances in an array.
  269. @param Count Return the count of root bridge instances.
  270. @return All the root bridge instances in an array.
  271. The array should be passed into PciHostBridgeFreeRootBridges()
  272. when it's not used.
  273. **/
  274. PCI_ROOT_BRIDGE *
  275. EFIAPI
  276. PciHostBridgeGetRootBridges (
  277. UINTN *Count
  278. )
  279. {
  280. UINT64 IoBase, IoSize;
  281. UINT64 Mmio32Base, Mmio32Size;
  282. UINT64 Mmio64Base, Mmio64Size;
  283. UINT32 BusMin, BusMax;
  284. EFI_STATUS Status;
  285. if (PcdGet64 (PcdPciExpressBaseAddress) == 0) {
  286. DEBUG ((EFI_D_INFO, "%a: PCI host bridge not present\n", __FUNCTION__));
  287. *Count = 0;
  288. return NULL;
  289. }
  290. Status = ProcessPciHost (&IoBase, &IoSize, &Mmio32Base, &Mmio32Size,
  291. &Mmio64Base, &Mmio64Size, &BusMin, &BusMax);
  292. if (EFI_ERROR (Status)) {
  293. DEBUG ((EFI_D_ERROR, "%a: failed to discover PCI host bridge: %r\n",
  294. __FUNCTION__, Status));
  295. *Count = 0;
  296. return NULL;
  297. }
  298. *Count = 1;
  299. mRootBridge.Segment = 0;
  300. mRootBridge.Supports = EFI_PCI_ATTRIBUTE_ISA_IO_16 |
  301. EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
  302. EFI_PCI_ATTRIBUTE_VGA_IO_16 |
  303. EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
  304. mRootBridge.Attributes = mRootBridge.Supports;
  305. mRootBridge.DmaAbove4G = TRUE;
  306. mRootBridge.NoExtendedConfigSpace = FALSE;
  307. mRootBridge.ResourceAssigned = FALSE;
  308. mRootBridge.AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;
  309. mRootBridge.Bus.Base = BusMin;
  310. mRootBridge.Bus.Limit = BusMax;
  311. mRootBridge.Io.Base = IoBase;
  312. mRootBridge.Io.Limit = IoBase + IoSize - 1;
  313. mRootBridge.Mem.Base = Mmio32Base;
  314. mRootBridge.Mem.Limit = Mmio32Base + Mmio32Size - 1;
  315. if (sizeof (UINTN) == sizeof (UINT64)) {
  316. mRootBridge.MemAbove4G.Base = Mmio64Base;
  317. mRootBridge.MemAbove4G.Limit = Mmio64Base + Mmio64Size - 1;
  318. if (Mmio64Size > 0) {
  319. mRootBridge.AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
  320. }
  321. } else {
  322. //
  323. // UEFI mandates a 1:1 virtual-to-physical mapping, so on a 32-bit
  324. // architecture such as ARM, we will not be able to access 64-bit MMIO
  325. // BARs unless they are allocated below 4 GB. So ignore the range above
  326. // 4 GB in this case.
  327. //
  328. mRootBridge.MemAbove4G.Base = MAX_UINT64;
  329. mRootBridge.MemAbove4G.Limit = 0;
  330. }
  331. //
  332. // No separate ranges for prefetchable and non-prefetchable BARs
  333. //
  334. mRootBridge.PMem.Base = MAX_UINT64;
  335. mRootBridge.PMem.Limit = 0;
  336. mRootBridge.PMemAbove4G.Base = MAX_UINT64;
  337. mRootBridge.PMemAbove4G.Limit = 0;
  338. mRootBridge.DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath;
  339. return &mRootBridge;
  340. }
  341. /**
  342. Free the root bridge instances array returned from
  343. PciHostBridgeGetRootBridges().
  344. @param Bridges The root bridge instances array.
  345. @param Count The count of the array.
  346. **/
  347. VOID
  348. EFIAPI
  349. PciHostBridgeFreeRootBridges (
  350. PCI_ROOT_BRIDGE *Bridges,
  351. UINTN Count
  352. )
  353. {
  354. ASSERT (Count == 1);
  355. }
  356. /**
  357. Inform the platform that the resource conflict happens.
  358. @param HostBridgeHandle Handle of the Host Bridge.
  359. @param Configuration Pointer to PCI I/O and PCI memory resource
  360. descriptors. The Configuration contains the resources
  361. for all the root bridges. The resource for each root
  362. bridge is terminated with END descriptor and an
  363. additional END is appended indicating the end of the
  364. entire resources. The resource descriptor field
  365. values follow the description in
  366. EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
  367. .SubmitResources().
  368. **/
  369. VOID
  370. EFIAPI
  371. PciHostBridgeResourceConflict (
  372. EFI_HANDLE HostBridgeHandle,
  373. VOID *Configuration
  374. )
  375. {
  376. EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
  377. UINTN RootBridgeIndex;
  378. DEBUG ((EFI_D_ERROR, "PciHostBridge: Resource conflict happens!\n"));
  379. RootBridgeIndex = 0;
  380. Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
  381. while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
  382. DEBUG ((EFI_D_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
  383. for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
  384. ASSERT (Descriptor->ResType <
  385. (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) /
  386. sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])
  387. )
  388. );
  389. DEBUG ((EFI_D_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
  390. mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
  391. Descriptor->AddrLen, Descriptor->AddrRangeMax
  392. ));
  393. if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
  394. DEBUG ((EFI_D_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
  395. Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
  396. ((Descriptor->SpecificFlag &
  397. EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
  398. ) != 0) ? L" (Prefetchable)" : L""
  399. ));
  400. }
  401. }
  402. //
  403. // Skip the END descriptor for root bridge
  404. //
  405. ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
  406. Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
  407. (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
  408. );
  409. }
  410. }