PciExpressLib.c 48 KB

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  1. /** @file
  2. Functions in this library instance make use of MMIO functions in IoLib to
  3. access memory mapped PCI configuration space.
  4. All assertions for I/O operations are handled in MMIO functions in the IoLib
  5. Library.
  6. Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
  7. SPDX-License-Identifier: BSD-2-Clause-Patent
  8. **/
  9. #include <Base.h>
  10. #include <Library/BaseLib.h>
  11. #include <Library/PciExpressLib.h>
  12. #include <Library/IoLib.h>
  13. #include <Library/DebugLib.h>
  14. #include <Library/PcdLib.h>
  15. /**
  16. Assert the validity of a PCI address. A valid PCI address should contain 1's
  17. only in the low 28 bits.
  18. @param A The address to validate.
  19. **/
  20. #define ASSERT_INVALID_PCI_ADDRESS(A) \
  21. ASSERT (((A) & ~0xfffffff) == 0)
  22. /**
  23. Registers a PCI device so PCI configuration registers may be accessed after
  24. SetVirtualAddressMap().
  25. Registers the PCI device specified by Address so all the PCI configuration
  26. registers associated with that PCI device may be accessed after SetVirtualAddressMap()
  27. is called.
  28. If Address > 0x0FFFFFFF, then ASSERT().
  29. @param Address The address that encodes the PCI Bus, Device, Function and
  30. Register.
  31. @retval RETURN_SUCCESS The PCI device was registered for runtime access.
  32. @retval RETURN_UNSUPPORTED An attempt was made to call this function
  33. after ExitBootServices().
  34. @retval RETURN_UNSUPPORTED The resources required to access the PCI device
  35. at runtime could not be mapped.
  36. @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
  37. complete the registration.
  38. **/
  39. RETURN_STATUS
  40. EFIAPI
  41. PciExpressRegisterForRuntimeAccess (
  42. IN UINTN Address
  43. )
  44. {
  45. ASSERT_INVALID_PCI_ADDRESS (Address);
  46. return RETURN_UNSUPPORTED;
  47. }
  48. STATIC UINT64 mPciExpressBaseAddress;
  49. RETURN_STATUS
  50. EFIAPI
  51. PciExpressLibInitialize (
  52. VOID
  53. )
  54. {
  55. mPciExpressBaseAddress = PcdGet64 (PcdPciExpressBaseAddress);
  56. return RETURN_SUCCESS;
  57. }
  58. /**
  59. Gets the base address of PCI Express.
  60. @return The base address of PCI Express.
  61. **/
  62. VOID*
  63. GetPciExpressBaseAddress (
  64. VOID
  65. )
  66. {
  67. return (VOID*)(UINTN) mPciExpressBaseAddress;
  68. }
  69. /**
  70. Reads an 8-bit PCI configuration register.
  71. Reads and returns the 8-bit PCI configuration register specified by Address.
  72. This function must guarantee that all PCI read and write operations are
  73. serialized.
  74. If Address > 0x0FFFFFFF, then ASSERT().
  75. @param Address The address that encodes the PCI Bus, Device, Function and
  76. Register.
  77. @return The read value from the PCI configuration register.
  78. **/
  79. UINT8
  80. EFIAPI
  81. PciExpressRead8 (
  82. IN UINTN Address
  83. )
  84. {
  85. ASSERT_INVALID_PCI_ADDRESS (Address);
  86. return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address);
  87. }
  88. /**
  89. Writes an 8-bit PCI configuration register.
  90. Writes the 8-bit PCI configuration register specified by Address with the
  91. value specified by Value. Value is returned. This function must guarantee
  92. that all PCI read and write operations are serialized.
  93. If Address > 0x0FFFFFFF, then ASSERT().
  94. @param Address The address that encodes the PCI Bus, Device, Function and
  95. Register.
  96. @param Value The value to write.
  97. @return The value written to the PCI configuration register.
  98. **/
  99. UINT8
  100. EFIAPI
  101. PciExpressWrite8 (
  102. IN UINTN Address,
  103. IN UINT8 Value
  104. )
  105. {
  106. ASSERT_INVALID_PCI_ADDRESS (Address);
  107. return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value);
  108. }
  109. /**
  110. Performs a bitwise OR of an 8-bit PCI configuration register with
  111. an 8-bit value.
  112. Reads the 8-bit PCI configuration register specified by Address, performs a
  113. bitwise OR between the read result and the value specified by
  114. OrData, and writes the result to the 8-bit PCI configuration register
  115. specified by Address. The value written to the PCI configuration register is
  116. returned. This function must guarantee that all PCI read and write operations
  117. are serialized.
  118. If Address > 0x0FFFFFFF, then ASSERT().
  119. @param Address The address that encodes the PCI Bus, Device, Function and
  120. Register.
  121. @param OrData The value to OR with the PCI configuration register.
  122. @return The value written back to the PCI configuration register.
  123. **/
  124. UINT8
  125. EFIAPI
  126. PciExpressOr8 (
  127. IN UINTN Address,
  128. IN UINT8 OrData
  129. )
  130. {
  131. ASSERT_INVALID_PCI_ADDRESS (Address);
  132. return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);
  133. }
  134. /**
  135. Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
  136. value.
  137. Reads the 8-bit PCI configuration register specified by Address, performs a
  138. bitwise AND between the read result and the value specified by AndData, and
  139. writes the result to the 8-bit PCI configuration register specified by
  140. Address. The value written to the PCI configuration register is returned.
  141. This function must guarantee that all PCI read and write operations are
  142. serialized.
  143. If Address > 0x0FFFFFFF, then ASSERT().
  144. @param Address The address that encodes the PCI Bus, Device, Function and
  145. Register.
  146. @param AndData The value to AND with the PCI configuration register.
  147. @return The value written back to the PCI configuration register.
  148. **/
  149. UINT8
  150. EFIAPI
  151. PciExpressAnd8 (
  152. IN UINTN Address,
  153. IN UINT8 AndData
  154. )
  155. {
  156. ASSERT_INVALID_PCI_ADDRESS (Address);
  157. return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);
  158. }
  159. /**
  160. Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
  161. value, followed a bitwise OR with another 8-bit value.
  162. Reads the 8-bit PCI configuration register specified by Address, performs a
  163. bitwise AND between the read result and the value specified by AndData,
  164. performs a bitwise OR between the result of the AND operation and
  165. the value specified by OrData, and writes the result to the 8-bit PCI
  166. configuration register specified by Address. The value written to the PCI
  167. configuration register is returned. This function must guarantee that all PCI
  168. read and write operations are serialized.
  169. If Address > 0x0FFFFFFF, then ASSERT().
  170. @param Address The address that encodes the PCI Bus, Device, Function and
  171. Register.
  172. @param AndData The value to AND with the PCI configuration register.
  173. @param OrData The value to OR with the result of the AND operation.
  174. @return The value written back to the PCI configuration register.
  175. **/
  176. UINT8
  177. EFIAPI
  178. PciExpressAndThenOr8 (
  179. IN UINTN Address,
  180. IN UINT8 AndData,
  181. IN UINT8 OrData
  182. )
  183. {
  184. ASSERT_INVALID_PCI_ADDRESS (Address);
  185. return MmioAndThenOr8 (
  186. (UINTN) GetPciExpressBaseAddress () + Address,
  187. AndData,
  188. OrData
  189. );
  190. }
  191. /**
  192. Reads a bit field of a PCI configuration register.
  193. Reads the bit field in an 8-bit PCI configuration register. The bit field is
  194. specified by the StartBit and the EndBit. The value of the bit field is
  195. returned.
  196. If Address > 0x0FFFFFFF, then ASSERT().
  197. If StartBit is greater than 7, then ASSERT().
  198. If EndBit is greater than 7, then ASSERT().
  199. If EndBit is less than StartBit, then ASSERT().
  200. @param Address The PCI configuration register to read.
  201. @param StartBit The ordinal of the least significant bit in the bit field.
  202. Range 0..7.
  203. @param EndBit The ordinal of the most significant bit in the bit field.
  204. Range 0..7.
  205. @return The value of the bit field read from the PCI configuration register.
  206. **/
  207. UINT8
  208. EFIAPI
  209. PciExpressBitFieldRead8 (
  210. IN UINTN Address,
  211. IN UINTN StartBit,
  212. IN UINTN EndBit
  213. )
  214. {
  215. ASSERT_INVALID_PCI_ADDRESS (Address);
  216. return MmioBitFieldRead8 (
  217. (UINTN) GetPciExpressBaseAddress () + Address,
  218. StartBit,
  219. EndBit
  220. );
  221. }
  222. /**
  223. Writes a bit field to a PCI configuration register.
  224. Writes Value to the bit field of the PCI configuration register. The bit
  225. field is specified by the StartBit and the EndBit. All other bits in the
  226. destination PCI configuration register are preserved. The new value of the
  227. 8-bit register is returned.
  228. If Address > 0x0FFFFFFF, then ASSERT().
  229. If StartBit is greater than 7, then ASSERT().
  230. If EndBit is greater than 7, then ASSERT().
  231. If EndBit is less than StartBit, then ASSERT().
  232. If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
  233. @param Address The PCI configuration register to write.
  234. @param StartBit The ordinal of the least significant bit in the bit field.
  235. Range 0..7.
  236. @param EndBit The ordinal of the most significant bit in the bit field.
  237. Range 0..7.
  238. @param Value The new value of the bit field.
  239. @return The value written back to the PCI configuration register.
  240. **/
  241. UINT8
  242. EFIAPI
  243. PciExpressBitFieldWrite8 (
  244. IN UINTN Address,
  245. IN UINTN StartBit,
  246. IN UINTN EndBit,
  247. IN UINT8 Value
  248. )
  249. {
  250. ASSERT_INVALID_PCI_ADDRESS (Address);
  251. return MmioBitFieldWrite8 (
  252. (UINTN) GetPciExpressBaseAddress () + Address,
  253. StartBit,
  254. EndBit,
  255. Value
  256. );
  257. }
  258. /**
  259. Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
  260. writes the result back to the bit field in the 8-bit port.
  261. Reads the 8-bit PCI configuration register specified by Address, performs a
  262. bitwise OR between the read result and the value specified by
  263. OrData, and writes the result to the 8-bit PCI configuration register
  264. specified by Address. The value written to the PCI configuration register is
  265. returned. This function must guarantee that all PCI read and write operations
  266. are serialized. Extra left bits in OrData are stripped.
  267. If Address > 0x0FFFFFFF, then ASSERT().
  268. If StartBit is greater than 7, then ASSERT().
  269. If EndBit is greater than 7, then ASSERT().
  270. If EndBit is less than StartBit, then ASSERT().
  271. If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
  272. @param Address The PCI configuration register to write.
  273. @param StartBit The ordinal of the least significant bit in the bit field.
  274. Range 0..7.
  275. @param EndBit The ordinal of the most significant bit in the bit field.
  276. Range 0..7.
  277. @param OrData The value to OR with the PCI configuration register.
  278. @return The value written back to the PCI configuration register.
  279. **/
  280. UINT8
  281. EFIAPI
  282. PciExpressBitFieldOr8 (
  283. IN UINTN Address,
  284. IN UINTN StartBit,
  285. IN UINTN EndBit,
  286. IN UINT8 OrData
  287. )
  288. {
  289. ASSERT_INVALID_PCI_ADDRESS (Address);
  290. return MmioBitFieldOr8 (
  291. (UINTN) GetPciExpressBaseAddress () + Address,
  292. StartBit,
  293. EndBit,
  294. OrData
  295. );
  296. }
  297. /**
  298. Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
  299. AND, and writes the result back to the bit field in the 8-bit register.
  300. Reads the 8-bit PCI configuration register specified by Address, performs a
  301. bitwise AND between the read result and the value specified by AndData, and
  302. writes the result to the 8-bit PCI configuration register specified by
  303. Address. The value written to the PCI configuration register is returned.
  304. This function must guarantee that all PCI read and write operations are
  305. serialized. Extra left bits in AndData are stripped.
  306. If Address > 0x0FFFFFFF, then ASSERT().
  307. If StartBit is greater than 7, then ASSERT().
  308. If EndBit is greater than 7, then ASSERT().
  309. If EndBit is less than StartBit, then ASSERT().
  310. If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
  311. @param Address The PCI configuration register to write.
  312. @param StartBit The ordinal of the least significant bit in the bit field.
  313. Range 0..7.
  314. @param EndBit The ordinal of the most significant bit in the bit field.
  315. Range 0..7.
  316. @param AndData The value to AND with the PCI configuration register.
  317. @return The value written back to the PCI configuration register.
  318. **/
  319. UINT8
  320. EFIAPI
  321. PciExpressBitFieldAnd8 (
  322. IN UINTN Address,
  323. IN UINTN StartBit,
  324. IN UINTN EndBit,
  325. IN UINT8 AndData
  326. )
  327. {
  328. ASSERT_INVALID_PCI_ADDRESS (Address);
  329. return MmioBitFieldAnd8 (
  330. (UINTN) GetPciExpressBaseAddress () + Address,
  331. StartBit,
  332. EndBit,
  333. AndData
  334. );
  335. }
  336. /**
  337. Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
  338. bitwise OR, and writes the result back to the bit field in the
  339. 8-bit port.
  340. Reads the 8-bit PCI configuration register specified by Address, performs a
  341. bitwise AND followed by a bitwise OR between the read result and
  342. the value specified by AndData, and writes the result to the 8-bit PCI
  343. configuration register specified by Address. The value written to the PCI
  344. configuration register is returned. This function must guarantee that all PCI
  345. read and write operations are serialized. Extra left bits in both AndData and
  346. OrData are stripped.
  347. If Address > 0x0FFFFFFF, then ASSERT().
  348. If StartBit is greater than 7, then ASSERT().
  349. If EndBit is greater than 7, then ASSERT().
  350. If EndBit is less than StartBit, then ASSERT().
  351. If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
  352. If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
  353. @param Address The PCI configuration register to write.
  354. @param StartBit The ordinal of the least significant bit in the bit field.
  355. Range 0..7.
  356. @param EndBit The ordinal of the most significant bit in the bit field.
  357. Range 0..7.
  358. @param AndData The value to AND with the PCI configuration register.
  359. @param OrData The value to OR with the result of the AND operation.
  360. @return The value written back to the PCI configuration register.
  361. **/
  362. UINT8
  363. EFIAPI
  364. PciExpressBitFieldAndThenOr8 (
  365. IN UINTN Address,
  366. IN UINTN StartBit,
  367. IN UINTN EndBit,
  368. IN UINT8 AndData,
  369. IN UINT8 OrData
  370. )
  371. {
  372. ASSERT_INVALID_PCI_ADDRESS (Address);
  373. return MmioBitFieldAndThenOr8 (
  374. (UINTN) GetPciExpressBaseAddress () + Address,
  375. StartBit,
  376. EndBit,
  377. AndData,
  378. OrData
  379. );
  380. }
  381. /**
  382. Reads a 16-bit PCI configuration register.
  383. Reads and returns the 16-bit PCI configuration register specified by Address.
  384. This function must guarantee that all PCI read and write operations are
  385. serialized.
  386. If Address > 0x0FFFFFFF, then ASSERT().
  387. If Address is not aligned on a 16-bit boundary, then ASSERT().
  388. @param Address The address that encodes the PCI Bus, Device, Function and
  389. Register.
  390. @return The read value from the PCI configuration register.
  391. **/
  392. UINT16
  393. EFIAPI
  394. PciExpressRead16 (
  395. IN UINTN Address
  396. )
  397. {
  398. ASSERT_INVALID_PCI_ADDRESS (Address);
  399. return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address);
  400. }
  401. /**
  402. Writes a 16-bit PCI configuration register.
  403. Writes the 16-bit PCI configuration register specified by Address with the
  404. value specified by Value. Value is returned. This function must guarantee
  405. that all PCI read and write operations are serialized.
  406. If Address > 0x0FFFFFFF, then ASSERT().
  407. If Address is not aligned on a 16-bit boundary, then ASSERT().
  408. @param Address The address that encodes the PCI Bus, Device, Function and
  409. Register.
  410. @param Value The value to write.
  411. @return The value written to the PCI configuration register.
  412. **/
  413. UINT16
  414. EFIAPI
  415. PciExpressWrite16 (
  416. IN UINTN Address,
  417. IN UINT16 Value
  418. )
  419. {
  420. ASSERT_INVALID_PCI_ADDRESS (Address);
  421. return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value);
  422. }
  423. /**
  424. Performs a bitwise OR of a 16-bit PCI configuration register with
  425. a 16-bit value.
  426. Reads the 16-bit PCI configuration register specified by Address, performs a
  427. bitwise OR between the read result and the value specified by
  428. OrData, and writes the result to the 16-bit PCI configuration register
  429. specified by Address. The value written to the PCI configuration register is
  430. returned. This function must guarantee that all PCI read and write operations
  431. are serialized.
  432. If Address > 0x0FFFFFFF, then ASSERT().
  433. If Address is not aligned on a 16-bit boundary, then ASSERT().
  434. @param Address The address that encodes the PCI Bus, Device, Function and
  435. Register.
  436. @param OrData The value to OR with the PCI configuration register.
  437. @return The value written back to the PCI configuration register.
  438. **/
  439. UINT16
  440. EFIAPI
  441. PciExpressOr16 (
  442. IN UINTN Address,
  443. IN UINT16 OrData
  444. )
  445. {
  446. ASSERT_INVALID_PCI_ADDRESS (Address);
  447. return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);
  448. }
  449. /**
  450. Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
  451. value.
  452. Reads the 16-bit PCI configuration register specified by Address, performs a
  453. bitwise AND between the read result and the value specified by AndData, and
  454. writes the result to the 16-bit PCI configuration register specified by
  455. Address. The value written to the PCI configuration register is returned.
  456. This function must guarantee that all PCI read and write operations are
  457. serialized.
  458. If Address > 0x0FFFFFFF, then ASSERT().
  459. If Address is not aligned on a 16-bit boundary, then ASSERT().
  460. @param Address The address that encodes the PCI Bus, Device, Function and
  461. Register.
  462. @param AndData The value to AND with the PCI configuration register.
  463. @return The value written back to the PCI configuration register.
  464. **/
  465. UINT16
  466. EFIAPI
  467. PciExpressAnd16 (
  468. IN UINTN Address,
  469. IN UINT16 AndData
  470. )
  471. {
  472. ASSERT_INVALID_PCI_ADDRESS (Address);
  473. return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);
  474. }
  475. /**
  476. Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
  477. value, followed a bitwise OR with another 16-bit value.
  478. Reads the 16-bit PCI configuration register specified by Address, performs a
  479. bitwise AND between the read result and the value specified by AndData,
  480. performs a bitwise OR between the result of the AND operation and
  481. the value specified by OrData, and writes the result to the 16-bit PCI
  482. configuration register specified by Address. The value written to the PCI
  483. configuration register is returned. This function must guarantee that all PCI
  484. read and write operations are serialized.
  485. If Address > 0x0FFFFFFF, then ASSERT().
  486. If Address is not aligned on a 16-bit boundary, then ASSERT().
  487. @param Address The address that encodes the PCI Bus, Device, Function and
  488. Register.
  489. @param AndData The value to AND with the PCI configuration register.
  490. @param OrData The value to OR with the result of the AND operation.
  491. @return The value written back to the PCI configuration register.
  492. **/
  493. UINT16
  494. EFIAPI
  495. PciExpressAndThenOr16 (
  496. IN UINTN Address,
  497. IN UINT16 AndData,
  498. IN UINT16 OrData
  499. )
  500. {
  501. ASSERT_INVALID_PCI_ADDRESS (Address);
  502. return MmioAndThenOr16 (
  503. (UINTN) GetPciExpressBaseAddress () + Address,
  504. AndData,
  505. OrData
  506. );
  507. }
  508. /**
  509. Reads a bit field of a PCI configuration register.
  510. Reads the bit field in a 16-bit PCI configuration register. The bit field is
  511. specified by the StartBit and the EndBit. The value of the bit field is
  512. returned.
  513. If Address > 0x0FFFFFFF, then ASSERT().
  514. If Address is not aligned on a 16-bit boundary, then ASSERT().
  515. If StartBit is greater than 15, then ASSERT().
  516. If EndBit is greater than 15, then ASSERT().
  517. If EndBit is less than StartBit, then ASSERT().
  518. @param Address The PCI configuration register to read.
  519. @param StartBit The ordinal of the least significant bit in the bit field.
  520. Range 0..15.
  521. @param EndBit The ordinal of the most significant bit in the bit field.
  522. Range 0..15.
  523. @return The value of the bit field read from the PCI configuration register.
  524. **/
  525. UINT16
  526. EFIAPI
  527. PciExpressBitFieldRead16 (
  528. IN UINTN Address,
  529. IN UINTN StartBit,
  530. IN UINTN EndBit
  531. )
  532. {
  533. ASSERT_INVALID_PCI_ADDRESS (Address);
  534. return MmioBitFieldRead16 (
  535. (UINTN) GetPciExpressBaseAddress () + Address,
  536. StartBit,
  537. EndBit
  538. );
  539. }
  540. /**
  541. Writes a bit field to a PCI configuration register.
  542. Writes Value to the bit field of the PCI configuration register. The bit
  543. field is specified by the StartBit and the EndBit. All other bits in the
  544. destination PCI configuration register are preserved. The new value of the
  545. 16-bit register is returned.
  546. If Address > 0x0FFFFFFF, then ASSERT().
  547. If Address is not aligned on a 16-bit boundary, then ASSERT().
  548. If StartBit is greater than 15, then ASSERT().
  549. If EndBit is greater than 15, then ASSERT().
  550. If EndBit is less than StartBit, then ASSERT().
  551. If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
  552. @param Address The PCI configuration register to write.
  553. @param StartBit The ordinal of the least significant bit in the bit field.
  554. Range 0..15.
  555. @param EndBit The ordinal of the most significant bit in the bit field.
  556. Range 0..15.
  557. @param Value The new value of the bit field.
  558. @return The value written back to the PCI configuration register.
  559. **/
  560. UINT16
  561. EFIAPI
  562. PciExpressBitFieldWrite16 (
  563. IN UINTN Address,
  564. IN UINTN StartBit,
  565. IN UINTN EndBit,
  566. IN UINT16 Value
  567. )
  568. {
  569. ASSERT_INVALID_PCI_ADDRESS (Address);
  570. return MmioBitFieldWrite16 (
  571. (UINTN) GetPciExpressBaseAddress () + Address,
  572. StartBit,
  573. EndBit,
  574. Value
  575. );
  576. }
  577. /**
  578. Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
  579. writes the result back to the bit field in the 16-bit port.
  580. Reads the 16-bit PCI configuration register specified by Address, performs a
  581. bitwise OR between the read result and the value specified by
  582. OrData, and writes the result to the 16-bit PCI configuration register
  583. specified by Address. The value written to the PCI configuration register is
  584. returned. This function must guarantee that all PCI read and write operations
  585. are serialized. Extra left bits in OrData are stripped.
  586. If Address > 0x0FFFFFFF, then ASSERT().
  587. If Address is not aligned on a 16-bit boundary, then ASSERT().
  588. If StartBit is greater than 15, then ASSERT().
  589. If EndBit is greater than 15, then ASSERT().
  590. If EndBit is less than StartBit, then ASSERT().
  591. If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
  592. @param Address The PCI configuration register to write.
  593. @param StartBit The ordinal of the least significant bit in the bit field.
  594. Range 0..15.
  595. @param EndBit The ordinal of the most significant bit in the bit field.
  596. Range 0..15.
  597. @param OrData The value to OR with the PCI configuration register.
  598. @return The value written back to the PCI configuration register.
  599. **/
  600. UINT16
  601. EFIAPI
  602. PciExpressBitFieldOr16 (
  603. IN UINTN Address,
  604. IN UINTN StartBit,
  605. IN UINTN EndBit,
  606. IN UINT16 OrData
  607. )
  608. {
  609. ASSERT_INVALID_PCI_ADDRESS (Address);
  610. return MmioBitFieldOr16 (
  611. (UINTN) GetPciExpressBaseAddress () + Address,
  612. StartBit,
  613. EndBit,
  614. OrData
  615. );
  616. }
  617. /**
  618. Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
  619. AND, and writes the result back to the bit field in the 16-bit register.
  620. Reads the 16-bit PCI configuration register specified by Address, performs a
  621. bitwise AND between the read result and the value specified by AndData, and
  622. writes the result to the 16-bit PCI configuration register specified by
  623. Address. The value written to the PCI configuration register is returned.
  624. This function must guarantee that all PCI read and write operations are
  625. serialized. Extra left bits in AndData are stripped.
  626. If Address > 0x0FFFFFFF, then ASSERT().
  627. If Address is not aligned on a 16-bit boundary, then ASSERT().
  628. If StartBit is greater than 15, then ASSERT().
  629. If EndBit is greater than 15, then ASSERT().
  630. If EndBit is less than StartBit, then ASSERT().
  631. If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
  632. @param Address The PCI configuration register to write.
  633. @param StartBit The ordinal of the least significant bit in the bit field.
  634. Range 0..15.
  635. @param EndBit The ordinal of the most significant bit in the bit field.
  636. Range 0..15.
  637. @param AndData The value to AND with the PCI configuration register.
  638. @return The value written back to the PCI configuration register.
  639. **/
  640. UINT16
  641. EFIAPI
  642. PciExpressBitFieldAnd16 (
  643. IN UINTN Address,
  644. IN UINTN StartBit,
  645. IN UINTN EndBit,
  646. IN UINT16 AndData
  647. )
  648. {
  649. ASSERT_INVALID_PCI_ADDRESS (Address);
  650. return MmioBitFieldAnd16 (
  651. (UINTN) GetPciExpressBaseAddress () + Address,
  652. StartBit,
  653. EndBit,
  654. AndData
  655. );
  656. }
  657. /**
  658. Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
  659. bitwise OR, and writes the result back to the bit field in the
  660. 16-bit port.
  661. Reads the 16-bit PCI configuration register specified by Address, performs a
  662. bitwise AND followed by a bitwise OR between the read result and
  663. the value specified by AndData, and writes the result to the 16-bit PCI
  664. configuration register specified by Address. The value written to the PCI
  665. configuration register is returned. This function must guarantee that all PCI
  666. read and write operations are serialized. Extra left bits in both AndData and
  667. OrData are stripped.
  668. If Address > 0x0FFFFFFF, then ASSERT().
  669. If Address is not aligned on a 16-bit boundary, then ASSERT().
  670. If StartBit is greater than 15, then ASSERT().
  671. If EndBit is greater than 15, then ASSERT().
  672. If EndBit is less than StartBit, then ASSERT().
  673. If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
  674. If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
  675. @param Address The PCI configuration register to write.
  676. @param StartBit The ordinal of the least significant bit in the bit field.
  677. Range 0..15.
  678. @param EndBit The ordinal of the most significant bit in the bit field.
  679. Range 0..15.
  680. @param AndData The value to AND with the PCI configuration register.
  681. @param OrData The value to OR with the result of the AND operation.
  682. @return The value written back to the PCI configuration register.
  683. **/
  684. UINT16
  685. EFIAPI
  686. PciExpressBitFieldAndThenOr16 (
  687. IN UINTN Address,
  688. IN UINTN StartBit,
  689. IN UINTN EndBit,
  690. IN UINT16 AndData,
  691. IN UINT16 OrData
  692. )
  693. {
  694. ASSERT_INVALID_PCI_ADDRESS (Address);
  695. return MmioBitFieldAndThenOr16 (
  696. (UINTN) GetPciExpressBaseAddress () + Address,
  697. StartBit,
  698. EndBit,
  699. AndData,
  700. OrData
  701. );
  702. }
  703. /**
  704. Reads a 32-bit PCI configuration register.
  705. Reads and returns the 32-bit PCI configuration register specified by Address.
  706. This function must guarantee that all PCI read and write operations are
  707. serialized.
  708. If Address > 0x0FFFFFFF, then ASSERT().
  709. If Address is not aligned on a 32-bit boundary, then ASSERT().
  710. @param Address The address that encodes the PCI Bus, Device, Function and
  711. Register.
  712. @return The read value from the PCI configuration register.
  713. **/
  714. UINT32
  715. EFIAPI
  716. PciExpressRead32 (
  717. IN UINTN Address
  718. )
  719. {
  720. ASSERT_INVALID_PCI_ADDRESS (Address);
  721. return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address);
  722. }
  723. /**
  724. Writes a 32-bit PCI configuration register.
  725. Writes the 32-bit PCI configuration register specified by Address with the
  726. value specified by Value. Value is returned. This function must guarantee
  727. that all PCI read and write operations are serialized.
  728. If Address > 0x0FFFFFFF, then ASSERT().
  729. If Address is not aligned on a 32-bit boundary, then ASSERT().
  730. @param Address The address that encodes the PCI Bus, Device, Function and
  731. Register.
  732. @param Value The value to write.
  733. @return The value written to the PCI configuration register.
  734. **/
  735. UINT32
  736. EFIAPI
  737. PciExpressWrite32 (
  738. IN UINTN Address,
  739. IN UINT32 Value
  740. )
  741. {
  742. ASSERT_INVALID_PCI_ADDRESS (Address);
  743. return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value);
  744. }
  745. /**
  746. Performs a bitwise OR of a 32-bit PCI configuration register with
  747. a 32-bit value.
  748. Reads the 32-bit PCI configuration register specified by Address, performs a
  749. bitwise OR between the read result and the value specified by
  750. OrData, and writes the result to the 32-bit PCI configuration register
  751. specified by Address. The value written to the PCI configuration register is
  752. returned. This function must guarantee that all PCI read and write operations
  753. are serialized.
  754. If Address > 0x0FFFFFFF, then ASSERT().
  755. If Address is not aligned on a 32-bit boundary, then ASSERT().
  756. @param Address The address that encodes the PCI Bus, Device, Function and
  757. Register.
  758. @param OrData The value to OR with the PCI configuration register.
  759. @return The value written back to the PCI configuration register.
  760. **/
  761. UINT32
  762. EFIAPI
  763. PciExpressOr32 (
  764. IN UINTN Address,
  765. IN UINT32 OrData
  766. )
  767. {
  768. ASSERT_INVALID_PCI_ADDRESS (Address);
  769. return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);
  770. }
  771. /**
  772. Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
  773. value.
  774. Reads the 32-bit PCI configuration register specified by Address, performs a
  775. bitwise AND between the read result and the value specified by AndData, and
  776. writes the result to the 32-bit PCI configuration register specified by
  777. Address. The value written to the PCI configuration register is returned.
  778. This function must guarantee that all PCI read and write operations are
  779. serialized.
  780. If Address > 0x0FFFFFFF, then ASSERT().
  781. If Address is not aligned on a 32-bit boundary, then ASSERT().
  782. @param Address The address that encodes the PCI Bus, Device, Function and
  783. Register.
  784. @param AndData The value to AND with the PCI configuration register.
  785. @return The value written back to the PCI configuration register.
  786. **/
  787. UINT32
  788. EFIAPI
  789. PciExpressAnd32 (
  790. IN UINTN Address,
  791. IN UINT32 AndData
  792. )
  793. {
  794. ASSERT_INVALID_PCI_ADDRESS (Address);
  795. return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);
  796. }
  797. /**
  798. Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
  799. value, followed a bitwise OR with another 32-bit value.
  800. Reads the 32-bit PCI configuration register specified by Address, performs a
  801. bitwise AND between the read result and the value specified by AndData,
  802. performs a bitwise OR between the result of the AND operation and
  803. the value specified by OrData, and writes the result to the 32-bit PCI
  804. configuration register specified by Address. The value written to the PCI
  805. configuration register is returned. This function must guarantee that all PCI
  806. read and write operations are serialized.
  807. If Address > 0x0FFFFFFF, then ASSERT().
  808. If Address is not aligned on a 32-bit boundary, then ASSERT().
  809. @param Address The address that encodes the PCI Bus, Device, Function and
  810. Register.
  811. @param AndData The value to AND with the PCI configuration register.
  812. @param OrData The value to OR with the result of the AND operation.
  813. @return The value written back to the PCI configuration register.
  814. **/
  815. UINT32
  816. EFIAPI
  817. PciExpressAndThenOr32 (
  818. IN UINTN Address,
  819. IN UINT32 AndData,
  820. IN UINT32 OrData
  821. )
  822. {
  823. ASSERT_INVALID_PCI_ADDRESS (Address);
  824. return MmioAndThenOr32 (
  825. (UINTN) GetPciExpressBaseAddress () + Address,
  826. AndData,
  827. OrData
  828. );
  829. }
  830. /**
  831. Reads a bit field of a PCI configuration register.
  832. Reads the bit field in a 32-bit PCI configuration register. The bit field is
  833. specified by the StartBit and the EndBit. The value of the bit field is
  834. returned.
  835. If Address > 0x0FFFFFFF, then ASSERT().
  836. If Address is not aligned on a 32-bit boundary, then ASSERT().
  837. If StartBit is greater than 31, then ASSERT().
  838. If EndBit is greater than 31, then ASSERT().
  839. If EndBit is less than StartBit, then ASSERT().
  840. @param Address The PCI configuration register to read.
  841. @param StartBit The ordinal of the least significant bit in the bit field.
  842. Range 0..31.
  843. @param EndBit The ordinal of the most significant bit in the bit field.
  844. Range 0..31.
  845. @return The value of the bit field read from the PCI configuration register.
  846. **/
  847. UINT32
  848. EFIAPI
  849. PciExpressBitFieldRead32 (
  850. IN UINTN Address,
  851. IN UINTN StartBit,
  852. IN UINTN EndBit
  853. )
  854. {
  855. ASSERT_INVALID_PCI_ADDRESS (Address);
  856. return MmioBitFieldRead32 (
  857. (UINTN) GetPciExpressBaseAddress () + Address,
  858. StartBit,
  859. EndBit
  860. );
  861. }
  862. /**
  863. Writes a bit field to a PCI configuration register.
  864. Writes Value to the bit field of the PCI configuration register. The bit
  865. field is specified by the StartBit and the EndBit. All other bits in the
  866. destination PCI configuration register are preserved. The new value of the
  867. 32-bit register is returned.
  868. If Address > 0x0FFFFFFF, then ASSERT().
  869. If Address is not aligned on a 32-bit boundary, then ASSERT().
  870. If StartBit is greater than 31, then ASSERT().
  871. If EndBit is greater than 31, then ASSERT().
  872. If EndBit is less than StartBit, then ASSERT().
  873. If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
  874. @param Address The PCI configuration register to write.
  875. @param StartBit The ordinal of the least significant bit in the bit field.
  876. Range 0..31.
  877. @param EndBit The ordinal of the most significant bit in the bit field.
  878. Range 0..31.
  879. @param Value The new value of the bit field.
  880. @return The value written back to the PCI configuration register.
  881. **/
  882. UINT32
  883. EFIAPI
  884. PciExpressBitFieldWrite32 (
  885. IN UINTN Address,
  886. IN UINTN StartBit,
  887. IN UINTN EndBit,
  888. IN UINT32 Value
  889. )
  890. {
  891. ASSERT_INVALID_PCI_ADDRESS (Address);
  892. return MmioBitFieldWrite32 (
  893. (UINTN) GetPciExpressBaseAddress () + Address,
  894. StartBit,
  895. EndBit,
  896. Value
  897. );
  898. }
  899. /**
  900. Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
  901. writes the result back to the bit field in the 32-bit port.
  902. Reads the 32-bit PCI configuration register specified by Address, performs a
  903. bitwise OR between the read result and the value specified by
  904. OrData, and writes the result to the 32-bit PCI configuration register
  905. specified by Address. The value written to the PCI configuration register is
  906. returned. This function must guarantee that all PCI read and write operations
  907. are serialized. Extra left bits in OrData are stripped.
  908. If Address > 0x0FFFFFFF, then ASSERT().
  909. If Address is not aligned on a 32-bit boundary, then ASSERT().
  910. If StartBit is greater than 31, then ASSERT().
  911. If EndBit is greater than 31, then ASSERT().
  912. If EndBit is less than StartBit, then ASSERT().
  913. If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
  914. @param Address The PCI configuration register to write.
  915. @param StartBit The ordinal of the least significant bit in the bit field.
  916. Range 0..31.
  917. @param EndBit The ordinal of the most significant bit in the bit field.
  918. Range 0..31.
  919. @param OrData The value to OR with the PCI configuration register.
  920. @return The value written back to the PCI configuration register.
  921. **/
  922. UINT32
  923. EFIAPI
  924. PciExpressBitFieldOr32 (
  925. IN UINTN Address,
  926. IN UINTN StartBit,
  927. IN UINTN EndBit,
  928. IN UINT32 OrData
  929. )
  930. {
  931. ASSERT_INVALID_PCI_ADDRESS (Address);
  932. return MmioBitFieldOr32 (
  933. (UINTN) GetPciExpressBaseAddress () + Address,
  934. StartBit,
  935. EndBit,
  936. OrData
  937. );
  938. }
  939. /**
  940. Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
  941. AND, and writes the result back to the bit field in the 32-bit register.
  942. Reads the 32-bit PCI configuration register specified by Address, performs a
  943. bitwise AND between the read result and the value specified by AndData, and
  944. writes the result to the 32-bit PCI configuration register specified by
  945. Address. The value written to the PCI configuration register is returned.
  946. This function must guarantee that all PCI read and write operations are
  947. serialized. Extra left bits in AndData are stripped.
  948. If Address > 0x0FFFFFFF, then ASSERT().
  949. If Address is not aligned on a 32-bit boundary, then ASSERT().
  950. If StartBit is greater than 31, then ASSERT().
  951. If EndBit is greater than 31, then ASSERT().
  952. If EndBit is less than StartBit, then ASSERT().
  953. If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
  954. @param Address The PCI configuration register to write.
  955. @param StartBit The ordinal of the least significant bit in the bit field.
  956. Range 0..31.
  957. @param EndBit The ordinal of the most significant bit in the bit field.
  958. Range 0..31.
  959. @param AndData The value to AND with the PCI configuration register.
  960. @return The value written back to the PCI configuration register.
  961. **/
  962. UINT32
  963. EFIAPI
  964. PciExpressBitFieldAnd32 (
  965. IN UINTN Address,
  966. IN UINTN StartBit,
  967. IN UINTN EndBit,
  968. IN UINT32 AndData
  969. )
  970. {
  971. ASSERT_INVALID_PCI_ADDRESS (Address);
  972. return MmioBitFieldAnd32 (
  973. (UINTN) GetPciExpressBaseAddress () + Address,
  974. StartBit,
  975. EndBit,
  976. AndData
  977. );
  978. }
  979. /**
  980. Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
  981. bitwise OR, and writes the result back to the bit field in the
  982. 32-bit port.
  983. Reads the 32-bit PCI configuration register specified by Address, performs a
  984. bitwise AND followed by a bitwise OR between the read result and
  985. the value specified by AndData, and writes the result to the 32-bit PCI
  986. configuration register specified by Address. The value written to the PCI
  987. configuration register is returned. This function must guarantee that all PCI
  988. read and write operations are serialized. Extra left bits in both AndData and
  989. OrData are stripped.
  990. If Address > 0x0FFFFFFF, then ASSERT().
  991. If Address is not aligned on a 32-bit boundary, then ASSERT().
  992. If StartBit is greater than 31, then ASSERT().
  993. If EndBit is greater than 31, then ASSERT().
  994. If EndBit is less than StartBit, then ASSERT().
  995. If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
  996. If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
  997. @param Address The PCI configuration register to write.
  998. @param StartBit The ordinal of the least significant bit in the bit field.
  999. Range 0..31.
  1000. @param EndBit The ordinal of the most significant bit in the bit field.
  1001. Range 0..31.
  1002. @param AndData The value to AND with the PCI configuration register.
  1003. @param OrData The value to OR with the result of the AND operation.
  1004. @return The value written back to the PCI configuration register.
  1005. **/
  1006. UINT32
  1007. EFIAPI
  1008. PciExpressBitFieldAndThenOr32 (
  1009. IN UINTN Address,
  1010. IN UINTN StartBit,
  1011. IN UINTN EndBit,
  1012. IN UINT32 AndData,
  1013. IN UINT32 OrData
  1014. )
  1015. {
  1016. ASSERT_INVALID_PCI_ADDRESS (Address);
  1017. return MmioBitFieldAndThenOr32 (
  1018. (UINTN) GetPciExpressBaseAddress () + Address,
  1019. StartBit,
  1020. EndBit,
  1021. AndData,
  1022. OrData
  1023. );
  1024. }
  1025. /**
  1026. Reads a range of PCI configuration registers into a caller supplied buffer.
  1027. Reads the range of PCI configuration registers specified by StartAddress and
  1028. Size into the buffer specified by Buffer. This function only allows the PCI
  1029. configuration registers from a single PCI function to be read. Size is
  1030. returned. When possible 32-bit PCI configuration read cycles are used to read
  1031. from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
  1032. and 16-bit PCI configuration read cycles may be used at the beginning and the
  1033. end of the range.
  1034. If StartAddress > 0x0FFFFFFF, then ASSERT().
  1035. If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
  1036. If Size > 0 and Buffer is NULL, then ASSERT().
  1037. @param StartAddress The starting address that encodes the PCI Bus, Device,
  1038. Function and Register.
  1039. @param Size The size in bytes of the transfer.
  1040. @param Buffer The pointer to a buffer receiving the data read.
  1041. @return Size read data from StartAddress.
  1042. **/
  1043. UINTN
  1044. EFIAPI
  1045. PciExpressReadBuffer (
  1046. IN UINTN StartAddress,
  1047. IN UINTN Size,
  1048. OUT VOID *Buffer
  1049. )
  1050. {
  1051. UINTN ReturnValue;
  1052. ASSERT_INVALID_PCI_ADDRESS (StartAddress);
  1053. ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
  1054. if (Size == 0) {
  1055. return Size;
  1056. }
  1057. ASSERT (Buffer != NULL);
  1058. //
  1059. // Save Size for return
  1060. //
  1061. ReturnValue = Size;
  1062. if ((StartAddress & 1) != 0) {
  1063. //
  1064. // Read a byte if StartAddress is byte aligned
  1065. //
  1066. *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
  1067. StartAddress += sizeof (UINT8);
  1068. Size -= sizeof (UINT8);
  1069. Buffer = (UINT8*)Buffer + 1;
  1070. }
  1071. if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
  1072. //
  1073. // Read a word if StartAddress is word aligned
  1074. //
  1075. WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
  1076. StartAddress += sizeof (UINT16);
  1077. Size -= sizeof (UINT16);
  1078. Buffer = (UINT16*)Buffer + 1;
  1079. }
  1080. while (Size >= sizeof (UINT32)) {
  1081. //
  1082. // Read as many double words as possible
  1083. //
  1084. WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));
  1085. StartAddress += sizeof (UINT32);
  1086. Size -= sizeof (UINT32);
  1087. Buffer = (UINT32*)Buffer + 1;
  1088. }
  1089. if (Size >= sizeof (UINT16)) {
  1090. //
  1091. // Read the last remaining word if exist
  1092. //
  1093. WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
  1094. StartAddress += sizeof (UINT16);
  1095. Size -= sizeof (UINT16);
  1096. Buffer = (UINT16*)Buffer + 1;
  1097. }
  1098. if (Size >= sizeof (UINT8)) {
  1099. //
  1100. // Read the last remaining byte if exist
  1101. //
  1102. *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
  1103. }
  1104. return ReturnValue;
  1105. }
  1106. /**
  1107. Copies the data in a caller supplied buffer to a specified range of PCI
  1108. configuration space.
  1109. Writes the range of PCI configuration registers specified by StartAddress and
  1110. Size from the buffer specified by Buffer. This function only allows the PCI
  1111. configuration registers from a single PCI function to be written. Size is
  1112. returned. When possible 32-bit PCI configuration write cycles are used to
  1113. write from StartAddress to StartAddress + Size. Due to alignment restrictions,
  1114. 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
  1115. and the end of the range.
  1116. If StartAddress > 0x0FFFFFFF, then ASSERT().
  1117. If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
  1118. If Size > 0 and Buffer is NULL, then ASSERT().
  1119. @param StartAddress The starting address that encodes the PCI Bus, Device,
  1120. Function and Register.
  1121. @param Size The size in bytes of the transfer.
  1122. @param Buffer The pointer to a buffer containing the data to write.
  1123. @return Size written to StartAddress.
  1124. **/
  1125. UINTN
  1126. EFIAPI
  1127. PciExpressWriteBuffer (
  1128. IN UINTN StartAddress,
  1129. IN UINTN Size,
  1130. IN VOID *Buffer
  1131. )
  1132. {
  1133. UINTN ReturnValue;
  1134. ASSERT_INVALID_PCI_ADDRESS (StartAddress);
  1135. ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
  1136. if (Size == 0) {
  1137. return 0;
  1138. }
  1139. ASSERT (Buffer != NULL);
  1140. //
  1141. // Save Size for return
  1142. //
  1143. ReturnValue = Size;
  1144. if ((StartAddress & 1) != 0) {
  1145. //
  1146. // Write a byte if StartAddress is byte aligned
  1147. //
  1148. PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
  1149. StartAddress += sizeof (UINT8);
  1150. Size -= sizeof (UINT8);
  1151. Buffer = (UINT8*)Buffer + 1;
  1152. }
  1153. if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
  1154. //
  1155. // Write a word if StartAddress is word aligned
  1156. //
  1157. PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
  1158. StartAddress += sizeof (UINT16);
  1159. Size -= sizeof (UINT16);
  1160. Buffer = (UINT16*)Buffer + 1;
  1161. }
  1162. while (Size >= sizeof (UINT32)) {
  1163. //
  1164. // Write as many double words as possible
  1165. //
  1166. PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));
  1167. StartAddress += sizeof (UINT32);
  1168. Size -= sizeof (UINT32);
  1169. Buffer = (UINT32*)Buffer + 1;
  1170. }
  1171. if (Size >= sizeof (UINT16)) {
  1172. //
  1173. // Write the last remaining word if exist
  1174. //
  1175. PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
  1176. StartAddress += sizeof (UINT16);
  1177. Size -= sizeof (UINT16);
  1178. Buffer = (UINT16*)Buffer + 1;
  1179. }
  1180. if (Size >= sizeof (UINT8)) {
  1181. //
  1182. // Write the last remaining byte if exist
  1183. //
  1184. PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
  1185. }
  1186. return ReturnValue;
  1187. }