RiscVVirt.fdf.inc 1.5 KB

1234567891011121314151617181920212223242526272829303132333435363738394041
  1. ## @file
  2. # Definitions of Flash definition file on RiscVVirt RISC-V platform
  3. #
  4. # Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
  5. # Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
  6. #
  7. # SPDX-License-Identifier: BSD-2-Clause-Patent
  8. #
  9. ##
  10. [Defines]
  11. DEFINE BLOCK_SIZE = 0x1000
  12. DEFINE PFLASH1_BASE = 0x22000000
  13. DEFINE FW_BASE_ADDRESS = $(PFLASH1_BASE)
  14. DEFINE FW_SIZE = 0x00800000
  15. DEFINE FW_BLOCKS = 0x800
  16. DEFINE CODE_BASE_ADDRESS = $(FW_BASE_ADDRESS)
  17. DEFINE CODE_SIZE = 0x00740000
  18. DEFINE CODE_BLOCKS = 0x740
  19. DEFINE VARS_SIZE = 0x000C0000
  20. DEFINE VARS_BLOCK_SIZE = 0x40000
  21. DEFINE VARS_BLOCKS = 0x3
  22. #
  23. # EFI Variable memory region.
  24. # The total size of EFI Variable FD must include
  25. # all of sub regions of EFI Variable
  26. #
  27. DEFINE VARS_OFFSET = $(CODE_SIZE)
  28. DEFINE VARS_LIVE_SIZE = 0x00040000
  29. DEFINE VARS_FTW_WORKING_OFFSET = $(VARS_OFFSET) + $(VARS_LIVE_SIZE)
  30. DEFINE VARS_FTW_WORKING_SIZE = 0x00040000
  31. DEFINE VARS_FTW_SPARE_OFFSET = $(VARS_FTW_WORKING_OFFSET) + $(VARS_FTW_WORKING_SIZE)
  32. DEFINE VARS_FTW_SPARE_SIZE = 0x00040000
  33. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency = 10000000
  34. SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase = 0x83FF0000
  35. SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize = 0x00010000