SataSiI3132.h 8.6 KB

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  1. /** @file
  2. * Header containing the structure specific to the Silicon Image I3132 Sata PCI card
  3. *
  4. * Copyright (c) 2011-2015, ARM Limited. All rights reserved.
  5. *
  6. * SPDX-License-Identifier: BSD-2-Clause-Patent
  7. *
  8. **/
  9. #ifndef __SATASII3132_H
  10. #define __SATASII3132_H
  11. #include <PiDxe.h>
  12. #include <Protocol/AtaPassThru.h>
  13. #include <Protocol/PciIo.h>
  14. #include <Library/UefiLib.h>
  15. #include <Library/DebugLib.h>
  16. #include <Library/PcdLib.h>
  17. #include <Library/BaseMemoryLib.h>
  18. #include <Library/UefiBootServicesTableLib.h>
  19. #include <IndustryStandard/Pci.h>
  20. #define SATA_SII3132_DEVICE_ID 0x3132
  21. #define SATA_SII3132_VENDOR_ID 0x1095
  22. #define SII3132_PORT_SIGNATURE_PMP 0x96690101
  23. #define SII3132_PORT_SIGNATURE_ATAPI 0xEB140101
  24. #define SII3132_PORT_SIGNATURE_ATA 0x00000101
  25. /*
  26. * Silicon Image SiI3132 Registers
  27. */
  28. #define SII3132_GLOBAL_CONTROL_REG 0x40
  29. #define SII3132_GLOBAL_FLASHADDR_REG 0x70
  30. #define SII3132_PORT_STATUS_REG 0x1000
  31. #define SII3132_PORT_CONTROLSET_REG 0x1000
  32. #define SII3132_PORT_CONTROLCLEAR_REG 0x1004
  33. #define SII3132_PORT_INTSTATUS_REG 0x1008
  34. #define SII3132_PORT_ENABLEINT_REG 0x1010
  35. #define SII3132_PORT_INTCLEAR_REG 0x1014
  36. #define SII3132_PORT_32BITACTIVADDR_REG 0x101C
  37. #define SII3132_PORT_CMDEXECFIFO_REG 0x1020
  38. #define SII3132_PORT_CMDERROR_REG 0x1024
  39. #define SII3132_PORT_ERRCOUNTDECODE 0x1040
  40. #define SII3132_PORT_ERRCOUNTCRC 0x1044
  41. #define SII3132_PORT_ERRCOUNTHANDSHAKE 0x1048
  42. #define SII3132_PORT_SLOTSTATUS_REG 0x1800
  43. #define SII3132_PORT_CMDACTIV_REG 0x1C00
  44. #define SII3132_PORT_SSTATUS_REG 0x1F04
  45. #define SII3132_PORT_CONTROL_RESET (1 << 0)
  46. #define SII3132_PORT_DEVICE_RESET (1 << 1)
  47. #define SII3132_PORT_CONTROL_INT (1 << 2)
  48. #define SII3132_PORT_CONTROL_32BITACTIVATION (1 << 10)
  49. #define SII3132_PORT_STATUS_PORTREADY 0x80000000
  50. #define SII3132_PORT_INT_CMDCOMPL (1 << 0)
  51. #define SII3132_PORT_INT_CMDERR (1 << 1)
  52. #define SII3132_PORT_INT_PORTRDY (1 << 2)
  53. #define SATA_SII3132_MAXPORT 2
  54. #define PRB_CTRL_ATA 0x0
  55. #define PRB_CTRL_PROT_OVERRIDE 0x1
  56. #define PRB_CTRL_RESTRANSMIT 0x2
  57. #define PRB_CTRL_EXT_CMD 0x4
  58. #define PRB_CTRL_RCV 0x8
  59. #define PRB_CTRL_PKT_READ 0x10
  60. #define PRB_CTRL_PKT_WRITE 0x20
  61. #define PRB_CTRL_INT_MASK 0x40
  62. #define PRB_CTRL_SRST 0x80
  63. #define PRB_PROT_PACKET 0x01
  64. #define PRB_PROT_LEGACY_QUEUE 0x02
  65. #define PRB_PROT_NATIVE_QUEUE 0x04
  66. #define PRB_PROT_READ 0x08
  67. #define PRB_PROT_WRITE 0x10
  68. #define PRB_PROT_TRANSPARENT 0x20
  69. #define SGE_XCF (1 << 28)
  70. #define SGE_DRD (1 << 29)
  71. #define SGE_LNK (1 << 30)
  72. #define SGE_TRM 0x80000000
  73. typedef struct _SATA_SI3132_SGE {
  74. UINT32 DataAddressLow;
  75. UINT32 DataAddressHigh;
  76. UINT32 DataCount;
  77. UINT32 Attributes;
  78. } SATA_SI3132_SGE;
  79. typedef struct _SATA_SI3132_FIS {
  80. UINT8 FisType;
  81. UINT8 Control;
  82. UINT8 Command;
  83. UINT8 Features;
  84. UINT8 Fis[5 * 4];
  85. } SATA_SI3132_FIS;
  86. typedef struct _SATA_SI3132_PRB {
  87. UINT16 Control;
  88. UINT16 ProtocolOverride;
  89. UINT32 RecTransCount;
  90. SATA_SI3132_FIS Fis;
  91. SATA_SI3132_SGE Sge[2];
  92. } SATA_SI3132_PRB;
  93. typedef struct _SATA_SI3132_DEVICE {
  94. LIST_ENTRY Link; // This attribute must be the first entry of this structure (to avoid pointer computation)
  95. UINTN Index;
  96. struct _SATA_SI3132_PORT *Port; //Parent Port
  97. UINT32 BlockSize;
  98. } SATA_SI3132_DEVICE;
  99. typedef struct _SATA_SI3132_PORT {
  100. UINTN Index;
  101. UINTN RegBase;
  102. struct _SATA_SI3132_INSTANCE *Instance;
  103. //TODO: Support Port multiplier
  104. LIST_ENTRY Devices;
  105. SATA_SI3132_PRB* HostPRB;
  106. EFI_PHYSICAL_ADDRESS PhysAddrHostPRB;
  107. VOID* PciAllocMappingPRB;
  108. } SATA_SI3132_PORT;
  109. typedef struct _SATA_SI3132_INSTANCE {
  110. UINTN Signature;
  111. SATA_SI3132_PORT Ports[SATA_SII3132_MAXPORT];
  112. EFI_ATA_PASS_THRU_PROTOCOL AtaPassThruProtocol;
  113. EFI_PCI_IO_PROTOCOL *PciIo;
  114. } SATA_SI3132_INSTANCE;
  115. #define SATA_SII3132_SIGNATURE SIGNATURE_32('s', 'i', '3', '2')
  116. #define INSTANCE_FROM_ATAPASSTHRU_THIS(a) CR(a, SATA_SI3132_INSTANCE, AtaPassThruProtocol, SATA_SII3132_SIGNATURE)
  117. #define SATA_GLOBAL_READ32(Offset, Value) PciIo->Mem.Read (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, Value)
  118. #define SATA_GLOBAL_WRITE32(Offset, Value) { UINT32 Value32 = Value; PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, &Value32); }
  119. #define SATA_PORT_READ32(Offset, Value) PciIo->Mem.Read (PciIo, EfiPciIoWidthUint32, 1, Offset, 1, Value)
  120. #define SATA_PORT_WRITE32(Offset, Value) { UINT32 Value32 = Value; PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 1, Offset, 1, &Value32); }
  121. #define SATA_TRACE(txt) DEBUG((EFI_D_VERBOSE, "ARM_SATA: " txt "\n"))
  122. extern EFI_COMPONENT_NAME_PROTOCOL gSataSiI3132ComponentName;
  123. extern EFI_COMPONENT_NAME2_PROTOCOL gSataSiI3132ComponentName2;
  124. /*
  125. * Component Name Protocol Functions
  126. */
  127. EFI_STATUS
  128. EFIAPI
  129. SataSiI3132ComponentNameGetDriverName (
  130. IN EFI_COMPONENT_NAME_PROTOCOL *This,
  131. IN CHAR8 *Language,
  132. OUT CHAR16 **DriverName
  133. );
  134. EFI_STATUS
  135. EFIAPI
  136. SataSiI3132ComponentNameGetControllerName (
  137. IN EFI_COMPONENT_NAME_PROTOCOL *This,
  138. IN EFI_HANDLE ControllerHandle,
  139. IN EFI_HANDLE ChildHandle OPTIONAL,
  140. IN CHAR8 *Language,
  141. OUT CHAR16 **ControllerName
  142. );
  143. EFI_STATUS SiI3132HwResetPort (SATA_SI3132_PORT *Port);
  144. /*
  145. * Driver Binding Protocol Functions
  146. */
  147. EFI_STATUS
  148. EFIAPI
  149. SataSiI3132DriverBindingSupported (
  150. IN EFI_DRIVER_BINDING_PROTOCOL *This,
  151. IN EFI_HANDLE Controller,
  152. IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
  153. );
  154. EFI_STATUS
  155. EFIAPI
  156. SataSiI3132DriverBindingStart (
  157. IN EFI_DRIVER_BINDING_PROTOCOL *This,
  158. IN EFI_HANDLE Controller,
  159. IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
  160. );
  161. EFI_STATUS
  162. EFIAPI
  163. SataSiI3132DriverBindingStop (
  164. IN EFI_DRIVER_BINDING_PROTOCOL *This,
  165. IN EFI_HANDLE Controller,
  166. IN UINTN NumberOfChildren,
  167. IN EFI_HANDLE *ChildHandleBuffer
  168. );
  169. EFI_STATUS SiI3132AtaPassThruCommand (
  170. IN SATA_SI3132_INSTANCE *pSataSiI3132Instance,
  171. IN SATA_SI3132_PORT *pSataPort,
  172. IN UINT16 PortMultiplierPort,
  173. IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,
  174. IN EFI_EVENT Event OPTIONAL
  175. );
  176. /**
  177. * EFI ATA Pass Thru Protocol
  178. */
  179. EFI_STATUS SiI3132AtaPassThru (
  180. IN EFI_ATA_PASS_THRU_PROTOCOL *This,
  181. IN UINT16 Port,
  182. IN UINT16 PortMultiplierPort,
  183. IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,
  184. IN EFI_EVENT Event OPTIONAL
  185. );
  186. EFI_STATUS SiI3132GetNextPort (
  187. IN EFI_ATA_PASS_THRU_PROTOCOL *This,
  188. IN OUT UINT16 *Port
  189. );
  190. EFI_STATUS SiI3132GetNextDevice (
  191. IN EFI_ATA_PASS_THRU_PROTOCOL *This,
  192. IN UINT16 Port,
  193. IN OUT UINT16 *PortMultiplierPort
  194. );
  195. EFI_STATUS SiI3132BuildDevicePath (
  196. IN EFI_ATA_PASS_THRU_PROTOCOL *This,
  197. IN UINT16 Port,
  198. IN UINT16 PortMultiplierPort,
  199. IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
  200. );
  201. EFI_STATUS SiI3132GetDevice (
  202. IN EFI_ATA_PASS_THRU_PROTOCOL *This,
  203. IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
  204. OUT UINT16 *Port,
  205. OUT UINT16 *PortMultiplierPort
  206. );
  207. EFI_STATUS SiI3132ResetPort (
  208. IN EFI_ATA_PASS_THRU_PROTOCOL *This,
  209. IN UINT16 Port
  210. );
  211. EFI_STATUS SiI3132ResetDevice (
  212. IN EFI_ATA_PASS_THRU_PROTOCOL *This,
  213. IN UINT16 Port,
  214. IN UINT16 PortMultiplierPort
  215. );
  216. #endif