Lan9118DxeHw.h 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394
  1. /** @file
  2. *
  3. * Copyright (c) 2012-2014, ARM Limited. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: BSD-2-Clause-Patent
  6. *
  7. **/
  8. #ifndef __LAN9118_DXE_HW_H__
  9. #define __LAN9118_DXE_HW_H__
  10. /*------------------------------------------------------------------------------
  11. LAN9118 SMCS Registers
  12. ------------------------------------------------------------------------------*/
  13. // Base address as on the VE board
  14. #define LAN9118_BA ((UINT32) PcdGet32(PcdLan9118DxeBaseAddress))
  15. /* ------------- Tx and Rx Data and Status Memory Locations ------------------*/
  16. #define LAN9118_RX_DATA (0x00000000 + LAN9118_BA)
  17. #define LAN9118_RX_STATUS (0x00000040 + LAN9118_BA)
  18. #define LAN9118_RX_STATUS_PEEK (0x00000044 + LAN9118_BA)
  19. #define LAN9118_TX_DATA (0x00000020 + LAN9118_BA)
  20. #define LAN9118_TX_STATUS (0x00000048 + LAN9118_BA)
  21. #define LAN9118_TX_STATUS_PEEK (0x0000004C + LAN9118_BA)
  22. /* ------------- System Control and Status Registers -------------------------*/
  23. #define LAN9118_ID_REV (0x00000050 + LAN9118_BA) // Chip ID and Revision
  24. #define LAN9118_IRQ_CFG (0x00000054 + LAN9118_BA) // Interrupt Configuration
  25. #define LAN9118_INT_STS (0x00000058 + LAN9118_BA) // Interrupt Status
  26. #define LAN9118_INT_EN (0x0000005C + LAN9118_BA) // Interrupt Enable
  27. //#define LAN9118_RESERVED (0x00000060)
  28. #define LAN9118_BYTE_TEST (0x00000064 + LAN9118_BA) // Byte Order Test
  29. #define LAN9118_FIFO_INT (0x00000068 + LAN9118_BA) // FIFO Level Interrupts
  30. #define LAN9118_RX_CFG (0x0000006C + LAN9118_BA) // Receive Configuration
  31. #define LAN9118_TX_CFG (0x00000070 + LAN9118_BA) // Transmit Configuration
  32. #define LAN9118_HW_CFG (0x00000074 + LAN9118_BA) // Hardware Configuration
  33. #define LAN9118_RX_DP_CTL (0x00000078 + LAN9118_BA) // Receive Data-Path Configuration
  34. #define LAN9118_RX_FIFO_INF (0x0000007C + LAN9118_BA) // Receive FIFO Information
  35. #define LAN9118_TX_FIFO_INF (0x00000080 + LAN9118_BA) // Transmit FIFO Information
  36. #define LAN9118_PMT_CTRL (0x00000084 + LAN9118_BA) // Power Management Control
  37. #define LAN9118_GPIO_CFG (0x00000088 + LAN9118_BA) // General Purpose IO Configuration
  38. #define LAN9118_GPT_CFG (0x0000008C + LAN9118_BA) // General Purpose Timer Configuration
  39. #define LAN9118_GPT_CNT (0x00000090 + LAN9118_BA) // General Purpose Timer Current Count
  40. #define LAN9118_WORD_SWAP (0x00000098 + LAN9118_BA) // Word Swap Control
  41. #define LAN9118_FREE_RUN (0x0000009C + LAN9118_BA) // Free-Run 25MHz Counter
  42. #define LAN9118_RX_DROP (0x000000A0 + LAN9118_BA) // Receiver Dropped Frames Counter
  43. #define LAN9118_MAC_CSR_CMD (0x000000A4 + LAN9118_BA) // MAC CSR Synchronizer Command
  44. #define LAN9118_MAC_CSR_DATA (0x000000A8 + LAN9118_BA) // MAC CSR Synchronizer Data
  45. #define LAN9118_AFC_CFG (0x000000AC + LAN9118_BA) // Automatic Flow Control Configuration
  46. #define LAN9118_E2P_CMD (0x000000B0 + LAN9118_BA) // EEPROM Command
  47. #define LAN9118_E2P_DATA (0x000000B4 + LAN9118_BA) // EEPROM Data
  48. /*
  49. * Required delays following write cycles (number of BYTE_TEST reads)
  50. * Taken from Table 6.1 in Revision 1.5 (07-11-08) of the LAN9118 datasheet.
  51. * Where no delay listed, 0 has been assumed.
  52. */
  53. #define LAN9118_RX_DATA_WR_DELAY 0
  54. #define LAN9118_RX_STATUS_WR_DELAY 0
  55. #define LAN9118_RX_STATUS_PEEK_WR_DELAY 0
  56. #define LAN9118_TX_DATA_WR_DELAY 0
  57. #define LAN9118_TX_STATUS_WR_DELAY 0
  58. #define LAN9118_TX_STATUS_PEEK_WR_DELAY 0
  59. #define LAN9118_ID_REV_WR_DELAY 0
  60. #define LAN9118_IRQ_CFG_WR_DELAY 3
  61. #define LAN9118_INT_STS_WR_DELAY 2
  62. #define LAN9118_INT_EN_WR_DELAY 1
  63. #define LAN9118_BYTE_TEST_WR_DELAY 0
  64. #define LAN9118_FIFO_INT_WR_DELAY 1
  65. #define LAN9118_RX_CFG_WR_DELAY 1
  66. #define LAN9118_TX_CFG_WR_DELAY 1
  67. #define LAN9118_HW_CFG_WR_DELAY 1
  68. #define LAN9118_RX_DP_CTL_WR_DELAY 1
  69. #define LAN9118_RX_FIFO_INF_WR_DELAY 0
  70. #define LAN9118_TX_FIFO_INF_WR_DELAY 3
  71. #define LAN9118_PMT_CTRL_WR_DELAY 7
  72. #define LAN9118_GPIO_CFG_WR_DELAY 1
  73. #define LAN9118_GPT_CFG_WR_DELAY 1
  74. #define LAN9118_GPT_CNT_WR_DELAY 3
  75. #define LAN9118_WORD_SWAP_WR_DELAY 1
  76. #define LAN9118_FREE_RUN_WR_DELAY 4
  77. #define LAN9118_RX_DROP_WR_DELAY 0
  78. #define LAN9118_MAC_CSR_CMD_WR_DELAY 1
  79. #define LAN9118_MAC_CSR_DATA_WR_DELAY 1
  80. #define LAN9118_AFC_CFG_WR_DELAY 1
  81. #define LAN9118_E2P_CMD_WR_DELAY 1
  82. #define LAN9118_E2P_DATA_WR_DELAY 1
  83. /*
  84. * Required delays following read cycles (number of BYTE_TEST reads)
  85. * Taken from Table 6.2 in Revision 1.5 (07-11-08) of the LAN9118 datasheet.
  86. * Where no delay listed, 0 has been assumed.
  87. */
  88. #define LAN9118_RX_DATA_RD_DELAY 3
  89. #define LAN9118_RX_STATUS_RD_DELAY 3
  90. #define LAN9118_RX_STATUS_PEEK_RD_DELAY 0
  91. #define LAN9118_TX_DATA_RD_DELAY 0
  92. #define LAN9118_TX_STATUS_RD_DELAY 3
  93. #define LAN9118_TX_STATUS_PEEK_RD_DELAY 0
  94. #define LAN9118_ID_REV_RD_DELAY 0
  95. #define LAN9118_IRQ_CFG_RD_DELAY 0
  96. #define LAN9118_INT_STS_RD_DELAY 0
  97. #define LAN9118_INT_EN_RD_DELAY 0
  98. #define LAN9118_BYTE_TEST_RD_DELAY 0
  99. #define LAN9118_FIFO_INT_RD_DELAY 0
  100. #define LAN9118_RX_CFG_RD_DELAY 0
  101. #define LAN9118_TX_CFG_RD_DELAY 0
  102. #define LAN9118_HW_CFG_RD_DELAY 0
  103. #define LAN9118_RX_DP_CTL_RD_DELAY 0
  104. #define LAN9118_RX_FIFO_INF_RD_DELAY 0
  105. #define LAN9118_TX_FIFO_INF_RD_DELAY 0
  106. #define LAN9118_PMT_CTRL_RD_DELAY 0
  107. #define LAN9118_GPIO_CFG_RD_DELAY 0
  108. #define LAN9118_GPT_CFG_RD_DELAY 0
  109. #define LAN9118_GPT_CNT_RD_DELAY 0
  110. #define LAN9118_WORD_SWAP_RD_DELAY 0
  111. #define LAN9118_FREE_RUN_RD_DELAY 0
  112. #define LAN9118_RX_DROP_RD_DELAY 4
  113. #define LAN9118_MAC_CSR_CMD_RD_DELAY 0
  114. #define LAN9118_MAC_CSR_DATA_RD_DELAY 0
  115. #define LAN9118_AFC_CFG_RD_DELAY 0
  116. #define LAN9118_E2P_CMD_RD_DELAY 0
  117. #define LAN9118_E2P_DATA_RD_DELAY 0
  118. // Receiver Status bits
  119. #define RXSTATUS_CRC_ERROR BIT1 // Cyclic Redundancy Check Error
  120. #define RXSTATUS_DB BIT2 // Dribbling bit: Frame had non-integer multiple of 8bits
  121. #define RXSTATUS_MII_ERROR BIT3 // Receive error during interception
  122. #define RXSTATUS_RXW_TO BIT4 // Incomming frame larger than 2kb
  123. #define RXSTATUS_FT BIT5 // 1: Ether type / 0: 802.3 type frame
  124. #define RXSTATUS_LCOLL BIT6 // Late collision detected
  125. #define RXSTATUS_FTL BIT7 // Frame longer than Ether type
  126. #define RXSTATUS_MCF BIT10 // Frame has Multicast Address
  127. #define RXSTATUS_RUNT BIT11 // Bad frame
  128. #define RXSTATUS_LE BIT12 // Actual length of frame different than it claims
  129. #define RXSTATUS_BCF BIT13 // Frame has Broadcast Address
  130. #define RXSTATUS_ES BIT15 // Reports any error from bits 1,6,7 and 11
  131. #define RXSTATUS_PL_MASK (0x3FFF0000) // Packet length bit mask
  132. #define GET_RXSTATUS_PACKET_LENGTH(RxStatus) (((RxStatus) >> 16) & 0x3FFF) // Packet length bit mask
  133. #define RXSTATUS_FILT_FAIL BIT30 // The frame failed filtering test
  134. // Transmitter Status bits
  135. #define TXSTATUS_DEF BIT0 // Packet tx was deferred
  136. #define TXSTATUS_EDEF BIT2 // Tx ended because of excessive deferral (> 24288 bit times)
  137. #define TXSTATUS_CC_MASK (0x00000078) // Collision Count (before Tx) bit mask
  138. #define TXSTATUS_ECOLL BIT8 // Tx ended because of Excessive Collisions (makes CC_MASK invalid after 16 collisions)
  139. #define TXSTATUS_LCOLL BIT9 // Packet Tx aborted after coll window of 64 bytes
  140. #define TXSTATUS_NO_CA BIT10 // Carrier signal not present during Tx (bad?)
  141. #define TXSTATUS_LOST_CA BIT11 // Lost carrier during Tx
  142. #define TXSTATUS_ES BIT15 // Reports any errors from bits 1,2,8,9,10 and 11
  143. #define TXSTATUS_PTAG_MASK (0xFFFF0000) // Mask for Unique ID of packets (So we know who the packets are for)
  144. // ID_REV register bits
  145. #define IDREV_ID ((Lan9118MmioRead32(LAN9118_ID_REV) & 0xFFFF0000) >> 16)
  146. #define IDREV_REV (Lan9118MmioRead32(LAN9118_ID_REV) & 0x0000FFFF)
  147. // Interrupt Config Register bits
  148. #define IRQCFG_IRQ_TYPE BIT0 // IRQ Buffer type
  149. #define IRQCFG_IRQ_POL BIT4 // IRQ Polarity
  150. #define IRQCFG_IRQ_EN BIT8 // Enable external interrupt
  151. #define IRQCFG_IRQ_INT BIT12 // State of internal interrupts line
  152. #define IRQCFG_INT_DEAS_STS BIT13 // State of deassertion interval
  153. #define IRQCFG_INT_DEAS_CLR BIT14 // Clear the deassertion counter
  154. #define IRQCFG_INT_DEAS_MASK (0xFF000000) // Interrupt deassertion interval value mask
  155. // Interrupt Status Register bits
  156. #define INSTS_GPIO_MASK (0x7) // GPIO interrupts mask
  157. #define INSTS_RSFL (0x8) // Rx Status FIFO Level reached
  158. #define INSTS_RSFF BIT4 // Rx Status FIFO full
  159. #define INSTS_RXDF_INT BIT6 // Rx Frame dropped
  160. #define INSTS_TSFL BIT7 // Tx Status FIFO Level reached
  161. #define INSTS_TSFF BIT8 // Tx Status FIFO full
  162. #define INSTS_TDFA BIT9 // Tx Data FIFO Level exceeded
  163. #define INSTS_TDFO BIT10 // Tx Data FIFO full
  164. #define INSTS_TXE BIT13 // Transmitter Error
  165. #define INSTS_RXE BIT14 // Receiver Error
  166. #define INSTS_RWT BIT15 // Packet > 2048 bytes received
  167. #define INSTS_TXSO BIT16 // Tx Status FIFO Overflow
  168. #define INSTS_PME_INT BIT17 // PME Signal detected
  169. #define INSTS_PHY_INT BIT18 // Indicates PHY Interrupt
  170. #define INSTS_GPT_INT BIT19 // GP Timer wrapped past 0xFFFF
  171. #define INSTS_RXD_INT BIT20 // Indicates that amount of data written to RX_CFG was cleared
  172. #define INSTS_TX_IOC BIT21 // Finished loading IOC flagged buffer to Tx FIFO
  173. #define INSTS_RXDFH_INT BIT23 // Rx Dropped frames went past 0x7FFFFFFF
  174. #define INSTS_RXSTOP_INT BIT24 // Rx was stopped
  175. #define INSTS_TXSTOP_INT BIT25 // Tx was stopped
  176. #define INSTS_SW_INT BIT31 // Software Interrupt occurred
  177. // Interrupt Enable Register bits
  178. // Hardware Config Register bits
  179. #define HWCFG_SRST BIT0 // Software Reset bit (SC)
  180. #define HWCFG_SRST_TO BIT1 // Software Reset Timeout bit (RO)
  181. #define HWCFG_BMODE BIT2 // 32/16 bit Mode bit (RO)
  182. #define HWCFG_TX_FIFO_SIZE_MASK (~ (UINT32)0xF0000) // Mask to Clear FIFO Size
  183. #define HWCFG_MBO BIT20 // Must Be One bit
  184. // Power Management Control Register
  185. #define MPTCTRL_READY BIT0 // Device ready indicator
  186. #define MPTCTRL_PME_EN BIT1 // Enable external PME signals
  187. #define MPTCTRL_PME_POL BIT2 // Set polarity of PME signals
  188. #define MPTCTRL_PME_IND BIT3 // Signal type of PME (refer to Spec)
  189. #define MPTCTRL_WUPS_MASK (0x18) // Wake up status indicator mask
  190. #define MPTCTRL_PME_TYPE BIT6 // PME Buffer type (Open Drain or Push-Pull)
  191. #define MPTCTRL_ED_EN BIT8 // Energy-detect enable
  192. #define MPTCTRL_WOL_EN BIT9 // Enable wake-on-lan
  193. #define MPTCTRL_PHY_RST BIT10 // Reset the PHY
  194. #define MPTCTRL_PM_MODE_MASK (BIT12 | BIT13) // Set the power mode
  195. // PHY control register bits
  196. #define PHYCR_COLL_TEST BIT7 // Collision test enable
  197. #define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode
  198. #define PHYCR_RST_AUTO BIT9 // Restart Auto-Negotiation of Link abilities
  199. #define PHYCR_PD BIT11 // Power-Down switch
  200. #define PHYCR_AUTO_EN BIT12 // Auto-Negotiation Enable
  201. #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection
  202. #define PHYCR_LOOPBK BIT14 // Set loopback mode
  203. #define PHYCR_RESET BIT15 // Do a PHY reset
  204. // PHY status register bits
  205. #define PHYSTS_EXT_CAP BIT0 // Extended Capabilities Register capability
  206. #define PHYSTS_JABBER BIT1 // Jabber condition detected
  207. #define PHYSTS_LINK_STS BIT2 // Link Status
  208. #define PHYSTS_AUTO_CAP BIT3 // Auto-Negotiation Capability
  209. #define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected
  210. #define PHYSTS_AUTO_COMP BIT5 // Auto-Negotiation Completed
  211. #define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability
  212. #define PHYSTS_10BASET_FDPLX BIT12 // 10Mbps Full-Duplex ability
  213. #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability
  214. #define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability
  215. #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability
  216. // PHY Auto-Negotiation advertisement
  217. #define PHYANA_SEL_MASK ((UINT32)0x1F) // Link type selector
  218. #define PHYANA_10BASET BIT5 // Advertise 10BASET capability
  219. #define PHYANA_10BASETFD BIT6 // Advertise 10BASET Full duplex capability
  220. #define PHYANA_100BASETX BIT7 // Advertise 100BASETX capability
  221. #define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full duplex capability
  222. #define PHYANA_PAUSE_OP_MASK (3 << 10) // Advertise PAUSE frame capability
  223. #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected
  224. // PHY Auto-Negotiation Link Partner Ability
  225. // PHY Auto-Negotiation Expansion
  226. // PHY Mode control/status
  227. // PHY Special Modes
  228. // PHY Special control/status
  229. // PHY Interrupt Source Flags
  230. // PHY Interrupt Mask
  231. // PHY Super Special control/status
  232. #define PHYSSCS_HCDSPEED_MASK (7 << 2) // Speed indication
  233. #define PHYSSCS_AUTODONE BIT12 // Auto-Negotiation Done
  234. // MAC control register bits
  235. #define MACCR_RX_EN BIT2 // Enable Receiver bit
  236. #define MACCR_TX_EN BIT3 // Enable Transmitter bit
  237. #define MACCR_DFCHK BIT5 // Deferral Check bit
  238. #define MACCR_PADSTR BIT8 // Automatic Pad Stripping bit
  239. #define MACCR_BOLMT_MASK (0xC0) // Back-Off limit mask
  240. #define MACCR_DISRTY BIT10 // Disable Transmit Retry bit
  241. #define MACCR_BCAST BIT11 // Disable Broadcast Frames bit
  242. #define MACCR_LCOLL BIT12 // Late Collision Control bit
  243. #define MACCR_HPFILT BIT13 // Hash/Perfect Filtering Mode bit
  244. #define MACCR_HO BIT15 // Hash Only Filtering Mode
  245. #define MACCR_PASSBAD BIT16 // Receive all frames that passed filter bit
  246. #define MACCR_INVFILT BIT17 // Enable Inverse Filtering bit
  247. #define MACCR_PRMS BIT18 // Promiscuous Mode bit
  248. #define MACCR_MCPAS BIT19 // Pass all Multicast packets bit
  249. #define MACCR_FDPX BIT20 // Full Duplex Mode bit
  250. #define MACCR_LOOPBK BIT21 // Loopback operation mode bit
  251. #define MACCR_RCVOWN BIT23 // Disable Receive Own frames bit
  252. #define MACCR_RX_ALL BIT31 // Receive all Packets and route to Filter
  253. // Wake-Up Control and Status Register
  254. #define WUCSR_MPEN BIT1 // Magic Packet enable (allow wake from Magic P)
  255. #define WUCSR_WUEN BIT2 // Allow remote wake up using Wake-Up Frames
  256. #define WUCSR_MPR_MASK (0x10) // Received Magic Packet
  257. #define WUCSR_WUFR_MASK (0x20) // Received Wake-Up Frame
  258. #define WUCSR_GUE BIT9 // Enable wake on global unicast frames
  259. // RX Configuration Register bits
  260. #define RXCFG_RXDOFF_MASK (0x1F00) // Rx Data Offset in Bytes
  261. #define RXCFG_RX_DUMP BIT15 // Clear Rx data and status FIFOs
  262. #define RXCFG_RX_DMA_CNT_MASK (0x0FFF0000) // Amount of data to be read from Rx FIFO
  263. #define RXCFG_RX_DMA_CNT(cnt) (((cnt) & 0xFFF) << 16) // Amount of data to be read from Rx FIFO
  264. #define RXCFG_RX_END_ALIGN_MASK (0xC0000000) // Alignment to preserve
  265. // TX Configuration Register bits
  266. #define TXCFG_STOP_TX BIT0 // Stop the transmitter
  267. #define TXCFG_TX_ON BIT1 // Start the transmitter
  268. #define TXCFG_TXSAO BIT2 // Tx Status FIFO full
  269. #define TXCFG_TXD_DUMP BIT14 // Clear Tx Data FIFO
  270. #define TXCFG_TXS_DUMP BIT15 // Clear Tx Status FIFO
  271. // Rx FIFO Information Register bits
  272. #define RXFIFOINF_RXDUSED_MASK (0xFFFF) // Rx Data FIFO Used Space
  273. #define RXFIFOINF_RXSUSED_MASK (0xFF0000) // Rx Status FIFO Used Space
  274. // Tx FIFO Information Register bits
  275. #define TXFIFOINF_TDFREE_MASK (0xFFFF) // Tx Data FIFO Free Space
  276. #define TXFIFOINF_TXSUSED_MASK (0xFF0000) // Tx Status FIFO Used Space
  277. // E2P Register
  278. #define E2P_EPC_BUSY BIT31
  279. #define E2P_EPC_CMD_READ (0)
  280. #define E2P_EPC_TIMEOUT BIT9
  281. #define E2P_EPC_MAC_ADDRESS_LOADED BIT8
  282. #define E2P_EPC_ADDRESS(address) ((address) & 0xFFFF)
  283. // GPIO Configuration register
  284. #define GPIO_GPIO0_PUSH_PULL BIT16
  285. #define GPIO_GPIO1_PUSH_PULL BIT17
  286. #define GPIO_GPIO2_PUSH_PULL BIT18
  287. #define GPIO_LED1_ENABLE BIT28
  288. #define GPIO_LED2_ENABLE BIT29
  289. #define GPIO_LED3_ENABLE BIT30
  290. // MII_ACC bits
  291. #define MII_ACC_MII_BUSY BIT0
  292. #define MII_ACC_MII_WRITE BIT1
  293. #define MII_ACC_MII_READ 0
  294. #define MII_ACC_PHY_VALUE BIT11
  295. #define MII_ACC_MII_REG_INDEX(index) (((index) & 0x1F) << 6)
  296. //
  297. // PHY Control Indexes
  298. //
  299. #define PHY_INDEX_BASIC_CTRL 0
  300. #define PHY_INDEX_BASIC_STATUS 1
  301. #define PHY_INDEX_ID1 2
  302. #define PHY_INDEX_ID2 3
  303. #define PHY_INDEX_AUTO_NEG_ADVERT 4
  304. #define PHY_INDEX_AUTO_NEG_LINK_ABILITY 5
  305. #define PHY_INDEX_AUTO_NEG_EXP 6
  306. #define PHY_INDEX_MODE 17
  307. #define PHY_INDEX_SPECIAL_MODES 18
  308. #define PHY_INDEX_SPECIAL_CTLR 27
  309. #define PHY_INDEX_INT_SRC 29
  310. #define PHY_INDEX_INT_MASK 30
  311. #define PHY_INDEX_SPECIAL_PHY_CTLR 31
  312. // Indirect MAC Indexes
  313. #define INDIRECT_MAC_INDEX_CR 1
  314. #define INDIRECT_MAC_INDEX_ADDRH 2
  315. #define INDIRECT_MAC_INDEX_ADDRL 3
  316. #define INDIRECT_MAC_INDEX_HASHH 4
  317. #define INDIRECT_MAC_INDEX_HASHL 5
  318. #define INDIRECT_MAC_INDEX_MII_ACC 6
  319. #define INDIRECT_MAC_INDEX_MII_DATA 7
  320. //
  321. // MAC CSR Synchronizer Command register
  322. //
  323. #define MAC_CSR_BUSY BIT31
  324. #define MAC_CSR_READ BIT30
  325. #define MAC_CSR_WRITE 0
  326. #define MAC_CSR_ADDR(Addr) ((Addr) & 0xFF)
  327. //
  328. // TX Packet Format
  329. //
  330. #define TX_CMD_A_COMPLETION_INT BIT31
  331. #define TX_CMD_A_FIRST_SEGMENT BIT13
  332. #define TX_CMD_A_LAST_SEGMENT BIT12
  333. #define TX_CMD_A_BUFF_SIZE(size) ((size) & 0x000003FF)
  334. #define TX_CMD_A_DATA_START_OFFSET(offset) (((offset) & 0x1F) << 16)
  335. #define TX_CMD_B_PACKET_LENGTH(size) ((size) & 0x000003FF)
  336. #define TX_CMD_B_PACKET_TAG(tag) (((tag) & 0x3FF) << 16)
  337. // Hardware Configuration Register
  338. #define HW_CFG_TX_FIFO_SIZE_MASK (0xF << 16)
  339. #define HW_CFG_TX_FIFO_SIZE(size) (((size) & 0xF) << 16)
  340. // EEPROM Definition
  341. #define EEPROM_EXTERNAL_SERIAL_EEPROM 0xA5
  342. //
  343. // Conditional compilation flags
  344. //
  345. //#define EVAL_PERFORMANCE
  346. #endif /* __LAN9118_DXE_HDR_H__ */