CpuS3.c 39 KB

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  1. /** @file
  2. Code for Processor S3 restoration
  3. Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "PiSmmCpuDxeSmm.h"
  7. #pragma pack(1)
  8. typedef struct {
  9. UINTN Lock;
  10. VOID *StackStart;
  11. UINTN StackSize;
  12. VOID *ApFunction;
  13. IA32_DESCRIPTOR GdtrProfile;
  14. IA32_DESCRIPTOR IdtrProfile;
  15. UINT32 BufferStart;
  16. UINT32 Cr3;
  17. UINTN InitializeFloatingPointUnitsAddress;
  18. } MP_CPU_EXCHANGE_INFO;
  19. #pragma pack()
  20. typedef struct {
  21. UINT8 *RendezvousFunnelAddress;
  22. UINTN PModeEntryOffset;
  23. UINTN FlatJumpOffset;
  24. UINTN Size;
  25. UINTN LModeEntryOffset;
  26. UINTN LongJumpOffset;
  27. } MP_ASSEMBLY_ADDRESS_MAP;
  28. //
  29. // Flags used when program the register.
  30. //
  31. typedef struct {
  32. volatile UINTN MemoryMappedLock; // Spinlock used to program mmio
  33. volatile UINT32 *CoreSemaphoreCount; // Semaphore container used to program
  34. // core level semaphore.
  35. volatile UINT32 *PackageSemaphoreCount; // Semaphore container used to program
  36. // package level semaphore.
  37. } PROGRAM_CPU_REGISTER_FLAGS;
  38. //
  39. // Signal that SMM BASE relocation is complete.
  40. //
  41. volatile BOOLEAN mInitApsAfterSmmBaseReloc;
  42. /**
  43. Get starting address and size of the rendezvous entry for APs.
  44. Information for fixing a jump instruction in the code is also returned.
  45. @param AddressMap Output buffer for address map information.
  46. **/
  47. VOID *
  48. EFIAPI
  49. AsmGetAddressMap (
  50. MP_ASSEMBLY_ADDRESS_MAP *AddressMap
  51. );
  52. #define LEGACY_REGION_SIZE (2 * 0x1000)
  53. #define LEGACY_REGION_BASE (0xA0000 - LEGACY_REGION_SIZE)
  54. PROGRAM_CPU_REGISTER_FLAGS mCpuFlags;
  55. ACPI_CPU_DATA mAcpiCpuData;
  56. volatile UINT32 mNumberToFinish;
  57. MP_CPU_EXCHANGE_INFO *mExchangeInfo;
  58. BOOLEAN mRestoreSmmConfigurationInS3 = FALSE;
  59. //
  60. // S3 boot flag
  61. //
  62. BOOLEAN mSmmS3Flag = FALSE;
  63. //
  64. // Pointer to structure used during S3 Resume
  65. //
  66. SMM_S3_RESUME_STATE *mSmmS3ResumeState = NULL;
  67. BOOLEAN mAcpiS3Enable = TRUE;
  68. UINT8 *mApHltLoopCode = NULL;
  69. UINT8 mApHltLoopCodeTemplate[] = {
  70. 0x8B, 0x44, 0x24, 0x04, // mov eax, dword ptr [esp+4]
  71. 0xF0, 0xFF, 0x08, // lock dec dword ptr [eax]
  72. 0xFA, // cli
  73. 0xF4, // hlt
  74. 0xEB, 0xFC // jmp $-2
  75. };
  76. /**
  77. Sync up the MTRR values for all processors.
  78. @param MtrrTable Table holding fixed/variable MTRR values to be loaded.
  79. **/
  80. VOID
  81. EFIAPI
  82. LoadMtrrData (
  83. EFI_PHYSICAL_ADDRESS MtrrTable
  84. )
  85. /*++
  86. Routine Description:
  87. Sync up the MTRR values for all processors.
  88. Arguments:
  89. Returns:
  90. None
  91. --*/
  92. {
  93. MTRR_SETTINGS *MtrrSettings;
  94. MtrrSettings = (MTRR_SETTINGS *)(UINTN)MtrrTable;
  95. MtrrSetAllMtrrs (MtrrSettings);
  96. }
  97. /**
  98. Increment semaphore by 1.
  99. @param Sem IN: 32-bit unsigned integer
  100. **/
  101. VOID
  102. S3ReleaseSemaphore (
  103. IN OUT volatile UINT32 *Sem
  104. )
  105. {
  106. InterlockedIncrement (Sem);
  107. }
  108. /**
  109. Decrement the semaphore by 1 if it is not zero.
  110. Performs an atomic decrement operation for semaphore.
  111. The compare exchange operation must be performed using
  112. MP safe mechanisms.
  113. @param Sem IN: 32-bit unsigned integer
  114. **/
  115. VOID
  116. S3WaitForSemaphore (
  117. IN OUT volatile UINT32 *Sem
  118. )
  119. {
  120. UINT32 Value;
  121. do {
  122. Value = *Sem;
  123. } while (Value == 0 ||
  124. InterlockedCompareExchange32 (
  125. Sem,
  126. Value,
  127. Value - 1
  128. ) != Value);
  129. }
  130. /**
  131. Read / write CR value.
  132. @param[in] CrIndex The CR index which need to read/write.
  133. @param[in] Read Read or write. TRUE is read.
  134. @param[in,out] CrValue CR value.
  135. @retval EFI_SUCCESS means read/write success, else return EFI_UNSUPPORTED.
  136. **/
  137. UINTN
  138. ReadWriteCr (
  139. IN UINT32 CrIndex,
  140. IN BOOLEAN Read,
  141. IN OUT UINTN *CrValue
  142. )
  143. {
  144. switch (CrIndex) {
  145. case 0:
  146. if (Read) {
  147. *CrValue = AsmReadCr0 ();
  148. } else {
  149. AsmWriteCr0 (*CrValue);
  150. }
  151. break;
  152. case 2:
  153. if (Read) {
  154. *CrValue = AsmReadCr2 ();
  155. } else {
  156. AsmWriteCr2 (*CrValue);
  157. }
  158. break;
  159. case 3:
  160. if (Read) {
  161. *CrValue = AsmReadCr3 ();
  162. } else {
  163. AsmWriteCr3 (*CrValue);
  164. }
  165. break;
  166. case 4:
  167. if (Read) {
  168. *CrValue = AsmReadCr4 ();
  169. } else {
  170. AsmWriteCr4 (*CrValue);
  171. }
  172. break;
  173. default:
  174. return EFI_UNSUPPORTED;
  175. }
  176. return EFI_SUCCESS;
  177. }
  178. /**
  179. Initialize the CPU registers from a register table.
  180. @param[in] RegisterTable The register table for this AP.
  181. @param[in] ApLocation AP location info for this ap.
  182. @param[in] CpuStatus CPU status info for this CPU.
  183. @param[in] CpuFlags Flags data structure used when program the register.
  184. @note This service could be called by BSP/APs.
  185. **/
  186. VOID
  187. ProgramProcessorRegister (
  188. IN CPU_REGISTER_TABLE *RegisterTable,
  189. IN EFI_CPU_PHYSICAL_LOCATION *ApLocation,
  190. IN CPU_STATUS_INFORMATION *CpuStatus,
  191. IN PROGRAM_CPU_REGISTER_FLAGS *CpuFlags
  192. )
  193. {
  194. CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
  195. UINTN Index;
  196. UINTN Value;
  197. CPU_REGISTER_TABLE_ENTRY *RegisterTableEntryHead;
  198. volatile UINT32 *SemaphorePtr;
  199. UINT32 FirstThread;
  200. UINT32 CurrentThread;
  201. UINT32 CurrentCore;
  202. UINTN ProcessorIndex;
  203. UINT32 *ThreadCountPerPackage;
  204. UINT8 *ThreadCountPerCore;
  205. EFI_STATUS Status;
  206. UINT64 CurrentValue;
  207. //
  208. // Traverse Register Table of this logical processor
  209. //
  210. RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry;
  211. for (Index = 0; Index < RegisterTable->TableLength; Index++) {
  212. RegisterTableEntry = &RegisterTableEntryHead[Index];
  213. //
  214. // Check the type of specified register
  215. //
  216. switch (RegisterTableEntry->RegisterType) {
  217. //
  218. // The specified register is Control Register
  219. //
  220. case ControlRegister:
  221. Status = ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value);
  222. if (EFI_ERROR (Status)) {
  223. break;
  224. }
  225. if (RegisterTableEntry->TestThenWrite) {
  226. CurrentValue = BitFieldRead64 (
  227. Value,
  228. RegisterTableEntry->ValidBitStart,
  229. RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1
  230. );
  231. if (CurrentValue == RegisterTableEntry->Value) {
  232. break;
  233. }
  234. }
  235. Value = (UINTN)BitFieldWrite64 (
  236. Value,
  237. RegisterTableEntry->ValidBitStart,
  238. RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
  239. RegisterTableEntry->Value
  240. );
  241. ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value);
  242. break;
  243. //
  244. // The specified register is Model Specific Register
  245. //
  246. case Msr:
  247. if (RegisterTableEntry->TestThenWrite) {
  248. Value = (UINTN)AsmReadMsr64 (RegisterTableEntry->Index);
  249. if (RegisterTableEntry->ValidBitLength >= 64) {
  250. if (Value == RegisterTableEntry->Value) {
  251. break;
  252. }
  253. } else {
  254. CurrentValue = BitFieldRead64 (
  255. Value,
  256. RegisterTableEntry->ValidBitStart,
  257. RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1
  258. );
  259. if (CurrentValue == RegisterTableEntry->Value) {
  260. break;
  261. }
  262. }
  263. }
  264. //
  265. // If this function is called to restore register setting after INIT signal,
  266. // there is no need to restore MSRs in register table.
  267. //
  268. if (RegisterTableEntry->ValidBitLength >= 64) {
  269. //
  270. // If length is not less than 64 bits, then directly write without reading
  271. //
  272. AsmWriteMsr64 (
  273. RegisterTableEntry->Index,
  274. RegisterTableEntry->Value
  275. );
  276. } else {
  277. //
  278. // Set the bit section according to bit start and length
  279. //
  280. AsmMsrBitFieldWrite64 (
  281. RegisterTableEntry->Index,
  282. RegisterTableEntry->ValidBitStart,
  283. RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
  284. RegisterTableEntry->Value
  285. );
  286. }
  287. break;
  288. //
  289. // MemoryMapped operations
  290. //
  291. case MemoryMapped:
  292. AcquireSpinLock (&CpuFlags->MemoryMappedLock);
  293. MmioBitFieldWrite32 (
  294. (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)),
  295. RegisterTableEntry->ValidBitStart,
  296. RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
  297. (UINT32)RegisterTableEntry->Value
  298. );
  299. ReleaseSpinLock (&CpuFlags->MemoryMappedLock);
  300. break;
  301. //
  302. // Enable or disable cache
  303. //
  304. case CacheControl:
  305. //
  306. // If value of the entry is 0, then disable cache. Otherwise, enable cache.
  307. //
  308. if (RegisterTableEntry->Value == 0) {
  309. AsmDisableCache ();
  310. } else {
  311. AsmEnableCache ();
  312. }
  313. break;
  314. case Semaphore:
  315. // Semaphore works logic like below:
  316. //
  317. // V(x) = LibReleaseSemaphore (Semaphore[FirstThread + x]);
  318. // P(x) = LibWaitForSemaphore (Semaphore[FirstThread + x]);
  319. //
  320. // All threads (T0...Tn) waits in P() line and continues running
  321. // together.
  322. //
  323. //
  324. // T0 T1 ... Tn
  325. //
  326. // V(0...n) V(0...n) ... V(0...n)
  327. // n * P(0) n * P(1) ... n * P(n)
  328. //
  329. ASSERT (
  330. (ApLocation != NULL) &&
  331. (CpuStatus->ThreadCountPerPackage != 0) &&
  332. (CpuStatus->ThreadCountPerCore != 0) &&
  333. (CpuFlags->CoreSemaphoreCount != NULL) &&
  334. (CpuFlags->PackageSemaphoreCount != NULL)
  335. );
  336. switch (RegisterTableEntry->Value) {
  337. case CoreDepType:
  338. SemaphorePtr = CpuFlags->CoreSemaphoreCount;
  339. ThreadCountPerCore = (UINT8 *)(UINTN)CpuStatus->ThreadCountPerCore;
  340. CurrentCore = ApLocation->Package * CpuStatus->MaxCoreCount + ApLocation->Core;
  341. //
  342. // Get Offset info for the first thread in the core which current thread belongs to.
  343. //
  344. FirstThread = CurrentCore * CpuStatus->MaxThreadCount;
  345. CurrentThread = FirstThread + ApLocation->Thread;
  346. //
  347. // Different cores may have different valid threads in them. If driver maintail clearly
  348. // thread index in different cores, the logic will be much complicated.
  349. // Here driver just simply records the max thread number in all cores and use it as expect
  350. // thread number for all cores.
  351. // In below two steps logic, first current thread will Release semaphore for each thread
  352. // in current core. Maybe some threads are not valid in this core, but driver don't
  353. // care. Second, driver will let current thread wait semaphore for all valid threads in
  354. // current core. Because only the valid threads will do release semaphore for this
  355. // thread, driver here only need to wait the valid thread count.
  356. //
  357. //
  358. // First Notify ALL THREADs in current Core that this thread is ready.
  359. //
  360. for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex++) {
  361. S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
  362. }
  363. //
  364. // Second, check whether all VALID THREADs (not all threads) in current core are ready.
  365. //
  366. for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex++) {
  367. S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);
  368. }
  369. break;
  370. case PackageDepType:
  371. SemaphorePtr = CpuFlags->PackageSemaphoreCount;
  372. ThreadCountPerPackage = (UINT32 *)(UINTN)CpuStatus->ThreadCountPerPackage;
  373. //
  374. // Get Offset info for the first thread in the package which current thread belongs to.
  375. //
  376. FirstThread = ApLocation->Package * CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount;
  377. //
  378. // Get the possible threads count for current package.
  379. //
  380. CurrentThread = FirstThread + CpuStatus->MaxThreadCount * ApLocation->Core + ApLocation->Thread;
  381. //
  382. // Different packages may have different valid threads in them. If driver maintail clearly
  383. // thread index in different packages, the logic will be much complicated.
  384. // Here driver just simply records the max thread number in all packages and use it as expect
  385. // thread number for all packages.
  386. // In below two steps logic, first current thread will Release semaphore for each thread
  387. // in current package. Maybe some threads are not valid in this package, but driver don't
  388. // care. Second, driver will let current thread wait semaphore for all valid threads in
  389. // current package. Because only the valid threads will do release semaphore for this
  390. // thread, driver here only need to wait the valid thread count.
  391. //
  392. //
  393. // First Notify ALL THREADS in current package that this thread is ready.
  394. //
  395. for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex++) {
  396. S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
  397. }
  398. //
  399. // Second, check whether VALID THREADS (not all threads) in current package are ready.
  400. //
  401. for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex++) {
  402. S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);
  403. }
  404. break;
  405. default:
  406. break;
  407. }
  408. break;
  409. default:
  410. break;
  411. }
  412. }
  413. }
  414. /**
  415. Set Processor register for one AP.
  416. @param PreSmmRegisterTable Use pre Smm register table or register table.
  417. **/
  418. VOID
  419. SetRegister (
  420. IN BOOLEAN PreSmmRegisterTable
  421. )
  422. {
  423. CPU_FEATURE_INIT_DATA *FeatureInitData;
  424. CPU_REGISTER_TABLE *RegisterTable;
  425. CPU_REGISTER_TABLE *RegisterTables;
  426. UINT32 InitApicId;
  427. UINTN ProcIndex;
  428. UINTN Index;
  429. FeatureInitData = &mAcpiCpuData.CpuFeatureInitData;
  430. if (PreSmmRegisterTable) {
  431. RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)FeatureInitData->PreSmmInitRegisterTable;
  432. } else {
  433. RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)FeatureInitData->RegisterTable;
  434. }
  435. if (RegisterTables == NULL) {
  436. return;
  437. }
  438. InitApicId = GetInitialApicId ();
  439. RegisterTable = NULL;
  440. ProcIndex = (UINTN)-1;
  441. for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {
  442. if (RegisterTables[Index].InitialApicId == InitApicId) {
  443. RegisterTable = &RegisterTables[Index];
  444. ProcIndex = Index;
  445. break;
  446. }
  447. }
  448. ASSERT (RegisterTable != NULL);
  449. if (FeatureInitData->ApLocation != 0) {
  450. ProgramProcessorRegister (
  451. RegisterTable,
  452. (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)FeatureInitData->ApLocation + ProcIndex,
  453. &FeatureInitData->CpuStatus,
  454. &mCpuFlags
  455. );
  456. } else {
  457. ProgramProcessorRegister (
  458. RegisterTable,
  459. NULL,
  460. &FeatureInitData->CpuStatus,
  461. &mCpuFlags
  462. );
  463. }
  464. }
  465. /**
  466. AP initialization before then after SMBASE relocation in the S3 boot path.
  467. **/
  468. VOID
  469. InitializeAp (
  470. VOID
  471. )
  472. {
  473. UINTN TopOfStack;
  474. UINT8 Stack[128];
  475. LoadMtrrData (mAcpiCpuData.MtrrTable);
  476. SetRegister (TRUE);
  477. //
  478. // Count down the number with lock mechanism.
  479. //
  480. InterlockedDecrement (&mNumberToFinish);
  481. //
  482. // Wait for BSP to signal SMM Base relocation done.
  483. //
  484. while (!mInitApsAfterSmmBaseReloc) {
  485. CpuPause ();
  486. }
  487. ProgramVirtualWireMode ();
  488. DisableLvtInterrupts ();
  489. SetRegister (FALSE);
  490. //
  491. // Place AP into the safe code, count down the number with lock mechanism in the safe code.
  492. //
  493. TopOfStack = (UINTN)Stack + sizeof (Stack);
  494. TopOfStack &= ~(UINTN)(CPU_STACK_ALIGNMENT - 1);
  495. CopyMem ((VOID *)(UINTN)mApHltLoopCode, mApHltLoopCodeTemplate, sizeof (mApHltLoopCodeTemplate));
  496. TransferApToSafeState ((UINTN)mApHltLoopCode, TopOfStack, (UINTN)&mNumberToFinish);
  497. }
  498. /**
  499. Prepares startup vector for APs.
  500. This function prepares startup vector for APs.
  501. @param WorkingBuffer The address of the work buffer.
  502. **/
  503. VOID
  504. PrepareApStartupVector (
  505. EFI_PHYSICAL_ADDRESS WorkingBuffer
  506. )
  507. {
  508. EFI_PHYSICAL_ADDRESS StartupVector;
  509. MP_ASSEMBLY_ADDRESS_MAP AddressMap;
  510. //
  511. // Get the address map of startup code for AP,
  512. // including code size, and offset of long jump instructions to redirect.
  513. //
  514. ZeroMem (&AddressMap, sizeof (AddressMap));
  515. AsmGetAddressMap (&AddressMap);
  516. StartupVector = WorkingBuffer;
  517. //
  518. // Copy AP startup code to startup vector, and then redirect the long jump
  519. // instructions for mode switching.
  520. //
  521. CopyMem ((VOID *)(UINTN)StartupVector, AddressMap.RendezvousFunnelAddress, AddressMap.Size);
  522. *(UINT32 *)(UINTN)(StartupVector + AddressMap.FlatJumpOffset + 3) = (UINT32)(StartupVector + AddressMap.PModeEntryOffset);
  523. if (AddressMap.LongJumpOffset != 0) {
  524. *(UINT32 *)(UINTN)(StartupVector + AddressMap.LongJumpOffset + 2) = (UINT32)(StartupVector + AddressMap.LModeEntryOffset);
  525. }
  526. //
  527. // Get the start address of exchange data between BSP and AP.
  528. //
  529. mExchangeInfo = (MP_CPU_EXCHANGE_INFO *)(UINTN)(StartupVector + AddressMap.Size);
  530. ZeroMem ((VOID *)mExchangeInfo, sizeof (MP_CPU_EXCHANGE_INFO));
  531. CopyMem ((VOID *)(UINTN)&mExchangeInfo->GdtrProfile, (VOID *)(UINTN)mAcpiCpuData.GdtrProfile, sizeof (IA32_DESCRIPTOR));
  532. CopyMem ((VOID *)(UINTN)&mExchangeInfo->IdtrProfile, (VOID *)(UINTN)mAcpiCpuData.IdtrProfile, sizeof (IA32_DESCRIPTOR));
  533. mExchangeInfo->StackStart = (VOID *)(UINTN)mAcpiCpuData.StackAddress;
  534. mExchangeInfo->StackSize = mAcpiCpuData.StackSize;
  535. mExchangeInfo->BufferStart = (UINT32)StartupVector;
  536. mExchangeInfo->Cr3 = (UINT32)(AsmReadCr3 ());
  537. mExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits;
  538. }
  539. /**
  540. The function is invoked before SMBASE relocation in S3 path to restores CPU status.
  541. The function is invoked before SMBASE relocation in S3 path. It does first time microcode load
  542. and restores MTRRs for both BSP and APs.
  543. **/
  544. VOID
  545. InitializeCpuBeforeRebase (
  546. VOID
  547. )
  548. {
  549. LoadMtrrData (mAcpiCpuData.MtrrTable);
  550. SetRegister (TRUE);
  551. ProgramVirtualWireMode ();
  552. PrepareApStartupVector (mAcpiCpuData.StartupVector);
  553. if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
  554. ASSERT (mNumberOfCpus <= mAcpiCpuData.NumberOfCpus);
  555. } else {
  556. ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus);
  557. }
  558. mNumberToFinish = (UINT32)(mNumberOfCpus - 1);
  559. mExchangeInfo->ApFunction = (VOID *)(UINTN)InitializeAp;
  560. //
  561. // Execute code for before SmmBaseReloc. Note: This flag is maintained across S3 boots.
  562. //
  563. mInitApsAfterSmmBaseReloc = FALSE;
  564. //
  565. // Send INIT IPI - SIPI to all APs
  566. //
  567. SendInitSipiSipiAllExcludingSelf ((UINT32)mAcpiCpuData.StartupVector);
  568. while (mNumberToFinish > 0) {
  569. CpuPause ();
  570. }
  571. }
  572. /**
  573. The function is invoked after SMBASE relocation in S3 path to restores CPU status.
  574. The function is invoked after SMBASE relocation in S3 path. It restores configuration according to
  575. data saved by normal boot path for both BSP and APs.
  576. **/
  577. VOID
  578. InitializeCpuAfterRebase (
  579. VOID
  580. )
  581. {
  582. if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
  583. ASSERT (mNumberOfCpus <= mAcpiCpuData.NumberOfCpus);
  584. } else {
  585. ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus);
  586. }
  587. mNumberToFinish = (UINT32)(mNumberOfCpus - 1);
  588. //
  589. // Signal that SMM base relocation is complete and to continue initialization for all APs.
  590. //
  591. mInitApsAfterSmmBaseReloc = TRUE;
  592. //
  593. // Must begin set register after all APs have continue their initialization.
  594. // This is a requirement to support semaphore mechanism in register table.
  595. // Because if semaphore's dependence type is package type, semaphore will wait
  596. // for all Aps in one package finishing their tasks before set next register
  597. // for all APs. If the Aps not begin its task during BSP doing its task, the
  598. // BSP thread will hang because it is waiting for other Aps in the same
  599. // package finishing their task.
  600. //
  601. SetRegister (FALSE);
  602. while (mNumberToFinish > 0) {
  603. CpuPause ();
  604. }
  605. }
  606. /**
  607. Restore SMM Configuration in S3 boot path.
  608. **/
  609. VOID
  610. RestoreSmmConfigurationInS3 (
  611. VOID
  612. )
  613. {
  614. if (!mAcpiS3Enable) {
  615. return;
  616. }
  617. //
  618. // Restore SMM Configuration in S3 boot path.
  619. //
  620. if (mRestoreSmmConfigurationInS3) {
  621. //
  622. // Need make sure gSmst is correct because below function may use them.
  623. //
  624. gSmst->SmmStartupThisAp = gSmmCpuPrivate->SmmCoreEntryContext.SmmStartupThisAp;
  625. gSmst->CurrentlyExecutingCpu = gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu;
  626. gSmst->NumberOfCpus = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
  627. gSmst->CpuSaveStateSize = gSmmCpuPrivate->SmmCoreEntryContext.CpuSaveStateSize;
  628. gSmst->CpuSaveState = gSmmCpuPrivate->SmmCoreEntryContext.CpuSaveState;
  629. //
  630. // Configure SMM Code Access Check feature if available.
  631. //
  632. ConfigSmmCodeAccessCheck ();
  633. SmmCpuFeaturesCompleteSmmReadyToLock ();
  634. mRestoreSmmConfigurationInS3 = FALSE;
  635. }
  636. }
  637. /**
  638. Perform SMM initialization for all processors in the S3 boot path.
  639. For a native platform, MP initialization in the S3 boot path is also performed in this function.
  640. **/
  641. VOID
  642. EFIAPI
  643. SmmRestoreCpu (
  644. VOID
  645. )
  646. {
  647. SMM_S3_RESUME_STATE *SmmS3ResumeState;
  648. IA32_DESCRIPTOR Ia32Idtr;
  649. IA32_DESCRIPTOR X64Idtr;
  650. IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER];
  651. EFI_STATUS Status;
  652. DEBUG ((DEBUG_INFO, "SmmRestoreCpu()\n"));
  653. mSmmS3Flag = TRUE;
  654. //
  655. // See if there is enough context to resume PEI Phase
  656. //
  657. if (mSmmS3ResumeState == NULL) {
  658. DEBUG ((DEBUG_ERROR, "No context to return to PEI Phase\n"));
  659. CpuDeadLoop ();
  660. }
  661. SmmS3ResumeState = mSmmS3ResumeState;
  662. ASSERT (SmmS3ResumeState != NULL);
  663. //
  664. // Setup 64bit IDT in 64bit SMM env when called from 32bit PEI.
  665. // Note: 64bit PEI and 32bit DXE is not a supported combination.
  666. //
  667. if ((SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) && (FeaturePcdGet (PcdDxeIplSwitchToLongMode) == TRUE)) {
  668. //
  669. // Save the IA32 IDT Descriptor
  670. //
  671. AsmReadIdtr ((IA32_DESCRIPTOR *)&Ia32Idtr);
  672. //
  673. // Setup X64 IDT table
  674. //
  675. ZeroMem (IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32);
  676. X64Idtr.Base = (UINTN)IdtEntryTable;
  677. X64Idtr.Limit = (UINT16)(sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32 - 1);
  678. AsmWriteIdtr ((IA32_DESCRIPTOR *)&X64Idtr);
  679. //
  680. // Setup the default exception handler
  681. //
  682. Status = InitializeCpuExceptionHandlers (NULL);
  683. ASSERT_EFI_ERROR (Status);
  684. //
  685. // Initialize Debug Agent to support source level debug
  686. //
  687. InitializeDebugAgent (DEBUG_AGENT_INIT_THUNK_PEI_IA32TOX64, (VOID *)&Ia32Idtr, NULL);
  688. }
  689. //
  690. // Skip initialization if mAcpiCpuData is not valid
  691. //
  692. if (mAcpiCpuData.NumberOfCpus > 0) {
  693. //
  694. // First time microcode load and restore MTRRs
  695. //
  696. InitializeCpuBeforeRebase ();
  697. }
  698. //
  699. // Restore SMBASE for BSP and all APs
  700. //
  701. SmmRelocateBases ();
  702. //
  703. // Skip initialization if mAcpiCpuData is not valid
  704. //
  705. if (mAcpiCpuData.NumberOfCpus > 0) {
  706. //
  707. // Restore MSRs for BSP and all APs
  708. //
  709. InitializeCpuAfterRebase ();
  710. }
  711. //
  712. // Set a flag to restore SMM configuration in S3 path.
  713. //
  714. mRestoreSmmConfigurationInS3 = TRUE;
  715. DEBUG ((DEBUG_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs));
  716. DEBUG ((DEBUG_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint));
  717. DEBUG ((DEBUG_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1));
  718. DEBUG ((DEBUG_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2));
  719. DEBUG ((DEBUG_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer));
  720. //
  721. // If SMM is in 32-bit mode or PcdDxeIplSwitchToLongMode is FALSE, then use SwitchStack() to resume PEI Phase.
  722. // Note: 64bit PEI and 32bit DXE is not a supported combination.
  723. //
  724. if ((SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) || (FeaturePcdGet (PcdDxeIplSwitchToLongMode) == FALSE)) {
  725. DEBUG ((DEBUG_INFO, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));
  726. SwitchStack (
  727. (SWITCH_STACK_ENTRY_POINT)(UINTN)SmmS3ResumeState->ReturnEntryPoint,
  728. (VOID *)(UINTN)SmmS3ResumeState->ReturnContext1,
  729. (VOID *)(UINTN)SmmS3ResumeState->ReturnContext2,
  730. (VOID *)(UINTN)SmmS3ResumeState->ReturnStackPointer
  731. );
  732. }
  733. //
  734. // If SMM is in 64-bit mode, then use AsmDisablePaging64() to resume PEI Phase
  735. //
  736. if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {
  737. DEBUG ((DEBUG_INFO, "Call AsmDisablePaging64() to return to S3 Resume in PEI Phase\n"));
  738. //
  739. // Disable interrupt of Debug timer, since new IDT table is for IA32 and will not work in long mode.
  740. //
  741. SaveAndSetDebugTimerInterrupt (FALSE);
  742. //
  743. // Restore IA32 IDT table
  744. //
  745. AsmWriteIdtr ((IA32_DESCRIPTOR *)&Ia32Idtr);
  746. AsmDisablePaging64 (
  747. SmmS3ResumeState->ReturnCs,
  748. (UINT32)SmmS3ResumeState->ReturnEntryPoint,
  749. (UINT32)SmmS3ResumeState->ReturnContext1,
  750. (UINT32)SmmS3ResumeState->ReturnContext2,
  751. (UINT32)SmmS3ResumeState->ReturnStackPointer
  752. );
  753. }
  754. //
  755. // Can not resume PEI Phase
  756. //
  757. DEBUG ((DEBUG_ERROR, "No context to return to PEI Phase\n"));
  758. CpuDeadLoop ();
  759. }
  760. /**
  761. Initialize SMM S3 resume state structure used during S3 Resume.
  762. @param[in] Cr3 The base address of the page tables to use in SMM.
  763. **/
  764. VOID
  765. InitSmmS3ResumeState (
  766. IN UINT32 Cr3
  767. )
  768. {
  769. VOID *GuidHob;
  770. EFI_SMRAM_DESCRIPTOR *SmramDescriptor;
  771. SMM_S3_RESUME_STATE *SmmS3ResumeState;
  772. EFI_PHYSICAL_ADDRESS Address;
  773. EFI_STATUS Status;
  774. if (!mAcpiS3Enable) {
  775. return;
  776. }
  777. GuidHob = GetFirstGuidHob (&gEfiAcpiVariableGuid);
  778. if (GuidHob == NULL) {
  779. DEBUG ((
  780. DEBUG_ERROR,
  781. "ERROR:%a(): HOB(gEfiAcpiVariableGuid=%g) needed by S3 resume doesn't exist!\n",
  782. __FUNCTION__,
  783. &gEfiAcpiVariableGuid
  784. ));
  785. CpuDeadLoop ();
  786. } else {
  787. SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *)GET_GUID_HOB_DATA (GuidHob);
  788. DEBUG ((DEBUG_INFO, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor));
  789. DEBUG ((DEBUG_INFO, "SMM S3 Structure = %x\n", SmramDescriptor->CpuStart));
  790. SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart;
  791. ZeroMem (SmmS3ResumeState, sizeof (SMM_S3_RESUME_STATE));
  792. mSmmS3ResumeState = SmmS3ResumeState;
  793. SmmS3ResumeState->Smst = (EFI_PHYSICAL_ADDRESS)(UINTN)gSmst;
  794. SmmS3ResumeState->SmmS3ResumeEntryPoint = (EFI_PHYSICAL_ADDRESS)(UINTN)SmmRestoreCpu;
  795. SmmS3ResumeState->SmmS3StackSize = SIZE_32KB;
  796. SmmS3ResumeState->SmmS3StackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)SmmS3ResumeState->SmmS3StackSize));
  797. if (SmmS3ResumeState->SmmS3StackBase == 0) {
  798. SmmS3ResumeState->SmmS3StackSize = 0;
  799. }
  800. SmmS3ResumeState->SmmS3Cr0 = mSmmCr0;
  801. SmmS3ResumeState->SmmS3Cr3 = Cr3;
  802. SmmS3ResumeState->SmmS3Cr4 = mSmmCr4;
  803. if (sizeof (UINTN) == sizeof (UINT64)) {
  804. SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_64;
  805. }
  806. if (sizeof (UINTN) == sizeof (UINT32)) {
  807. SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_32;
  808. }
  809. //
  810. // Patch SmmS3ResumeState->SmmS3Cr3
  811. //
  812. InitSmmS3Cr3 ();
  813. }
  814. //
  815. // Allocate safe memory in ACPI NVS for AP to execute hlt loop in
  816. // protected mode on S3 path
  817. //
  818. Address = BASE_4GB - 1;
  819. Status = gBS->AllocatePages (
  820. AllocateMaxAddress,
  821. EfiACPIMemoryNVS,
  822. EFI_SIZE_TO_PAGES (sizeof (mApHltLoopCodeTemplate)),
  823. &Address
  824. );
  825. ASSERT_EFI_ERROR (Status);
  826. mApHltLoopCode = (UINT8 *)(UINTN)Address;
  827. }
  828. /**
  829. Copy register table from non-SMRAM into SMRAM.
  830. @param[in] DestinationRegisterTableList Points to destination register table.
  831. @param[in] SourceRegisterTableList Points to source register table.
  832. @param[in] NumberOfCpus Number of CPUs.
  833. **/
  834. VOID
  835. CopyRegisterTable (
  836. IN CPU_REGISTER_TABLE *DestinationRegisterTableList,
  837. IN CPU_REGISTER_TABLE *SourceRegisterTableList,
  838. IN UINT32 NumberOfCpus
  839. )
  840. {
  841. UINTN Index;
  842. CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
  843. CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
  844. for (Index = 0; Index < NumberOfCpus; Index++) {
  845. if (DestinationRegisterTableList[Index].TableLength != 0) {
  846. DestinationRegisterTableList[Index].AllocatedSize = DestinationRegisterTableList[Index].TableLength * sizeof (CPU_REGISTER_TABLE_ENTRY);
  847. RegisterTableEntry = AllocateCopyPool (
  848. DestinationRegisterTableList[Index].AllocatedSize,
  849. (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry
  850. );
  851. ASSERT (RegisterTableEntry != NULL);
  852. DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;
  853. }
  854. }
  855. }
  856. /**
  857. Check whether the register table is empty or not.
  858. @param[in] RegisterTable Point to the register table.
  859. @param[in] NumberOfCpus Number of CPUs.
  860. @retval TRUE The register table is empty.
  861. @retval FALSE The register table is not empty.
  862. **/
  863. BOOLEAN
  864. IsRegisterTableEmpty (
  865. IN CPU_REGISTER_TABLE *RegisterTable,
  866. IN UINT32 NumberOfCpus
  867. )
  868. {
  869. UINTN Index;
  870. if (RegisterTable != NULL) {
  871. for (Index = 0; Index < NumberOfCpus; Index++) {
  872. if (RegisterTable[Index].TableLength != 0) {
  873. return FALSE;
  874. }
  875. }
  876. }
  877. return TRUE;
  878. }
  879. /**
  880. Copy the data used to initialize processor register into SMRAM.
  881. @param[in,out] CpuFeatureInitDataDst Pointer to the destination CPU_FEATURE_INIT_DATA structure.
  882. @param[in] CpuFeatureInitDataSrc Pointer to the source CPU_FEATURE_INIT_DATA structure.
  883. **/
  884. VOID
  885. CopyCpuFeatureInitDatatoSmram (
  886. IN OUT CPU_FEATURE_INIT_DATA *CpuFeatureInitDataDst,
  887. IN CPU_FEATURE_INIT_DATA *CpuFeatureInitDataSrc
  888. )
  889. {
  890. CPU_STATUS_INFORMATION *CpuStatus;
  891. if (!IsRegisterTableEmpty ((CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataSrc->PreSmmInitRegisterTable, mAcpiCpuData.NumberOfCpus)) {
  892. CpuFeatureInitDataDst->PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
  893. ASSERT (CpuFeatureInitDataDst->PreSmmInitRegisterTable != 0);
  894. CopyRegisterTable (
  895. (CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataDst->PreSmmInitRegisterTable,
  896. (CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataSrc->PreSmmInitRegisterTable,
  897. mAcpiCpuData.NumberOfCpus
  898. );
  899. }
  900. if (!IsRegisterTableEmpty ((CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataSrc->RegisterTable, mAcpiCpuData.NumberOfCpus)) {
  901. CpuFeatureInitDataDst->RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
  902. ASSERT (CpuFeatureInitDataDst->RegisterTable != 0);
  903. CopyRegisterTable (
  904. (CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataDst->RegisterTable,
  905. (CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataSrc->RegisterTable,
  906. mAcpiCpuData.NumberOfCpus
  907. );
  908. }
  909. CpuStatus = &CpuFeatureInitDataDst->CpuStatus;
  910. CopyMem (CpuStatus, &CpuFeatureInitDataSrc->CpuStatus, sizeof (CPU_STATUS_INFORMATION));
  911. if (CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerPackage != 0) {
  912. CpuStatus->ThreadCountPerPackage = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool (
  913. sizeof (UINT32) * CpuStatus->PackageCount,
  914. (UINT32 *)(UINTN)CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerPackage
  915. );
  916. ASSERT (CpuStatus->ThreadCountPerPackage != 0);
  917. }
  918. if (CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerCore != 0) {
  919. CpuStatus->ThreadCountPerCore = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool (
  920. sizeof (UINT8) * (CpuStatus->PackageCount * CpuStatus->MaxCoreCount),
  921. (UINT32 *)(UINTN)CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerCore
  922. );
  923. ASSERT (CpuStatus->ThreadCountPerCore != 0);
  924. }
  925. if (CpuFeatureInitDataSrc->ApLocation != 0) {
  926. CpuFeatureInitDataDst->ApLocation = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool (
  927. mAcpiCpuData.NumberOfCpus * sizeof (EFI_CPU_PHYSICAL_LOCATION),
  928. (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)CpuFeatureInitDataSrc->ApLocation
  929. );
  930. ASSERT (CpuFeatureInitDataDst->ApLocation != 0);
  931. }
  932. }
  933. /**
  934. Get ACPI CPU data.
  935. **/
  936. VOID
  937. GetAcpiCpuData (
  938. VOID
  939. )
  940. {
  941. ACPI_CPU_DATA *AcpiCpuData;
  942. IA32_DESCRIPTOR *Gdtr;
  943. IA32_DESCRIPTOR *Idtr;
  944. VOID *GdtForAp;
  945. VOID *IdtForAp;
  946. VOID *MachineCheckHandlerForAp;
  947. CPU_STATUS_INFORMATION *CpuStatus;
  948. if (!mAcpiS3Enable) {
  949. return;
  950. }
  951. //
  952. // Prevent use of mAcpiCpuData by initialize NumberOfCpus to 0
  953. //
  954. mAcpiCpuData.NumberOfCpus = 0;
  955. //
  956. // If PcdCpuS3DataAddress was never set, then do not copy CPU S3 Data into SMRAM
  957. //
  958. AcpiCpuData = (ACPI_CPU_DATA *)(UINTN)PcdGet64 (PcdCpuS3DataAddress);
  959. if (AcpiCpuData == 0) {
  960. return;
  961. }
  962. //
  963. // For a native platform, copy the CPU S3 data into SMRAM for use on CPU S3 Resume.
  964. //
  965. CopyMem (&mAcpiCpuData, AcpiCpuData, sizeof (mAcpiCpuData));
  966. mAcpiCpuData.MtrrTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (MTRR_SETTINGS));
  967. ASSERT (mAcpiCpuData.MtrrTable != 0);
  968. CopyMem ((VOID *)(UINTN)mAcpiCpuData.MtrrTable, (VOID *)(UINTN)AcpiCpuData->MtrrTable, sizeof (MTRR_SETTINGS));
  969. mAcpiCpuData.GdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (IA32_DESCRIPTOR));
  970. ASSERT (mAcpiCpuData.GdtrProfile != 0);
  971. CopyMem ((VOID *)(UINTN)mAcpiCpuData.GdtrProfile, (VOID *)(UINTN)AcpiCpuData->GdtrProfile, sizeof (IA32_DESCRIPTOR));
  972. mAcpiCpuData.IdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (IA32_DESCRIPTOR));
  973. ASSERT (mAcpiCpuData.IdtrProfile != 0);
  974. CopyMem ((VOID *)(UINTN)mAcpiCpuData.IdtrProfile, (VOID *)(UINTN)AcpiCpuData->IdtrProfile, sizeof (IA32_DESCRIPTOR));
  975. //
  976. // Copy AP's GDT, IDT and Machine Check handler into SMRAM.
  977. //
  978. Gdtr = (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.GdtrProfile;
  979. Idtr = (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.IdtrProfile;
  980. GdtForAp = AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + mAcpiCpuData.ApMachineCheckHandlerSize);
  981. ASSERT (GdtForAp != NULL);
  982. IdtForAp = (VOID *)((UINTN)GdtForAp + (Gdtr->Limit + 1));
  983. MachineCheckHandlerForAp = (VOID *)((UINTN)IdtForAp + (Idtr->Limit + 1));
  984. CopyMem (GdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1);
  985. CopyMem (IdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1);
  986. CopyMem (MachineCheckHandlerForAp, (VOID *)(UINTN)mAcpiCpuData.ApMachineCheckHandlerBase, mAcpiCpuData.ApMachineCheckHandlerSize);
  987. Gdtr->Base = (UINTN)GdtForAp;
  988. Idtr->Base = (UINTN)IdtForAp;
  989. mAcpiCpuData.ApMachineCheckHandlerBase = (EFI_PHYSICAL_ADDRESS)(UINTN)MachineCheckHandlerForAp;
  990. ZeroMem (&mAcpiCpuData.CpuFeatureInitData, sizeof (CPU_FEATURE_INIT_DATA));
  991. if (!PcdGetBool (PcdCpuFeaturesInitOnS3Resume)) {
  992. //
  993. // If the CPU features will not be initialized by CpuFeaturesPei module during
  994. // next ACPI S3 resume, copy the CPU features initialization data into SMRAM,
  995. // which will be consumed in SmmRestoreCpu during next S3 resume.
  996. //
  997. CopyCpuFeatureInitDatatoSmram (&mAcpiCpuData.CpuFeatureInitData, &AcpiCpuData->CpuFeatureInitData);
  998. CpuStatus = &mAcpiCpuData.CpuFeatureInitData.CpuStatus;
  999. mCpuFlags.CoreSemaphoreCount = AllocateZeroPool (
  1000. sizeof (UINT32) * CpuStatus->PackageCount *
  1001. CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount
  1002. );
  1003. ASSERT (mCpuFlags.CoreSemaphoreCount != NULL);
  1004. mCpuFlags.PackageSemaphoreCount = AllocateZeroPool (
  1005. sizeof (UINT32) * CpuStatus->PackageCount *
  1006. CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount
  1007. );
  1008. ASSERT (mCpuFlags.PackageSemaphoreCount != NULL);
  1009. InitializeSpinLock ((SPIN_LOCK *)&mCpuFlags.MemoryMappedLock);
  1010. }
  1011. }
  1012. /**
  1013. Get ACPI S3 enable flag.
  1014. **/
  1015. VOID
  1016. GetAcpiS3EnableFlag (
  1017. VOID
  1018. )
  1019. {
  1020. mAcpiS3Enable = PcdGetBool (PcdAcpiS3Enable);
  1021. }