Omap3530PadConfiguration.h 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297
  1. /** @file
  2. Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #ifndef __OMAP3530_PAD_CONFIGURATION_H__
  6. #define __OMAP3530_PAD_CONFIGURATION_H__
  7. #define SYSTEM_CONTROL_MODULE_BASE 0x48002000
  8. //Pin definition
  9. #define SDRC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x030)
  10. #define SDRC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x032)
  11. #define SDRC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x034)
  12. #define SDRC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x036)
  13. #define SDRC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x038)
  14. #define SDRC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x03A)
  15. #define SDRC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x03C)
  16. #define SDRC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x03E)
  17. #define SDRC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x040)
  18. #define SDRC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x042)
  19. #define SDRC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x044)
  20. #define SDRC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x046)
  21. #define SDRC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x048)
  22. #define SDRC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x04A)
  23. #define SDRC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x04C)
  24. #define SDRC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x04E)
  25. #define SDRC_D16 (SYSTEM_CONTROL_MODULE_BASE + 0x050)
  26. #define SDRC_D17 (SYSTEM_CONTROL_MODULE_BASE + 0x052)
  27. #define SDRC_D18 (SYSTEM_CONTROL_MODULE_BASE + 0x054)
  28. #define SDRC_D19 (SYSTEM_CONTROL_MODULE_BASE + 0x056)
  29. #define SDRC_D20 (SYSTEM_CONTROL_MODULE_BASE + 0x058)
  30. #define SDRC_D21 (SYSTEM_CONTROL_MODULE_BASE + 0x05A)
  31. #define SDRC_D22 (SYSTEM_CONTROL_MODULE_BASE + 0x05C)
  32. #define SDRC_D23 (SYSTEM_CONTROL_MODULE_BASE + 0x05E)
  33. #define SDRC_D24 (SYSTEM_CONTROL_MODULE_BASE + 0x060)
  34. #define SDRC_D25 (SYSTEM_CONTROL_MODULE_BASE + 0x062)
  35. #define SDRC_D26 (SYSTEM_CONTROL_MODULE_BASE + 0x064)
  36. #define SDRC_D27 (SYSTEM_CONTROL_MODULE_BASE + 0x066)
  37. #define SDRC_D28 (SYSTEM_CONTROL_MODULE_BASE + 0x068)
  38. #define SDRC_D29 (SYSTEM_CONTROL_MODULE_BASE + 0x06A)
  39. #define SDRC_D30 (SYSTEM_CONTROL_MODULE_BASE + 0x06C)
  40. #define SDRC_D31 (SYSTEM_CONTROL_MODULE_BASE + 0x06E)
  41. #define SDRC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x070)
  42. #define SDRC_DQS0 (SYSTEM_CONTROL_MODULE_BASE + 0x072)
  43. #define SDRC_CKE0 (SYSTEM_CONTROL_MODULE_BASE + 0x262)
  44. #define SDRC_CKE1 (SYSTEM_CONTROL_MODULE_BASE + 0x264)
  45. #define SDRC_DQS1 (SYSTEM_CONTROL_MODULE_BASE + 0x074)
  46. #define SDRC_DQS2 (SYSTEM_CONTROL_MODULE_BASE + 0x076)
  47. #define SDRC_DQS3 (SYSTEM_CONTROL_MODULE_BASE + 0x078)
  48. #define GPMC_A1 (SYSTEM_CONTROL_MODULE_BASE + 0x07A)
  49. #define GPMC_A2 (SYSTEM_CONTROL_MODULE_BASE + 0x07C)
  50. #define GPMC_A3 (SYSTEM_CONTROL_MODULE_BASE + 0x07E)
  51. #define GPMC_A4 (SYSTEM_CONTROL_MODULE_BASE + 0x080)
  52. #define GPMC_A5 (SYSTEM_CONTROL_MODULE_BASE + 0x082)
  53. #define GPMC_A6 (SYSTEM_CONTROL_MODULE_BASE + 0x084)
  54. #define GPMC_A7 (SYSTEM_CONTROL_MODULE_BASE + 0x086)
  55. #define GPMC_A8 (SYSTEM_CONTROL_MODULE_BASE + 0x088)
  56. #define GPMC_A9 (SYSTEM_CONTROL_MODULE_BASE + 0x08A)
  57. #define GPMC_A10 (SYSTEM_CONTROL_MODULE_BASE + 0x08C)
  58. #define GPMC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x08E)
  59. #define GPMC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x090)
  60. #define GPMC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x092)
  61. #define GPMC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x094)
  62. #define GPMC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x096)
  63. #define GPMC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x098)
  64. #define GPMC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x09A)
  65. #define GPMC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x09C)
  66. #define GPMC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x09E)
  67. #define GPMC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x0A0)
  68. #define GPMC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x0A2)
  69. #define GPMC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x0A4)
  70. #define GPMC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x0A6)
  71. #define GPMC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x0A8)
  72. #define GPMC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x0AA)
  73. #define GPMC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x0AC)
  74. #define GPMC_NCS0 (SYSTEM_CONTROL_MODULE_BASE + 0x0AE)
  75. #define GPMC_NCS1 (SYSTEM_CONTROL_MODULE_BASE + 0x0B0)
  76. #define GPMC_NCS2 (SYSTEM_CONTROL_MODULE_BASE + 0x0B2)
  77. #define GPMC_NCS3 (SYSTEM_CONTROL_MODULE_BASE + 0x0B4)
  78. #define GPMC_NCS4 (SYSTEM_CONTROL_MODULE_BASE + 0x0B6)
  79. #define GPMC_NCS5 (SYSTEM_CONTROL_MODULE_BASE + 0x0B8)
  80. #define GPMC_NCS6 (SYSTEM_CONTROL_MODULE_BASE + 0x0BA)
  81. #define GPMC_NCS7 (SYSTEM_CONTROL_MODULE_BASE + 0x0BC)
  82. #define GPMC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x0BE)
  83. #define GPMC_NADV_ALE (SYSTEM_CONTROL_MODULE_BASE + 0x0C0)
  84. #define GPMC_NOE (SYSTEM_CONTROL_MODULE_BASE + 0x0C2)
  85. #define GPMC_NWE (SYSTEM_CONTROL_MODULE_BASE + 0x0C4)
  86. #define GPMC_NBE0_CLE (SYSTEM_CONTROL_MODULE_BASE + 0x0C6)
  87. #define GPMC_NBE1 (SYSTEM_CONTROL_MODULE_BASE + 0x0C8)
  88. #define GPMC_NWP (SYSTEM_CONTROL_MODULE_BASE + 0x0CA)
  89. #define GPMC_WAIT0 (SYSTEM_CONTROL_MODULE_BASE + 0x0CC)
  90. #define GPMC_WAIT1 (SYSTEM_CONTROL_MODULE_BASE + 0x0CE)
  91. #define GPMC_WAIT2 (SYSTEM_CONTROL_MODULE_BASE + 0x0D0)
  92. #define GPMC_WAIT3 (SYSTEM_CONTROL_MODULE_BASE + 0x0D2)
  93. #define DSS_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x0D4)
  94. #define DSS_HSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D6)
  95. #define DSS_PSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D8)
  96. #define DSS_ACBIAS (SYSTEM_CONTROL_MODULE_BASE + 0x0DA)
  97. #define DSS_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x0DC)
  98. #define DSS_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x0DE)
  99. #define DSS_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x0E0)
  100. #define DSS_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x0E2)
  101. #define DSS_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x0E4)
  102. #define DSS_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x0E6)
  103. #define DSS_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x0E8)
  104. #define DSS_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x0EA)
  105. #define DSS_DATA8 (SYSTEM_CONTROL_MODULE_BASE + 0x0EC)
  106. #define DSS_DATA9 (SYSTEM_CONTROL_MODULE_BASE + 0x0EE)
  107. #define DSS_DATA10 (SYSTEM_CONTROL_MODULE_BASE + 0x0F0)
  108. #define DSS_DATA11 (SYSTEM_CONTROL_MODULE_BASE + 0x0F2)
  109. #define DSS_DATA12 (SYSTEM_CONTROL_MODULE_BASE + 0x0F4)
  110. #define DSS_DATA13 (SYSTEM_CONTROL_MODULE_BASE + 0x0F6)
  111. #define DSS_DATA14 (SYSTEM_CONTROL_MODULE_BASE + 0x0F8)
  112. #define DSS_DATA15 (SYSTEM_CONTROL_MODULE_BASE + 0x0FA)
  113. #define DSS_DATA16 (SYSTEM_CONTROL_MODULE_BASE + 0x0FC)
  114. #define DSS_DATA17 (SYSTEM_CONTROL_MODULE_BASE + 0x0FE)
  115. #define DSS_DATA18 (SYSTEM_CONTROL_MODULE_BASE + 0x100)
  116. #define DSS_DATA19 (SYSTEM_CONTROL_MODULE_BASE + 0x102)
  117. #define DSS_DATA20 (SYSTEM_CONTROL_MODULE_BASE + 0x104)
  118. #define DSS_DATA21 (SYSTEM_CONTROL_MODULE_BASE + 0x106)
  119. #define DSS_DATA22 (SYSTEM_CONTROL_MODULE_BASE + 0x108)
  120. #define DSS_DATA23 (SYSTEM_CONTROL_MODULE_BASE + 0x10A)
  121. #define CAM_HS (SYSTEM_CONTROL_MODULE_BASE + 0x10C)
  122. #define CAM_VS (SYSTEM_CONTROL_MODULE_BASE + 0x10E)
  123. #define CAM_XCLKA (SYSTEM_CONTROL_MODULE_BASE + 0x110)
  124. #define CAM_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x112)
  125. #define CAM_FLD (SYSTEM_CONTROL_MODULE_BASE + 0x114)
  126. #define CAM_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x116)
  127. #define CAM_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x118)
  128. #define CAM_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x11A)
  129. #define CAM_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x11C)
  130. #define CAM_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x11E)
  131. #define CAM_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x120)
  132. #define CAM_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x122)
  133. #define CAM_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x124)
  134. #define CAM_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x126)
  135. #define CAM_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x128)
  136. #define CAM_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x12A)
  137. #define CAM_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x12C)
  138. #define CAM_XCLKB (SYSTEM_CONTROL_MODULE_BASE + 0x12E)
  139. #define CAM_WEN (SYSTEM_CONTROL_MODULE_BASE + 0x130)
  140. #define CAM_STROBE (SYSTEM_CONTROL_MODULE_BASE + 0x132)
  141. #define CSI2_DX0 (SYSTEM_CONTROL_MODULE_BASE + 0x134)
  142. #define CSI2_DY0 (SYSTEM_CONTROL_MODULE_BASE + 0x136)
  143. #define CSI2_DX1 (SYSTEM_CONTROL_MODULE_BASE + 0x138)
  144. #define CSI2_DY1 (SYSTEM_CONTROL_MODULE_BASE + 0x13A)
  145. #define MCBSP2_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x13C)
  146. #define MCBSP2_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x13E)
  147. #define MCBSP2_DR (SYSTEM_CONTROL_MODULE_BASE + 0x140)
  148. #define MCBSP2_DX (SYSTEM_CONTROL_MODULE_BASE + 0x142)
  149. #define MMC1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x144)
  150. #define MMC1_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x146)
  151. #define MMC1_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x148)
  152. #define MMC1_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x14A)
  153. #define MMC1_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x14C)
  154. #define MMC1_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x14E)
  155. #define MMC1_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x150)
  156. #define MMC1_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x152)
  157. #define MMC1_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x154)
  158. #define MMC1_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x156)
  159. #define MMC2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x158)
  160. #define MMC2_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x15A)
  161. #define MMC2_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x15C)
  162. #define MMC2_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x15E)
  163. #define MMC2_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x160)
  164. #define MMC2_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x162)
  165. #define MMC2_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x164)
  166. #define MMC2_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x166)
  167. #define MMC2_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x168)
  168. #define MMC2_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x16A)
  169. #define MCBSP3_DX (SYSTEM_CONTROL_MODULE_BASE + 0x16C)
  170. #define MCBSP3_DR (SYSTEM_CONTROL_MODULE_BASE + 0x16E)
  171. #define MCBSP3_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x170)
  172. #define MCBSP3_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x172)
  173. #define UART2_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x174)
  174. #define UART2_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x176)
  175. #define UART2_TX (SYSTEM_CONTROL_MODULE_BASE + 0x178)
  176. #define UART2_RX (SYSTEM_CONTROL_MODULE_BASE + 0x17A)
  177. #define UART1_TX (SYSTEM_CONTROL_MODULE_BASE + 0x17C)
  178. #define UART1_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x17E)
  179. #define UART1_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x180)
  180. #define UART1_RX (SYSTEM_CONTROL_MODULE_BASE + 0x182)
  181. #define MCBSP4_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x184)
  182. #define MCBSP4_DR (SYSTEM_CONTROL_MODULE_BASE + 0x186)
  183. #define MCBSP4_DX (SYSTEM_CONTROL_MODULE_BASE + 0x188)
  184. #define MCBSP4_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x18A)
  185. #define MCBSP1_CLKR (SYSTEM_CONTROL_MODULE_BASE + 0x18C)
  186. #define MCBSP1_FSR (SYSTEM_CONTROL_MODULE_BASE + 0x18E)
  187. #define MCBSP1_DX (SYSTEM_CONTROL_MODULE_BASE + 0x190)
  188. #define MCBSP1_DR (SYSTEM_CONTROL_MODULE_BASE + 0x192)
  189. #define MCBSP1_CLKS (SYSTEM_CONTROL_MODULE_BASE + 0x194)
  190. #define MCBSP1_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x196)
  191. #define MCBSP1_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x198)
  192. #define UART3_CTS_RCTX (SYSTEM_CONTROL_MODULE_BASE + 0x19A)
  193. #define UART3_RTS_SD (SYSTEM_CONTROL_MODULE_BASE + 0x19C)
  194. #define UART3_RX_IRRX (SYSTEM_CONTROL_MODULE_BASE + 0x19E)
  195. #define UART3_TX_IRTX (SYSTEM_CONTROL_MODULE_BASE + 0x1A0)
  196. #define HSUSB0_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1A2)
  197. #define HSUSB0_STP (SYSTEM_CONTROL_MODULE_BASE + 0x1A4)
  198. #define HSUSB0_DIR (SYSTEM_CONTROL_MODULE_BASE + 0x1A6)
  199. #define HSUSB0_NXT (SYSTEM_CONTROL_MODULE_BASE + 0x1A8)
  200. #define HSUSB0_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x1AA)
  201. #define HSUSB0_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x1AC)
  202. #define HSUSB0_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x1AE)
  203. #define HSUSB0_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x1B0)
  204. #define HSUSB0_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x1B2)
  205. #define HSUSB0_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x1B4)
  206. #define HSUSB0_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x1B6)
  207. #define HSUSB0_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x1B8)
  208. #define I2C1_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BA)
  209. #define I2C1_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1BC)
  210. #define I2C2_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BE)
  211. #define I2C2_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C0)
  212. #define I2C3_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1C2)
  213. #define I2C3_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C4)
  214. #define HDQ_SIO (SYSTEM_CONTROL_MODULE_BASE + 0x1C6)
  215. #define MCSPI1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1C8)
  216. #define MCSPI1_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1CA)
  217. #define MCSPI1_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1CC)
  218. #define MCSPI1_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1CE)
  219. #define MCSPI1_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1D0)
  220. #define MCSPI1_CS2 (SYSTEM_CONTROL_MODULE_BASE + 0x1D2)
  221. #define MCSPI1_CS3 (SYSTEM_CONTROL_MODULE_BASE + 0x1D4)
  222. #define MCSPI2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1D6)
  223. #define MCSPI2_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1D8)
  224. #define MCSPI2_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1DA)
  225. #define MCSPI2_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1DC)
  226. #define MCSPI2_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1DE)
  227. #define SYS_NIRQ (SYSTEM_CONTROL_MODULE_BASE + 0x1E0)
  228. #define SYS_CLKOUT2 (SYSTEM_CONTROL_MODULE_BASE + 0x1E2)
  229. #define ETK_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x5D8)
  230. #define ETK_CTL (SYSTEM_CONTROL_MODULE_BASE + 0x5DA)
  231. #define ETK_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x5DC)
  232. #define ETK_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x5DE)
  233. #define ETK_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x5E0)
  234. #define ETK_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x5E2)
  235. #define ETK_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x5E4)
  236. #define ETK_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x5E6)
  237. #define ETK_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x5E8)
  238. #define ETK_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x5EA)
  239. #define ETK_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x5EC)
  240. #define ETK_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x5EE)
  241. #define ETK_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x5F0)
  242. #define ETK_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x5F2)
  243. #define ETK_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x5F4)
  244. #define ETK_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x5F6)
  245. #define ETK_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x5F8)
  246. #define ETK_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x5FA)
  247. #define SYS_BOOT0 (SYSTEM_CONTROL_MODULE_BASE + 0xA0A)
  248. #define SYS_BOOT1 (SYSTEM_CONTROL_MODULE_BASE + 0xA0C)
  249. #define SYS_BOOT3 (SYSTEM_CONTROL_MODULE_BASE + 0xA10)
  250. #define SYS_BOOT4 (SYSTEM_CONTROL_MODULE_BASE + 0xA12)
  251. #define SYS_BOOT5 (SYSTEM_CONTROL_MODULE_BASE + 0xA14)
  252. #define SYS_BOOT6 (SYSTEM_CONTROL_MODULE_BASE + 0xA16)
  253. //Mux modes
  254. #define MUXMODE0 (0x0UL)
  255. #define MUXMODE1 (0x1UL)
  256. #define MUXMODE2 (0x2UL)
  257. #define MUXMODE3 (0x3UL)
  258. #define MUXMODE4 (0x4UL)
  259. #define MUXMODE5 (0x5UL)
  260. #define MUXMODE6 (0x6UL)
  261. #define MUXMODE7 (0x7UL)
  262. //Pad configuration register.
  263. #define PAD_CONFIG_MASK (0xFFFFUL)
  264. #define MUXMODE_OFFSET 0
  265. #define MUXMODE_MASK (0x7UL << MUXMODE_OFFSET)
  266. #define PULL_CONFIG_OFFSET 3
  267. #define PULL_CONFIG_MASK (0x3UL << PULL_CONFIG_OFFSET)
  268. #define INPUTENABLE_OFFSET 8
  269. #define INPUTENABLE_MASK (0x1UL << INPUTENABLE_OFFSET)
  270. #define OFFMODE_VALUE_OFFSET 9
  271. #define OFFMODE_VALUE_MASK (0x1FUL << OFFMODE_VALUE_OFFSET)
  272. #define WAKEUP_OFFSET 14
  273. #define WAKEUP_MASK (0x2UL << WAKEUP_OFFSET)
  274. #define PULL_DOWN_SELECTED ((0x0UL << 1) | BIT0)
  275. #define PULL_UP_SELECTED (BIT1 | BIT0)
  276. #define PULL_DISABLED (0x0UL << 0)
  277. #define OUTPUT (0x0UL) //Pin is configured in output only mode.
  278. #define INPUT (0x1UL) //Pin is configured in bi-directional mode.
  279. typedef struct {
  280. UINTN Pin;
  281. UINTN MuxMode;
  282. UINTN PullConfig;
  283. UINTN InputEnable;
  284. } PAD_CONFIGURATION;
  285. #endif //__OMAP3530_PAD_CONFIGURATION_H__