Omap3530MMCHS.h 7.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208
  1. /** @file
  2. Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #ifndef __OMAP3530SDIO_H__
  6. #define __OMAP3530SDIO_H__
  7. //MMC/SD/SDIO1 register definitions.
  8. #define MMCHS1BASE 0x4809C000
  9. #define MMC_REFERENCE_CLK (96000000)
  10. #define MMCHS_SYSCONFIG (MMCHS1BASE + 0x10)
  11. #define SOFTRESET BIT1
  12. #define ENAWAKEUP BIT2
  13. #define MMCHS_SYSSTATUS (MMCHS1BASE + 0x14)
  14. #define RESETDONE_MASK BIT0
  15. #define RESETDONE BIT0
  16. #define MMCHS_CSRE (MMCHS1BASE + 0x24)
  17. #define MMCHS_SYSTEST (MMCHS1BASE + 0x28)
  18. #define MMCHS_CON (MMCHS1BASE + 0x2C)
  19. #define OD BIT0
  20. #define NOINIT (0x0UL << 1)
  21. #define INIT BIT1
  22. #define HR BIT2
  23. #define STR BIT3
  24. #define MODE BIT4
  25. #define DW8_1_4_BIT (0x0UL << 5)
  26. #define DW8_8_BIT BIT5
  27. #define MIT BIT6
  28. #define CDP BIT7
  29. #define WPP BIT8
  30. #define CTPL BIT11
  31. #define CEATA_OFF (0x0UL << 12)
  32. #define CEATA_ON BIT12
  33. #define MMCHS_PWCNT (MMCHS1BASE + 0x30)
  34. #define MMCHS_BLK (MMCHS1BASE + 0x104)
  35. #define BLEN_512BYTES (0x200UL << 0)
  36. #define MMCHS_ARG (MMCHS1BASE + 0x108)
  37. #define MMCHS_CMD (MMCHS1BASE + 0x10C)
  38. #define DE_ENABLE BIT0
  39. #define BCE_ENABLE BIT1
  40. #define ACEN_ENABLE BIT2
  41. #define DDIR_READ BIT4
  42. #define DDIR_WRITE (0x0UL << 4)
  43. #define MSBS_SGLEBLK (0x0UL << 5)
  44. #define MSBS_MULTBLK BIT5
  45. #define RSP_TYPE_MASK (0x3UL << 16)
  46. #define RSP_TYPE_136BITS BIT16
  47. #define RSP_TYPE_48BITS (0x2UL << 16)
  48. #define CCCE_ENABLE BIT19
  49. #define CICE_ENABLE BIT20
  50. #define DP_ENABLE BIT21
  51. #define INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24)
  52. #define MMCHS_RSP10 (MMCHS1BASE + 0x110)
  53. #define MMCHS_RSP32 (MMCHS1BASE + 0x114)
  54. #define MMCHS_RSP54 (MMCHS1BASE + 0x118)
  55. #define MMCHS_RSP76 (MMCHS1BASE + 0x11C)
  56. #define MMCHS_DATA (MMCHS1BASE + 0x120)
  57. #define MMCHS_PSTATE (MMCHS1BASE + 0x124)
  58. #define CMDI_MASK BIT0
  59. #define CMDI_ALLOWED (0x0UL << 0)
  60. #define CMDI_NOT_ALLOWED BIT0
  61. #define DATI_MASK BIT1
  62. #define DATI_ALLOWED (0x0UL << 1)
  63. #define DATI_NOT_ALLOWED BIT1
  64. #define MMCHS_HCTL (MMCHS1BASE + 0x128)
  65. #define DTW_1_BIT (0x0UL << 1)
  66. #define DTW_4_BIT BIT1
  67. #define SDBP_MASK BIT8
  68. #define SDBP_OFF (0x0UL << 8)
  69. #define SDBP_ON BIT8
  70. #define SDVS_1_8_V (0x5UL << 9)
  71. #define SDVS_3_0_V (0x6UL << 9)
  72. #define IWE BIT24
  73. #define MMCHS_SYSCTL (MMCHS1BASE + 0x12C)
  74. #define ICE BIT0
  75. #define ICS_MASK BIT1
  76. #define ICS BIT1
  77. #define CEN BIT2
  78. #define CLKD_MASK (0x3FFUL << 6)
  79. #define CLKD_80KHZ (0x258UL) //(96*1000/80)/2
  80. #define CLKD_400KHZ (0xF0UL)
  81. #define DTO_MASK (0xFUL << 16)
  82. #define DTO_VAL (0xEUL << 16)
  83. #define SRA BIT24
  84. #define SRC_MASK BIT25
  85. #define SRC BIT25
  86. #define SRD BIT26
  87. #define MMCHS_STAT (MMCHS1BASE + 0x130)
  88. #define CC BIT0
  89. #define TC BIT1
  90. #define BWR BIT4
  91. #define BRR BIT5
  92. #define ERRI BIT15
  93. #define CTO BIT16
  94. #define DTO BIT20
  95. #define DCRC BIT21
  96. #define DEB BIT22
  97. #define MMCHS_IE (MMCHS1BASE + 0x134)
  98. #define CC_EN BIT0
  99. #define TC_EN BIT1
  100. #define BWR_EN BIT4
  101. #define BRR_EN BIT5
  102. #define CTO_EN BIT16
  103. #define CCRC_EN BIT17
  104. #define CEB_EN BIT18
  105. #define CIE_EN BIT19
  106. #define DTO_EN BIT20
  107. #define DCRC_EN BIT21
  108. #define DEB_EN BIT22
  109. #define CERR_EN BIT28
  110. #define BADA_EN BIT29
  111. #define MMCHS_ISE (MMCHS1BASE + 0x138)
  112. #define CC_SIGEN BIT0
  113. #define TC_SIGEN BIT1
  114. #define BWR_SIGEN BIT4
  115. #define BRR_SIGEN BIT5
  116. #define CTO_SIGEN BIT16
  117. #define CCRC_SIGEN BIT17
  118. #define CEB_SIGEN BIT18
  119. #define CIE_SIGEN BIT19
  120. #define DTO_SIGEN BIT20
  121. #define DCRC_SIGEN BIT21
  122. #define DEB_SIGEN BIT22
  123. #define CERR_SIGEN BIT28
  124. #define BADA_SIGEN BIT29
  125. #define MMCHS_AC12 (MMCHS1BASE + 0x13C)
  126. #define MMCHS_CAPA (MMCHS1BASE + 0x140)
  127. #define VS30 BIT25
  128. #define VS18 BIT26
  129. #define MMCHS_CUR_CAPA (MMCHS1BASE + 0x148)
  130. #define MMCHS_REV (MMCHS1BASE + 0x1FC)
  131. #define CMD0 INDX(0)
  132. #define CMD0_INT_EN (CC_EN | CEB_EN)
  133. #define CMD1 (INDX(1) | RSP_TYPE_48BITS)
  134. #define CMD1_INT_EN (CC_EN | CEB_EN | CTO_EN)
  135. #define CMD2 (INDX(2) | CCCE_ENABLE | RSP_TYPE_136BITS)
  136. #define CMD2_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
  137. #define CMD3 (INDX(3) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
  138. #define CMD3_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
  139. #define CMD5 (INDX(5) | RSP_TYPE_48BITS)
  140. #define CMD5_INT_EN (CC_EN | CEB_EN | CTO_EN)
  141. #define CMD7 (INDX(7) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
  142. #define CMD7_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
  143. #define CMD8 (INDX(8) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
  144. #define CMD8_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
  145. //Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE
  146. #define CMD8_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0)
  147. #define CMD9 (INDX(9) | CCCE_ENABLE | RSP_TYPE_136BITS)
  148. #define CMD9_INT_EN (CCRC_EN | CC_EN | CEB_EN | CTO_EN)
  149. #define CMD16 (INDX(16) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
  150. #define CMD16_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
  151. #define CMD17 (INDX(17) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_READ)
  152. #define CMD17_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
  153. #define CMD18 (INDX(18) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)
  154. #define CMD18_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
  155. #define CMD23 (INDX(23) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
  156. #define CMD23_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
  157. #define CMD24 (INDX(24) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_WRITE)
  158. #define CMD24_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BWR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
  159. #define CMD25 (INDX(25) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)
  160. #define CMD25_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
  161. #define CMD55 (INDX(55) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
  162. #define CMD55_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
  163. #define ACMD41 (INDX(41) | RSP_TYPE_48BITS)
  164. #define ACMD41_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
  165. #define ACMD6 (INDX(6) | RSP_TYPE_48BITS)
  166. #define ACMD6_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
  167. #endif //__OMAP3530SDIO_H__