Omap3530Gpmc.h 3.4 KB

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  1. /** @file
  2. Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #ifndef __OMAP3530GPMC_H__
  6. #define __OMAP3530GPMC_H__
  7. #define GPMC_BASE (0x6E000000)
  8. //GPMC NAND definitions.
  9. #define GPMC_SYSCONFIG (GPMC_BASE + 0x10)
  10. #define SMARTIDLEMODE (0x2UL << 3)
  11. #define GPMC_SYSSTATUS (GPMC_BASE + 0x14)
  12. #define GPMC_IRQSTATUS (GPMC_BASE + 0x18)
  13. #define GPMC_IRQENABLE (GPMC_BASE + 0x1C)
  14. #define GPMC_TIMEOUT_CONTROL (GPMC_BASE + 0x40)
  15. #define TIMEOUTENABLE BIT0
  16. #define TIMEOUTDISABLE (0x0UL << 0)
  17. #define GPMC_ERR_ADDRESS (GPMC_BASE + 0x44)
  18. #define GPMC_ERR_TYPE (GPMC_BASE + 0x48)
  19. #define GPMC_CONFIG (GPMC_BASE + 0x50)
  20. #define WRITEPROTECT_HIGH BIT4
  21. #define WRITEPROTECT_LOW (0x0UL << 4)
  22. #define GPMC_STATUS (GPMC_BASE + 0x54)
  23. #define GPMC_CONFIG1_0 (GPMC_BASE + 0x60)
  24. #define DEVICETYPE_NOR (0x0UL << 10)
  25. #define DEVICETYPE_NAND (0x2UL << 10)
  26. #define DEVICESIZE_X8 (0x0UL << 12)
  27. #define DEVICESIZE_X16 BIT12
  28. #define GPMC_CONFIG2_0 (GPMC_BASE + 0x64)
  29. #define CSONTIME (0x0UL << 0)
  30. #define CSRDOFFTIME (0x14UL << 8)
  31. #define CSWROFFTIME (0x14UL << 16)
  32. #define GPMC_CONFIG3_0 (GPMC_BASE + 0x68)
  33. #define ADVRDOFFTIME (0x14UL << 8)
  34. #define ADVWROFFTIME (0x14UL << 16)
  35. #define GPMC_CONFIG4_0 (GPMC_BASE + 0x6C)
  36. #define OEONTIME BIT0
  37. #define OEOFFTIME (0xFUL << 8)
  38. #define WEONTIME BIT16
  39. #define WEOFFTIME (0xFUL << 24)
  40. #define GPMC_CONFIG5_0 (GPMC_BASE + 0x70)
  41. #define RDCYCLETIME (0x14UL << 0)
  42. #define WRCYCLETIME (0x14UL << 8)
  43. #define RDACCESSTIME (0xCUL << 16)
  44. #define PAGEBURSTACCESSTIME BIT24
  45. #define GPMC_CONFIG6_0 (GPMC_BASE + 0x74)
  46. #define CYCLE2CYCLESAMECSEN BIT7
  47. #define CYCLE2CYCLEDELAY (0xAUL << 8)
  48. #define WRDATAONADMUXBUS (0xFUL << 16)
  49. #define WRACCESSTIME BIT24
  50. #define GPMC_CONFIG7_0 (GPMC_BASE + 0x78)
  51. #define BASEADDRESS (0x30UL << 0)
  52. #define CSVALID BIT6
  53. #define MASKADDRESS_128MB (0x8UL << 8)
  54. #define GPMC_NAND_COMMAND_0 (GPMC_BASE + 0x7C)
  55. #define GPMC_NAND_ADDRESS_0 (GPMC_BASE + 0x80)
  56. #define GPMC_NAND_DATA_0 (GPMC_BASE + 0x84)
  57. #define GPMC_ECC_CONFIG (GPMC_BASE + 0x1F4)
  58. #define ECCENABLE BIT0
  59. #define ECCDISABLE (0x0UL << 0)
  60. #define ECCCS_0 (0x0UL << 1)
  61. #define ECC16B BIT7
  62. #define GPMC_ECC_CONTROL (GPMC_BASE + 0x1F8)
  63. #define ECCPOINTER_REG1 BIT0
  64. #define ECCCLEAR BIT8
  65. #define GPMC_ECC_SIZE_CONFIG (GPMC_BASE + 0x1FC)
  66. #define ECCSIZE0_512BYTES (0xFFUL << 12)
  67. #define ECCSIZE1_512BYTES (0xFFUL << 22)
  68. #define GPMC_ECC1_RESULT (GPMC_BASE + 0x200)
  69. #define GPMC_ECC2_RESULT (GPMC_BASE + 0x204)
  70. #define GPMC_ECC3_RESULT (GPMC_BASE + 0x208)
  71. #define GPMC_ECC4_RESULT (GPMC_BASE + 0x20C)
  72. #define GPMC_ECC5_RESULT (GPMC_BASE + 0x210)
  73. #define GPMC_ECC6_RESULT (GPMC_BASE + 0x214)
  74. #define GPMC_ECC7_RESULT (GPMC_BASE + 0x218)
  75. #define GPMC_ECC8_RESULT (GPMC_BASE + 0x21C)
  76. #define GPMC_ECC9_RESULT (GPMC_BASE + 0x220)
  77. #endif //__OMAP3530GPMC_H__