Hpet.h 2.6 KB

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  1. /** @file
  2. HPET register definitions from the IA-PC HPET (High Precision Event Timers)
  3. Specification, Revision 1.0a, October 2004.
  4. Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #ifndef __HPET_REGISTER_H__
  8. #define __HPET_REGISTER_H__
  9. ///
  10. /// HPET General Register Offsets
  11. ///
  12. #define HPET_GENERAL_CAPABILITIES_ID_OFFSET 0x000
  13. #define HPET_GENERAL_CONFIGURATION_OFFSET 0x010
  14. #define HPET_GENERAL_INTERRUPT_STATUS_OFFSET 0x020
  15. ///
  16. /// HPET Timer Register Offsets
  17. ///
  18. #define HPET_MAIN_COUNTER_OFFSET 0x0F0
  19. #define HPET_TIMER_CONFIGURATION_OFFSET 0x100
  20. #define HPET_TIMER_COMPARATOR_OFFSET 0x108
  21. #define HPET_TIMER_MSI_ROUTE_OFFSET 0x110
  22. ///
  23. /// Stride between sets of HPET Timer Registers
  24. ///
  25. #define HPET_TIMER_STRIDE 0x20
  26. #pragma pack(1)
  27. ///
  28. /// HPET General Capabilities and ID Register
  29. ///
  30. typedef union {
  31. struct {
  32. UINT32 Revision : 8;
  33. UINT32 NumberOfTimers : 5;
  34. UINT32 CounterSize : 1;
  35. UINT32 Reserved0 : 1;
  36. UINT32 LegacyRoute : 1;
  37. UINT32 VendorId : 16;
  38. UINT32 CounterClockPeriod : 32;
  39. } Bits;
  40. UINT64 Uint64;
  41. } HPET_GENERAL_CAPABILITIES_ID_REGISTER;
  42. ///
  43. /// HPET General Configuration Register
  44. ///
  45. typedef union {
  46. struct {
  47. UINT32 MainCounterEnable : 1;
  48. UINT32 LegacyRouteEnable : 1;
  49. UINT32 Reserved0 : 30;
  50. UINT32 Reserved1 : 32;
  51. } Bits;
  52. UINT64 Uint64;
  53. } HPET_GENERAL_CONFIGURATION_REGISTER;
  54. ///
  55. /// HPET Timer Configuration Register
  56. ///
  57. typedef union {
  58. struct {
  59. UINT32 Reserved0 : 1;
  60. UINT32 LevelTriggeredInterrupt : 1;
  61. UINT32 InterruptEnable : 1;
  62. UINT32 PeriodicInterruptEnable : 1;
  63. UINT32 PeriodicInterruptCapability : 1;
  64. UINT32 CounterSizeCapability : 1;
  65. UINT32 ValueSetEnable : 1;
  66. UINT32 Reserved1 : 1;
  67. UINT32 CounterSizeEnable : 1;
  68. UINT32 InterruptRoute : 5;
  69. UINT32 MsiInterruptEnable : 1;
  70. UINT32 MsiInterruptCapability : 1;
  71. UINT32 Reserved2 : 16;
  72. UINT32 InterruptRouteCapability;
  73. } Bits;
  74. UINT64 Uint64;
  75. } HPET_TIMER_CONFIGURATION_REGISTER;
  76. ///
  77. /// HPET Timer MSI Route Register
  78. ///
  79. typedef union {
  80. struct {
  81. UINT32 Value : 32;
  82. UINT32 Address : 32;
  83. } Bits;
  84. UINT64 Uint64;
  85. } HPET_TIMER_MSI_ROUTE_REGISTER;
  86. #pragma pack()
  87. #endif