PpttParser.c 14 KB

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  1. /** @file
  2. PPTT table parser
  3. Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. @par Reference(s):
  6. - ACPI 6.3 Specification - January 2019
  7. - ARM Architecture Reference Manual ARMv8 (D.a)
  8. **/
  9. #include <Library/PrintLib.h>
  10. #include <Library/UefiLib.h>
  11. #include "AcpiParser.h"
  12. #include "AcpiView.h"
  13. #include "AcpiViewConfig.h"
  14. #include "PpttParser.h"
  15. // Local variables
  16. STATIC CONST UINT8 *ProcessorTopologyStructureType;
  17. STATIC CONST UINT8 *ProcessorTopologyStructureLength;
  18. STATIC CONST UINT32 *NumberOfPrivateResources;
  19. STATIC ACPI_DESCRIPTION_HEADER_INFO AcpiHdrInfo;
  20. /**
  21. This function validates the Cache Type Structure (Type 1) 'Number of sets'
  22. field.
  23. @param [in] Ptr Pointer to the start of the field data.
  24. @param [in] Context Pointer to context specific information e.g. this
  25. could be a pointer to the ACPI table header.
  26. **/
  27. STATIC
  28. VOID
  29. EFIAPI
  30. ValidateCacheNumberOfSets (
  31. IN UINT8 *Ptr,
  32. IN VOID *Context
  33. )
  34. {
  35. UINT32 NumberOfSets;
  36. NumberOfSets = *(UINT32 *)Ptr;
  37. if (NumberOfSets == 0) {
  38. IncrementErrorCount ();
  39. Print (L"\nERROR: Cache number of sets must be greater than 0");
  40. return;
  41. }
  42. #if defined (MDE_CPU_ARM) || defined (MDE_CPU_AARCH64)
  43. if (NumberOfSets > PPTT_ARM_CCIDX_CACHE_NUMBER_OF_SETS_MAX) {
  44. IncrementErrorCount ();
  45. Print (
  46. L"\nERROR: When ARMv8.3-CCIDX is implemented the maximum cache number of "
  47. L"sets must be less than or equal to %d",
  48. PPTT_ARM_CCIDX_CACHE_NUMBER_OF_SETS_MAX
  49. );
  50. return;
  51. }
  52. if (NumberOfSets > PPTT_ARM_CACHE_NUMBER_OF_SETS_MAX) {
  53. IncrementWarningCount ();
  54. Print (
  55. L"\nWARNING: Without ARMv8.3-CCIDX, the maximum cache number of sets "
  56. L"must be less than or equal to %d. Ignore this message if "
  57. L"ARMv8.3-CCIDX is implemented",
  58. PPTT_ARM_CACHE_NUMBER_OF_SETS_MAX
  59. );
  60. return;
  61. }
  62. #endif
  63. }
  64. /**
  65. This function validates the Cache Type Structure (Type 1) 'Associativity'
  66. field.
  67. @param [in] Ptr Pointer to the start of the field data.
  68. @param [in] Context Pointer to context specific information e.g. this
  69. could be a pointer to the ACPI table header.
  70. **/
  71. STATIC
  72. VOID
  73. EFIAPI
  74. ValidateCacheAssociativity (
  75. IN UINT8 *Ptr,
  76. IN VOID *Context
  77. )
  78. {
  79. UINT8 Associativity;
  80. Associativity = *(UINT8 *)Ptr;
  81. if (Associativity == 0) {
  82. IncrementErrorCount ();
  83. Print (L"\nERROR: Cache associativity must be greater than 0");
  84. return;
  85. }
  86. }
  87. /**
  88. This function validates the Cache Type Structure (Type 1) Line size field.
  89. @param [in] Ptr Pointer to the start of the field data.
  90. @param [in] Context Pointer to context specific information e.g. this
  91. could be a pointer to the ACPI table header.
  92. **/
  93. STATIC
  94. VOID
  95. EFIAPI
  96. ValidateCacheLineSize (
  97. IN UINT8 *Ptr,
  98. IN VOID *Context
  99. )
  100. {
  101. #if defined (MDE_CPU_ARM) || defined (MDE_CPU_AARCH64)
  102. // Reference: ARM Architecture Reference Manual ARMv8 (D.a)
  103. // Section D12.2.25: CCSIDR_EL1, Current Cache Size ID Register
  104. // LineSize, bits [2:0]
  105. // (Log2(Number of bytes in cache line)) - 4.
  106. UINT16 LineSize;
  107. LineSize = *(UINT16 *)Ptr;
  108. if ((LineSize < PPTT_ARM_CACHE_LINE_SIZE_MIN) ||
  109. (LineSize > PPTT_ARM_CACHE_LINE_SIZE_MAX))
  110. {
  111. IncrementErrorCount ();
  112. Print (
  113. L"\nERROR: The cache line size must be between %d and %d bytes"
  114. L" on ARM Platforms.",
  115. PPTT_ARM_CACHE_LINE_SIZE_MIN,
  116. PPTT_ARM_CACHE_LINE_SIZE_MAX
  117. );
  118. return;
  119. }
  120. if ((LineSize & (LineSize - 1)) != 0) {
  121. IncrementErrorCount ();
  122. Print (L"\nERROR: The cache line size is not a power of 2.");
  123. }
  124. #endif
  125. }
  126. /**
  127. This function validates the Cache Type Structure (Type 1) Attributes field.
  128. @param [in] Ptr Pointer to the start of the field data.
  129. @param [in] Context Pointer to context specific information e.g. this
  130. could be a pointer to the ACPI table header.
  131. **/
  132. STATIC
  133. VOID
  134. EFIAPI
  135. ValidateCacheAttributes (
  136. IN UINT8 *Ptr,
  137. IN VOID *Context
  138. )
  139. {
  140. // Reference: Advanced Configuration and Power Interface (ACPI) Specification
  141. // Version 6.2 Errata A, September 2017
  142. // Table 5-153: Cache Type Structure
  143. UINT8 Attributes;
  144. Attributes = *(UINT8 *)Ptr;
  145. if ((Attributes & 0xE0) != 0) {
  146. IncrementErrorCount ();
  147. Print (
  148. L"\nERROR: Attributes bits [7:5] are reserved and must be zero.",
  149. Attributes
  150. );
  151. return;
  152. }
  153. }
  154. /**
  155. An ACPI_PARSER array describing the ACPI PPTT Table.
  156. **/
  157. STATIC CONST ACPI_PARSER PpttParser[] = {
  158. PARSE_ACPI_HEADER (&AcpiHdrInfo)
  159. };
  160. /**
  161. An ACPI_PARSER array describing the processor topology structure header.
  162. **/
  163. STATIC CONST ACPI_PARSER ProcessorTopologyStructureHeaderParser[] = {
  164. { L"Type", 1, 0, NULL, NULL, (VOID **)&ProcessorTopologyStructureType,
  165. NULL, NULL },
  166. { L"Length", 1, 1, NULL, NULL, (VOID **)&ProcessorTopologyStructureLength,
  167. NULL, NULL },
  168. { L"Reserved", 2, 2, NULL, NULL, NULL, NULL,NULL }
  169. };
  170. /**
  171. An ACPI_PARSER array describing the Processor Hierarchy Node Structure - Type 0.
  172. **/
  173. STATIC CONST ACPI_PARSER ProcessorHierarchyNodeStructureParser[] = {
  174. { L"Type", 1, 0, L"0x%x", NULL, NULL, NULL, NULL },
  175. { L"Length", 1, 1, L"%d", NULL, NULL, NULL, NULL },
  176. { L"Reserved", 2, 2, L"0x%x", NULL, NULL, NULL, NULL },
  177. { L"Flags", 4, 4, L"0x%x", NULL, NULL, NULL, NULL },
  178. { L"Parent", 4, 8, L"0x%x", NULL, NULL, NULL, NULL },
  179. { L"ACPI Processor ID", 4, 12, L"0x%x", NULL, NULL, NULL, NULL },
  180. { L"Number of private resources", 4, 16, L"%d", NULL,
  181. (VOID **)&NumberOfPrivateResources, NULL, NULL }
  182. };
  183. /**
  184. An ACPI_PARSER array describing the Cache Type Structure - Type 1.
  185. **/
  186. STATIC CONST ACPI_PARSER CacheTypeStructureParser[] = {
  187. { L"Type", 1, 0, L"0x%x", NULL, NULL, NULL, NULL },
  188. { L"Length", 1, 1, L"%d", NULL, NULL, NULL, NULL },
  189. { L"Reserved", 2, 2, L"0x%x", NULL, NULL, NULL, NULL },
  190. { L"Flags", 4, 4, L"0x%x", NULL, NULL, NULL, NULL },
  191. { L"Next Level of Cache", 4, 8, L"0x%x", NULL, NULL, NULL, NULL },
  192. { L"Size", 4, 12, L"0x%x", NULL, NULL, NULL, NULL },
  193. { L"Number of sets", 4, 16, L"%d", NULL, NULL, ValidateCacheNumberOfSets, NULL },
  194. { L"Associativity", 1, 20, L"%d", NULL, NULL, ValidateCacheAssociativity, NULL },
  195. { L"Attributes", 1, 21, L"0x%x", NULL, NULL, ValidateCacheAttributes, NULL },
  196. { L"Line size", 2, 22, L"%d", NULL, NULL, ValidateCacheLineSize, NULL }
  197. };
  198. /**
  199. An ACPI_PARSER array describing the ID Type Structure - Type 2.
  200. **/
  201. STATIC CONST ACPI_PARSER IdStructureParser[] = {
  202. { L"Type", 1, 0, L"0x%x", NULL, NULL, NULL, NULL },
  203. { L"Length", 1, 1, L"%d", NULL, NULL, NULL, NULL },
  204. { L"Reserved", 2, 2, L"0x%x", NULL, NULL, NULL, NULL },
  205. { L"VENDOR_ID", 4, 4, NULL, Dump4Chars, NULL, NULL, NULL },
  206. { L"LEVEL_1_ID", 8, 8, L"0x%x", NULL, NULL, NULL, NULL },
  207. { L"LEVEL_2_ID", 8, 16, L"0x%x", NULL, NULL, NULL, NULL },
  208. { L"MAJOR_REV", 2, 24, L"0x%x", NULL, NULL, NULL, NULL },
  209. { L"MINOR_REV", 2, 26, L"0x%x", NULL, NULL, NULL, NULL },
  210. { L"SPIN_REV", 2, 28, L"0x%x", NULL, NULL, NULL, NULL },
  211. };
  212. /**
  213. This function parses the Processor Hierarchy Node Structure (Type 0).
  214. @param [in] Ptr Pointer to the start of the Processor Hierarchy Node
  215. Structure data.
  216. @param [in] Length Length of the Processor Hierarchy Node Structure.
  217. **/
  218. STATIC
  219. VOID
  220. DumpProcessorHierarchyNodeStructure (
  221. IN UINT8 *Ptr,
  222. IN UINT8 Length
  223. )
  224. {
  225. UINT32 Offset;
  226. UINT32 Index;
  227. CHAR16 Buffer[OUTPUT_FIELD_COLUMN_WIDTH];
  228. Offset = ParseAcpi (
  229. TRUE,
  230. 2,
  231. "Processor Hierarchy Node Structure",
  232. Ptr,
  233. Length,
  234. PARSER_PARAMS (ProcessorHierarchyNodeStructureParser)
  235. );
  236. // Check if the values used to control the parsing logic have been
  237. // successfully read.
  238. if (NumberOfPrivateResources == NULL) {
  239. IncrementErrorCount ();
  240. Print (
  241. L"ERROR: Insufficient Processor Hierarchy Node length. Length = %d.\n",
  242. Length
  243. );
  244. return;
  245. }
  246. // Make sure the Private Resource array lies inside this structure
  247. if (Offset + (*NumberOfPrivateResources * sizeof (UINT32)) > Length) {
  248. IncrementErrorCount ();
  249. Print (
  250. L"ERROR: Invalid Number of Private Resources. " \
  251. L"PrivateResourceCount = %d. RemainingBufferLength = %d. " \
  252. L"Parsing of this structure aborted.\n",
  253. *NumberOfPrivateResources,
  254. Length - Offset
  255. );
  256. return;
  257. }
  258. Index = 0;
  259. // Parse the specified number of private resource references or the Processor
  260. // Hierarchy Node length. Whichever is minimum.
  261. while (Index < *NumberOfPrivateResources) {
  262. UnicodeSPrint (
  263. Buffer,
  264. sizeof (Buffer),
  265. L"Private resources [%d]",
  266. Index
  267. );
  268. PrintFieldName (4, Buffer);
  269. Print (
  270. L"0x%x\n",
  271. *((UINT32 *)(Ptr + Offset))
  272. );
  273. Offset += sizeof (UINT32);
  274. Index++;
  275. }
  276. }
  277. /**
  278. This function parses the Cache Type Structure (Type 1).
  279. @param [in] Ptr Pointer to the start of the Cache Type Structure data.
  280. @param [in] Length Length of the Cache Type Structure.
  281. **/
  282. STATIC
  283. VOID
  284. DumpCacheTypeStructure (
  285. IN UINT8 *Ptr,
  286. IN UINT8 Length
  287. )
  288. {
  289. ParseAcpi (
  290. TRUE,
  291. 2,
  292. "Cache Type Structure",
  293. Ptr,
  294. Length,
  295. PARSER_PARAMS (CacheTypeStructureParser)
  296. );
  297. }
  298. /**
  299. This function parses the ID Structure (Type 2).
  300. @param [in] Ptr Pointer to the start of the ID Structure data.
  301. @param [in] Length Length of the ID Structure.
  302. **/
  303. STATIC
  304. VOID
  305. DumpIDStructure (
  306. IN UINT8 *Ptr,
  307. IN UINT8 Length
  308. )
  309. {
  310. ParseAcpi (
  311. TRUE,
  312. 2,
  313. "ID Structure",
  314. Ptr,
  315. Length,
  316. PARSER_PARAMS (IdStructureParser)
  317. );
  318. }
  319. /**
  320. This function parses the ACPI PPTT table.
  321. When trace is enabled this function parses the PPTT table and
  322. traces the ACPI table fields.
  323. This function parses the following processor topology structures:
  324. - Processor hierarchy node structure (Type 0)
  325. - Cache Type Structure (Type 1)
  326. - ID structure (Type 2)
  327. This function also performs validation of the ACPI table fields.
  328. @param [in] Trace If TRUE, trace the ACPI fields.
  329. @param [in] Ptr Pointer to the start of the buffer.
  330. @param [in] AcpiTableLength Length of the ACPI table.
  331. @param [in] AcpiTableRevision Revision of the ACPI table.
  332. **/
  333. VOID
  334. EFIAPI
  335. ParseAcpiPptt (
  336. IN BOOLEAN Trace,
  337. IN UINT8 *Ptr,
  338. IN UINT32 AcpiTableLength,
  339. IN UINT8 AcpiTableRevision
  340. )
  341. {
  342. UINT32 Offset;
  343. UINT8 *ProcessorTopologyStructurePtr;
  344. if (!Trace) {
  345. return;
  346. }
  347. Offset = ParseAcpi (
  348. TRUE,
  349. 0,
  350. "PPTT",
  351. Ptr,
  352. AcpiTableLength,
  353. PARSER_PARAMS (PpttParser)
  354. );
  355. ProcessorTopologyStructurePtr = Ptr + Offset;
  356. while (Offset < AcpiTableLength) {
  357. // Parse Processor Hierarchy Node Structure to obtain Type and Length.
  358. ParseAcpi (
  359. FALSE,
  360. 0,
  361. NULL,
  362. ProcessorTopologyStructurePtr,
  363. AcpiTableLength - Offset,
  364. PARSER_PARAMS (ProcessorTopologyStructureHeaderParser)
  365. );
  366. // Check if the values used to control the parsing logic have been
  367. // successfully read.
  368. if ((ProcessorTopologyStructureType == NULL) ||
  369. (ProcessorTopologyStructureLength == NULL))
  370. {
  371. IncrementErrorCount ();
  372. Print (
  373. L"ERROR: Insufficient remaining table buffer length to read the " \
  374. L"processor topology structure header. Length = %d.\n",
  375. AcpiTableLength - Offset
  376. );
  377. return;
  378. }
  379. // Validate Processor Topology Structure length
  380. if ((*ProcessorTopologyStructureLength == 0) ||
  381. ((Offset + (*ProcessorTopologyStructureLength)) > AcpiTableLength))
  382. {
  383. IncrementErrorCount ();
  384. Print (
  385. L"ERROR: Invalid Processor Topology Structure length. " \
  386. L"Length = %d. Offset = %d. AcpiTableLength = %d.\n",
  387. *ProcessorTopologyStructureLength,
  388. Offset,
  389. AcpiTableLength
  390. );
  391. return;
  392. }
  393. PrintFieldName (2, L"* Structure Offset *");
  394. Print (L"0x%x\n", Offset);
  395. switch (*ProcessorTopologyStructureType) {
  396. case EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR:
  397. DumpProcessorHierarchyNodeStructure (
  398. ProcessorTopologyStructurePtr,
  399. *ProcessorTopologyStructureLength
  400. );
  401. break;
  402. case EFI_ACPI_6_2_PPTT_TYPE_CACHE:
  403. DumpCacheTypeStructure (
  404. ProcessorTopologyStructurePtr,
  405. *ProcessorTopologyStructureLength
  406. );
  407. break;
  408. case EFI_ACPI_6_2_PPTT_TYPE_ID:
  409. DumpIDStructure (
  410. ProcessorTopologyStructurePtr,
  411. *ProcessorTopologyStructureLength
  412. );
  413. break;
  414. default:
  415. IncrementErrorCount ();
  416. Print (
  417. L"ERROR: Unknown processor topology structure:"
  418. L" Type = %d, Length = %d\n",
  419. *ProcessorTopologyStructureType,
  420. *ProcessorTopologyStructureLength
  421. );
  422. }
  423. ProcessorTopologyStructurePtr += *ProcessorTopologyStructureLength;
  424. Offset += *ProcessorTopologyStructureLength;
  425. } // while
  426. }