ArmPkg.dec 16 KB

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  1. #/** @file
  2. # ARM processor package.
  3. #
  4. # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
  5. # Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.
  6. # Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
  7. #
  8. # SPDX-License-Identifier: BSD-2-Clause-Patent
  9. #
  10. #**/
  11. [Defines]
  12. DEC_SPECIFICATION = 0x00010005
  13. PACKAGE_NAME = ArmPkg
  14. PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
  15. PACKAGE_VERSION = 0.1
  16. ################################################################################
  17. #
  18. # Include Section - list of Include Paths that are provided by this package.
  19. # Comments are used for Keywords and Module Types.
  20. #
  21. # Supported Module Types:
  22. # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
  23. #
  24. ################################################################################
  25. [Includes.common]
  26. Include # Root include for the package
  27. [LibraryClasses.common]
  28. ## @libraryclass Convert Arm instructions to a human readable format.
  29. #
  30. ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
  31. ## @libraryclass Provides an interface to Arm generic counters.
  32. #
  33. ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h
  34. ## @libraryclass Provides an interface to initialize a
  35. # Generic Interrupt Controller (GIC).
  36. #
  37. ArmGicArchLib|Include/Library/ArmGicArchLib.h
  38. ## @libraryclass Provides a Generic Interrupt Controller (GIC)
  39. # configuration interface.
  40. #
  41. ArmGicLib|Include/Library/ArmGicLib.h
  42. ## @libraryclass Provides a HyperVisor Call (HVC) interface.
  43. #
  44. ArmHvcLib|Include/Library/ArmHvcLib.h
  45. ## @libraryclass Provides an interface to Arm registers.
  46. #
  47. ArmLib|Include/Library/ArmLib.h
  48. ## @libraryclass Provides a Mmu interface.
  49. #
  50. ArmMmuLib|Include/Library/ArmMmuLib.h
  51. ## @libraryclass Provides a Mailbox Transport Layer (MTL) interface
  52. # for the System Control and Management Interface (SCMI).
  53. #
  54. ArmMtlLib|Include/Library/ArmMtlLib.h
  55. ## @libraryclass Provides a System Monitor Call (SMC) interface.
  56. #
  57. ArmSmcLib|Include/Library/ArmSmcLib.h
  58. ## @libraryclass Provides a SuperVisor Call (SVC) interface.
  59. #
  60. ArmSvcLib|Include/Library/ArmSvcLib.h
  61. ## @libraryclass Provides a default exception handler.
  62. #
  63. DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
  64. ## @libraryclass Provides an interface to query miscellaneous OEM
  65. # information.
  66. #
  67. OemMiscLib|Include/Library/OemMiscLib.h
  68. ## @libraryclass Provides an OpTee interface.
  69. #
  70. OpteeLib|Include/Library/OpteeLib.h
  71. ## @libraryclass Provides a semihosting interface.
  72. #
  73. SemihostLib|Include/Library/SemihostLib.h
  74. ## @libraryclass Provides an interface for a StandaloneMm Mmu.
  75. #
  76. StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
  77. [Guids.common]
  78. gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
  79. ## ARM MPCore table
  80. # Include/Guid/ArmMpCoreInfo.h
  81. gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
  82. gArmMmuReplaceLiveTranslationEntryFuncGuid = { 0xa8b50ff3, 0x08ec, 0x4dd3, {0xbf, 0x04, 0x28, 0xbf, 0x71, 0x75, 0xc7, 0x4a} }
  83. [Protocols.common]
  84. ## Arm System Control and Management Interface(SCMI) Base protocol
  85. ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h
  86. gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }
  87. ## Arm System Control and Management Interface(SCMI) Clock management protocol
  88. ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
  89. gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }
  90. gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }
  91. ## Arm System Control and Management Interface(SCMI) Clock management protocol
  92. ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h
  93. gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }
  94. [Ppis]
  95. ## Include/Ppi/ArmMpCoreInfo.h
  96. gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
  97. [PcdsFeatureFlag.common]
  98. gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
  99. # On ARM Architecture with the Security Extension, the address for the
  100. # Vector Table can be mapped anywhere in the memory map. It means we can
  101. # point the Exception Vector Table to its location in CpuDxe.
  102. # By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)
  103. gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
  104. # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
  105. # it has been configured by the CPU DXE
  106. gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
  107. # Define if the GICv3 controller should use the GICv2 legacy
  108. gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
  109. [PcdsFeatureFlag.ARM]
  110. # Whether to map normal memory as non-shareable. FALSE is the safe choice, but
  111. # TRUE may be appropriate to fix performance problems if you don't care about
  112. # hardware coherency (i.e., no virtualization or cache coherent DMA)
  113. gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
  114. [PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.ARM]
  115. ## Used to select method for requesting services from S-EL1.<BR><BR>
  116. # TRUE - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>
  117. # FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>
  118. # @Prompt Enable FF-A support.
  119. gArmTokenSpaceGuid.PcdFfaEnable|FALSE|BOOLEAN|0x0000005B
  120. [PcdsFixedAtBuild.common]
  121. gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
  122. # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
  123. # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
  124. gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
  125. gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
  126. gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
  127. #
  128. # ARM Secure Firmware PCDs
  129. #
  130. gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
  131. gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
  132. gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
  133. gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
  134. #
  135. # ARM Hypervisor Firmware PCDs
  136. #
  137. gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
  138. gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
  139. gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
  140. gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
  141. # Use ClusterId + CoreId to identify the PrimaryCore
  142. gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
  143. # The Primary Core is ClusterId[0] & CoreId[0]
  144. gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
  145. #
  146. # SMBIOS PCDs
  147. #
  148. gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053
  149. gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054
  150. gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055
  151. gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056
  152. gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057
  153. gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071
  154. gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072
  155. gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073
  156. gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074
  157. gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075
  158. #
  159. # ARM L2x0 PCDs
  160. #
  161. gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
  162. #
  163. # ARM Normal (or Non Secure) Firmware PCDs
  164. #
  165. gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
  166. gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
  167. #
  168. # Value to add to a host address to obtain a device address, using
  169. # unsigned 64-bit integer arithmetic on both ARM and AArch64. This
  170. # means we can rely on truncation on overflow to specify negative
  171. # offsets.
  172. #
  173. gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044
  174. [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
  175. gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
  176. gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
  177. [PcdsFixedAtBuild.ARM]
  178. #
  179. # ARM Security Extension
  180. #
  181. # Secure Configuration Register
  182. # - BIT0 : NS - Non Secure bit
  183. # - BIT1 : IRQ Handler
  184. # - BIT2 : FIQ Handler
  185. # - BIT3 : EA - External Abort
  186. # - BIT4 : FW - F bit writable
  187. # - BIT5 : AW - A bit writable
  188. # - BIT6 : nET - Not Early Termination
  189. # - BIT7 : SCD - Secure Monitor Call Disable
  190. # - BIT8 : HCE - Hyp Call enable
  191. # - BIT9 : SIF - Secure Instruction Fetch
  192. # 0x31 = NS | EA | FW
  193. gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
  194. # By default we do not do a transition to non-secure mode
  195. gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
  196. # Non Secure Access Control Register
  197. # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
  198. # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
  199. # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
  200. # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
  201. # 0xC00 = cp10 | cp11
  202. gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
  203. [PcdsFixedAtBuild.AARCH64]
  204. #
  205. # AArch64 Security Extension
  206. #
  207. # Secure Configuration Register
  208. # - BIT0 : NS - Non Secure bit
  209. # - BIT1 : IRQ Handler
  210. # - BIT2 : FIQ Handler
  211. # - BIT3 : EA - External Abort
  212. # - BIT4 : FW - F bit writable
  213. # - BIT5 : AW - A bit writable
  214. # - BIT6 : nET - Not Early Termination
  215. # - BIT7 : SCD - Secure Monitor Call Disable
  216. # - BIT8 : HCE - Hyp Call enable
  217. # - BIT9 : SIF - Secure Instruction Fetch
  218. # - BIT10: RW - Register width control for lower exception levels
  219. # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
  220. # - BIT12: TWI - Trap WFI
  221. # - BIT13: TWE - Trap WFE
  222. # 0x501 = NS | HCE | RW
  223. gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
  224. # By default we do transition to EL2 non-secure mode with Stack for EL2.
  225. # Mode Description Bits
  226. # NS EL2 SP2 all interrupts disabled = 0x3c9
  227. # NS EL1 SP1 all interrupts disabled = 0x3c5
  228. # Other modes include using SP0 or switching to Aarch32, but these are
  229. # not currently supported.
  230. gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
  231. #
  232. # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
  233. # redefined when using UEFI in a context of virtual machine.
  234. #
  235. [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
  236. # System Memory (DRAM): These PCDs define the region of in-built system memory
  237. # Some platforms can get DRAM extensions, these additional regions may be
  238. # declared to UEFI using separate resource descriptor HOBs
  239. gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
  240. gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
  241. gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045
  242. gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046
  243. gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058
  244. gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059
  245. [PcdsFixedAtBuild.common, PcdsDynamic.common]
  246. #
  247. # ARM Architectural Timer
  248. #
  249. gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
  250. # ARM Architectural Timer Interrupt(GIC PPI) numbers
  251. gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
  252. gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
  253. gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
  254. gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
  255. #
  256. # ARM Generic Watchdog
  257. #
  258. gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007
  259. gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008
  260. gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
  261. #
  262. # ARM Generic Interrupt Controller
  263. #
  264. gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
  265. # Base address for the GIC Redistributor region that contains the boot CPU
  266. gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
  267. gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
  268. gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
  269. #
  270. # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
  271. # Note that "IO" is just another MMIO range that simulates IO space; there
  272. # are no special instructions to access it.
  273. #
  274. # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
  275. # specific to their containing address spaces. In order to get the physical
  276. # address for the CPU, for a given access, the respective translation value
  277. # has to be added.
  278. #
  279. # The translations always have to be initialized like this, using UINT64:
  280. #
  281. # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space
  282. # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
  283. # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
  284. #
  285. # gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
  286. # gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
  287. # gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
  288. #
  289. # because (a) the target address space (ie. the cpu-physical space) is
  290. # 64-bit, and (b) the translation values are meant as offsets for *modular*
  291. # arithmetic.
  292. #
  293. # Accordingly, the translation itself needs to be implemented as:
  294. #
  295. # UINT64 UntranslatedIoAddress; // input parameter
  296. # UINT32 UntranslatedMmio32Address; // input parameter
  297. # UINT64 UntranslatedMmio64Address; // input parameter
  298. #
  299. # UINT64 TranslatedIoAddress; // output parameter
  300. # UINT64 TranslatedMmio32Address; // output parameter
  301. # UINT64 TranslatedMmio64Address; // output parameter
  302. #
  303. # TranslatedIoAddress = UntranslatedIoAddress +
  304. # gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation;
  305. # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
  306. # gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation;
  307. # TranslatedMmio64Address = UntranslatedMmio64Address +
  308. # gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation;
  309. #
  310. # The modular arithmetic performed in UINT64 ensures that the translation
  311. # works correctly regardless of the relation between IoCpuBase and
  312. # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
  313. # PcdPciMmio64Base.
  314. #
  315. gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
  316. gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
  317. gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
  318. gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
  319. gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
  320. gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
  321. #
  322. # Inclusive range of allowed PCI buses.
  323. #
  324. gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
  325. gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A
  326. [PcdsDynamicEx]
  327. #
  328. # This dynamic PCD hold the GUID of a firmware FFS which contains
  329. # the LinuxBoot payload.
  330. #
  331. gArmTokenSpaceGuid.PcdLinuxBootFileGuid|{0x0}|VOID*|0x0000005C