PrePeiCore.c 4.5 KB

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  1. /** @file
  2. Main file supporting the transition to PEI Core in Normal World for Versatile Express
  3. Copyright (c) 2011 - 2022, ARM Limited. All rights reserved.
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <Library/BaseLib.h>
  7. #include <Library/CacheMaintenanceLib.h>
  8. #include <Library/DebugAgentLib.h>
  9. #include <Library/ArmLib.h>
  10. #include "PrePeiCore.h"
  11. CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };
  12. CONST EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable[] = {
  13. {
  14. EFI_PEI_PPI_DESCRIPTOR_PPI,
  15. &gEfiTemporaryRamSupportPpiGuid,
  16. (VOID *)&mTemporaryRamSupportPpi
  17. }
  18. };
  19. VOID
  20. CreatePpiList (
  21. OUT UINTN *PpiListSize,
  22. OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
  23. )
  24. {
  25. EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;
  26. UINTN PlatformPpiListSize;
  27. UINTN ListBase;
  28. EFI_PEI_PPI_DESCRIPTOR *LastPpi;
  29. // Get the Platform PPIs
  30. PlatformPpiListSize = 0;
  31. ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);
  32. // Copy the Common and Platform PPis in Temporary Memory
  33. ListBase = PcdGet64 (PcdCPUCoresStackBase);
  34. CopyMem ((VOID *)ListBase, gCommonPpiTable, sizeof (gCommonPpiTable));
  35. CopyMem ((VOID *)(ListBase + sizeof (gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);
  36. // Set the Terminate flag on the last PPI entry
  37. LastPpi = (EFI_PEI_PPI_DESCRIPTOR *)ListBase + ((sizeof (gCommonPpiTable) + PlatformPpiListSize) / sizeof (EFI_PEI_PPI_DESCRIPTOR)) - 1;
  38. LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
  39. *PpiList = (EFI_PEI_PPI_DESCRIPTOR *)ListBase;
  40. *PpiListSize = sizeof (gCommonPpiTable) + PlatformPpiListSize;
  41. }
  42. VOID
  43. CEntryPoint (
  44. IN UINTN MpId,
  45. IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
  46. )
  47. {
  48. // Data Cache enabled on Primary core when MMU is enabled.
  49. ArmDisableDataCache ();
  50. // Invalidate instruction cache
  51. ArmInvalidateInstructionCache ();
  52. // Enable Instruction Caches on all cores.
  53. ArmEnableInstructionCache ();
  54. InvalidateDataCacheRange (
  55. (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),
  56. PcdGet32 (PcdCPUCorePrimaryStackSize)
  57. );
  58. //
  59. // Note: Doesn't have to Enable CPU interface in non-secure world,
  60. // as Non-secure interface is already enabled in Secure world.
  61. //
  62. // Write VBAR - The Exception Vector table must be aligned to its requirement
  63. // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure
  64. // 'Align=4K' is defined into your FDF for this module.
  65. ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
  66. ArmWriteVBar ((UINTN)PeiVectorTable);
  67. // Enable Floating Point
  68. if (FixedPcdGet32 (PcdVFPEnabled)) {
  69. ArmEnableVFP ();
  70. }
  71. // Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.
  72. // If not primary Jump to Secondary Main
  73. if (ArmPlatformIsPrimaryCore (MpId)) {
  74. // Invoke "ProcessLibraryConstructorList" to have all library constructors
  75. // called.
  76. ProcessLibraryConstructorList ();
  77. // Initialize the Debug Agent for Source Level Debugging
  78. InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
  79. SaveAndSetDebugTimerInterrupt (TRUE);
  80. // Initialize the platform specific controllers
  81. ArmPlatformInitialize (MpId);
  82. // Goto primary Main.
  83. PrimaryMain (PeiCoreEntryPoint);
  84. } else {
  85. SecondaryMain (MpId);
  86. }
  87. // PEI Core should always load and never return
  88. ASSERT (FALSE);
  89. }
  90. EFI_STATUS
  91. EFIAPI
  92. PrePeiCoreTemporaryRamSupport (
  93. IN CONST EFI_PEI_SERVICES **PeiServices,
  94. IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
  95. IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
  96. IN UINTN CopySize
  97. )
  98. {
  99. VOID *OldHeap;
  100. VOID *NewHeap;
  101. VOID *OldStack;
  102. VOID *NewStack;
  103. UINTN HeapSize;
  104. HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);
  105. OldHeap = (VOID *)(UINTN)TemporaryMemoryBase;
  106. NewHeap = (VOID *)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));
  107. OldStack = (VOID *)((UINTN)TemporaryMemoryBase + HeapSize);
  108. NewStack = (VOID *)(UINTN)PermanentMemoryBase;
  109. //
  110. // Migrate the temporary memory stack to permanent memory stack.
  111. //
  112. CopyMem (NewStack, OldStack, CopySize - HeapSize);
  113. //
  114. // Migrate the temporary memory heap to permanent memory heap.
  115. //
  116. CopyMem (NewHeap, OldHeap, HeapSize);
  117. SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);
  118. return EFI_SUCCESS;
  119. }