SmmCpuSaveState.h 5.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169
  1. /** @file
  2. This file declares the SMM CPU Save State protocol, which provides the processor
  3. save-state information for IA-32 and Itanium processors.
  4. Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. @par Revision Reference:
  7. This Protocol is defined in Framework of EFI SMM Core Interface Spec
  8. Version 0.91.
  9. **/
  10. #ifndef _SMM_CPU_SAVE_STATE_H_
  11. #define _SMM_CPU_SAVE_STATE_H_
  12. #define EFI_SMM_CPU_SAVE_STATE_PROTOCOL_GUID \
  13. { \
  14. 0x21f302ad, 0x6e94, 0x471b, {0x84, 0xbc, 0xb1, 0x48, 0x0, 0x40, 0x3a, 0x1d} \
  15. }
  16. typedef struct _EFI_SMM_CPU_SAVE_STATE_PROTOCOL EFI_SMM_CPU_SAVE_STATE_PROTOCOL;
  17. #define EFI_SMM_MIN_REV_ID_x64 0x30006
  18. #pragma pack (1)
  19. ///
  20. /// CPU save-state strcuture for IA32 and X64.
  21. ///
  22. /// This struct declaration does not exctly match the Framework SMM CIS 0.91 because the
  23. /// union in the Framework SMM CIS 0.91 contains an unnamed union member that causes build
  24. /// breaks on many compilers with high warning levels. Instead, the UINT8 Reserved[0x200]
  25. /// field has been moved into EFI_SMM_CPU_STATE32. This maintains binary compatibility for
  26. /// the layout and also maintains source comaptibility for access of all fields in this
  27. /// union.
  28. ///
  29. /// This struct declaration does not exctly match the Framework SMM CIS 0.91 because
  30. /// the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure. These
  31. /// have been changed to use the base types defined in the UEFI Specification.
  32. ///
  33. typedef struct {
  34. UINT8 Reserved[0x200];
  35. UINT8 Reserved1[0xf8]; // fe00h
  36. UINT32 SMBASE; // fef8h
  37. UINT32 SMMRevId; // fefch
  38. UINT16 IORestart; // ff00h
  39. UINT16 AutoHALTRestart; // ff02h
  40. UINT32 IEDBASE; // ff04h
  41. UINT8 Reserved2[0x98]; // ff08h
  42. UINT32 IOMemAddr; // ffa0h
  43. UINT32 IOMisc; // ffa4h
  44. UINT32 _ES;
  45. UINT32 _CS;
  46. UINT32 _SS;
  47. UINT32 _DS;
  48. UINT32 _FS;
  49. UINT32 _GS;
  50. UINT32 _LDTBase;
  51. UINT32 _TR;
  52. UINT32 _DR7;
  53. UINT32 _DR6;
  54. UINT32 _EAX;
  55. UINT32 _ECX;
  56. UINT32 _EDX;
  57. UINT32 _EBX;
  58. UINT32 _ESP;
  59. UINT32 _EBP;
  60. UINT32 _ESI;
  61. UINT32 _EDI;
  62. UINT32 _EIP;
  63. UINT32 _EFLAGS;
  64. UINT32 _CR3;
  65. UINT32 _CR0;
  66. } EFI_SMM_CPU_STATE32;
  67. ///
  68. /// This struct declaration does not exctly match the Framework SMM CIS 0.91 because
  69. /// the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure. These
  70. /// have been changed to use the base types defined in the UEFI Specification.
  71. ///
  72. typedef struct {
  73. UINT8 Reserved1[0x1d0]; // fc00h
  74. UINT32 GdtBaseHiDword; // fdd0h
  75. UINT32 LdtBaseHiDword; // fdd4h
  76. UINT32 IdtBaseHiDword; // fdd8h
  77. UINT8 Reserved2[0xc]; // fddch
  78. UINT64 IO_EIP; // fde8h
  79. UINT8 Reserved3[0x50]; // fdf0h
  80. UINT32 _CR4; // fe40h
  81. UINT8 Reserved4[0x48]; // fe44h
  82. UINT32 GdtBaseLoDword; // fe8ch
  83. UINT32 GdtLimit; // fe90h
  84. UINT32 IdtBaseLoDword; // fe94h
  85. UINT32 IdtLimit; // fe98h
  86. UINT32 LdtBaseLoDword; // fe9ch
  87. UINT32 LdtLimit; // fea0h
  88. UINT32 LdtInfo; // fea4h
  89. UINT8 Reserved5[0x50]; // fea8h
  90. UINT32 SMBASE; // fef8h
  91. UINT32 SMMRevId; // fefch
  92. UINT16 AutoHALTRestart; // ff00h
  93. UINT16 IORestart; // ff02h
  94. UINT32 IEDBASE; // ff04h
  95. UINT8 Reserved6[0x14]; // ff08h
  96. UINT64 _R15; // ff1ch
  97. UINT64 _R14;
  98. UINT64 _R13;
  99. UINT64 _R12;
  100. UINT64 _R11;
  101. UINT64 _R10;
  102. UINT64 _R9;
  103. UINT64 _R8;
  104. UINT64 _RAX; // ff5ch
  105. UINT64 _RCX;
  106. UINT64 _RDX;
  107. UINT64 _RBX;
  108. UINT64 _RSP;
  109. UINT64 _RBP;
  110. UINT64 _RSI;
  111. UINT64 _RDI;
  112. UINT64 IOMemAddr; // ff9ch
  113. UINT32 IOMisc; // ffa4h
  114. UINT32 _ES; // ffa8h
  115. UINT32 _CS;
  116. UINT32 _SS;
  117. UINT32 _DS;
  118. UINT32 _FS;
  119. UINT32 _GS;
  120. UINT32 _LDTR; // ffc0h
  121. UINT32 _TR;
  122. UINT64 _DR7; // ffc8h
  123. UINT64 _DR6;
  124. UINT64 _RIP; // ffd8h
  125. UINT64 IA32_EFER; // ffe0h
  126. UINT64 _RFLAGS; // ffe8h
  127. UINT64 _CR3; // fff0h
  128. UINT64 _CR0; // fff8h
  129. } EFI_SMM_CPU_STATE64;
  130. ///
  131. /// Union of CPU save-state strcutures for IA32 and X64.
  132. ///
  133. /// This union declaration does not exctly match the Framework SMM CIS 0.91 because the
  134. /// union in the Framework SMM CIS 0.91 contains an unnamed union member that causes build
  135. /// breaks on many compilers with high warning levels. Instead, the UINT8 Reserved[0x200]
  136. /// field has been moved into EFI_SMM_CPU_STATE32. This maintains binary compatibility for
  137. /// the layout and also maintains source comaptibility for access of all fields in this
  138. /// union.
  139. ///
  140. typedef union {
  141. EFI_SMM_CPU_STATE32 x86;
  142. EFI_SMM_CPU_STATE64 x64;
  143. } EFI_SMM_CPU_STATE;
  144. #pragma pack ()
  145. ///
  146. /// Provides a programatic means to access SMM save state.
  147. ///
  148. struct _EFI_SMM_CPU_SAVE_STATE_PROTOCOL {
  149. ///
  150. /// Reference to a list of save states.
  151. ///
  152. EFI_SMM_CPU_STATE **CpuSaveState;
  153. };
  154. extern EFI_GUID gEfiSmmCpuSaveStateProtocolGuid;
  155. #endif