SaveRestoreSse.inc 4.4 KB

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  1. ;------------------------------------------------------------------------------
  2. ;
  3. ; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
  4. ; SPDX-License-Identifier: BSD-2-Clause-Patent
  5. ;
  6. ; Abstract:
  7. ;
  8. ; Provide macro for register save/restore using SSE registers
  9. ;
  10. ;------------------------------------------------------------------------------
  11. ;
  12. ; Define SSE instruction set
  13. ;
  14. IFDEF USE_SSE41_FLAG
  15. ;
  16. ; Define SSE macros using SSE 4.1 instructions
  17. ;
  18. SXMMN MACRO XMM, IDX, REG
  19. pinsrd XMM, REG, (IDX AND 3)
  20. ENDM
  21. LXMMN MACRO XMM, REG, IDX
  22. pextrd REG, XMM, (IDX AND 3)
  23. ENDM
  24. ELSE
  25. ;
  26. ; Define SSE macros using SSE 2 instructions
  27. ;
  28. SXMMN MACRO XMM, IDX, REG
  29. pinsrw XMM, REG, (IDX AND 3) * 2
  30. ror REG, 16
  31. pinsrw XMM, REG, (IDX AND 3) * 2 + 1
  32. rol REG, 16
  33. ENDM
  34. LXMMN MACRO XMM, REG, IDX
  35. pshufd XMM, XMM, (0E4E4E4h SHR (IDX * 2)) AND 0FFh
  36. movd REG, XMM
  37. pshufd XMM, XMM, (0E4E4E4h SHR (IDX * 2 + (IDX AND 1) * 4)) AND 0FFh
  38. ENDM
  39. ENDIF
  40. ;
  41. ; XMM7 to save/restore EBP, EBX, ESI, EDI
  42. ;
  43. SAVE_REGS MACRO
  44. SXMMN xmm7, 0, ebp
  45. SXMMN xmm7, 1, ebx
  46. SXMMN xmm7, 2, esi
  47. SXMMN xmm7, 3, edi
  48. SAVE_ESP
  49. ENDM
  50. LOAD_REGS MACRO
  51. LXMMN xmm7, ebp, 0
  52. LXMMN xmm7, ebx, 1
  53. LXMMN xmm7, esi, 2
  54. LXMMN xmm7, edi, 3
  55. LOAD_ESP
  56. ENDM
  57. ;
  58. ; XMM6 to save/restore EAX, EDX, ECX, ESP
  59. ;
  60. LOAD_EAX MACRO
  61. LXMMN xmm6, eax, 1
  62. ENDM
  63. SAVE_EAX MACRO
  64. SXMMN xmm6, 1, eax
  65. ENDM
  66. LOAD_EDX MACRO
  67. LXMMN xmm6, edx, 2
  68. ENDM
  69. SAVE_EDX MACRO
  70. SXMMN xmm6, 2, edx
  71. ENDM
  72. SAVE_ECX MACRO
  73. SXMMN xmm6, 3, ecx
  74. ENDM
  75. LOAD_ECX MACRO
  76. LXMMN xmm6, ecx, 3
  77. ENDM
  78. SAVE_ESP MACRO
  79. SXMMN xmm6, 0, esp
  80. ENDM
  81. LOAD_ESP MACRO
  82. movd esp, xmm6
  83. ENDM
  84. ;
  85. ; XMM5 for calling stack
  86. ;
  87. CALL_XMM MACRO Entry
  88. local ReturnAddress
  89. mov esi, offset ReturnAddress
  90. pslldq xmm5, 4
  91. IFDEF USE_SSE41_FLAG
  92. pinsrd xmm5, esi, 0
  93. ELSE
  94. pinsrw xmm5, esi, 0
  95. ror esi, 16
  96. pinsrw xmm5, esi, 1
  97. ENDIF
  98. mov esi, Entry
  99. jmp esi
  100. ReturnAddress:
  101. ENDM
  102. RET_XMM MACRO
  103. movd esi, xmm5
  104. psrldq xmm5, 4
  105. jmp esi
  106. ENDM
  107. ENABLE_SSE MACRO
  108. ;
  109. ; Initialize floating point units
  110. ;
  111. local NextAddress
  112. jmp NextAddress
  113. ALIGN 4
  114. ;
  115. ; Float control word initial value:
  116. ; all exceptions masked, double-precision, round-to-nearest
  117. ;
  118. FpuControlWord DW 027Fh
  119. ;
  120. ; Multimedia-extensions control word:
  121. ; all exceptions masked, round-to-nearest, flush to zero for masked underflow
  122. ;
  123. MmxControlWord DD 01F80h
  124. SseError:
  125. ;
  126. ; Processor has to support SSE
  127. ;
  128. jmp SseError
  129. NextAddress:
  130. finit
  131. fldcw FpuControlWord
  132. ;
  133. ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
  134. ; whether the processor supports SSE instruction.
  135. ;
  136. mov eax, 1
  137. cpuid
  138. bt edx, 25
  139. jnc SseError
  140. IFDEF USE_SSE41_FLAG
  141. ;
  142. ; SSE 4.1 support
  143. ;
  144. bt ecx, 19
  145. jnc SseError
  146. ENDIF
  147. ;
  148. ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
  149. ;
  150. mov eax, cr4
  151. or eax, 00000600h
  152. mov cr4, eax
  153. ;
  154. ; The processor should support SSE instruction and we can use
  155. ; ldmxcsr instruction
  156. ;
  157. ldmxcsr MmxControlWord
  158. ENDM