InitializeFpu.s 1.7 KB

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  1. #------------------------------------------------------------------------------
  2. #
  3. # Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
  4. # SPDX-License-Identifier: BSD-2-Clause-Patent
  5. #
  6. # Abstract:
  7. #
  8. #------------------------------------------------------------------------------
  9. #
  10. # Float control word initial value:
  11. # all exceptions masked, double-precision, round-to-nearest
  12. #
  13. ASM_PFX(mFpuControlWord): .word 0x027F
  14. #
  15. # Multimedia-extensions control word:
  16. # all exceptions masked, round-to-nearest, flush to zero for masked underflow
  17. #
  18. ASM_PFX(mMmxControlWord): .long 0x01F80
  19. #
  20. # Initializes floating point units for requirement of UEFI specification.
  21. #
  22. # This function initializes floating-point control word to 0x027F (all exceptions
  23. # masked,double-precision, round-to-nearest) and multimedia-extensions control word
  24. # (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
  25. # for masked underflow).
  26. #
  27. ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
  28. ASM_PFX(InitializeFloatingPointUnits):
  29. pushl %ebx
  30. #
  31. # Initialize floating point units
  32. #
  33. finit
  34. fldcw ASM_PFX(mFpuControlWord)
  35. #
  36. # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
  37. # whether the processor supports SSE instruction.
  38. #
  39. movl $1, %eax
  40. cpuid
  41. btl $25, %edx
  42. jnc Done
  43. #
  44. # Set OSFXSR bit 9 in CR4
  45. #
  46. movl %cr4, %eax
  47. orl $BIT9, %eax
  48. movl %eax, %cr4
  49. #
  50. # The processor should support SSE instruction and we can use
  51. # ldmxcsr instruction
  52. #
  53. ldmxcsr ASM_PFX(mMmxControlWord)
  54. Done:
  55. popl %ebx
  56. ret