InitializeFpu.asm 1.7 KB

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  1. ;------------------------------------------------------------------------------
  2. ;
  3. ; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
  4. ; SPDX-License-Identifier: BSD-2-Clause-Patent
  5. ;
  6. ; Abstract:
  7. ;
  8. ;------------------------------------------------------------------------------
  9. .686
  10. .model flat,C
  11. .const
  12. ;
  13. ; Float control word initial value:
  14. ; all exceptions masked, double-precision, round-to-nearest
  15. ;
  16. mFpuControlWord DW 027Fh
  17. ;
  18. ; Multimedia-extensions control word:
  19. ; all exceptions masked, round-to-nearest, flush to zero for masked underflow
  20. ;
  21. mMmxControlWord DD 01F80h
  22. .xmm
  23. .code
  24. ;
  25. ; Initializes floating point units for requirement of UEFI specification.
  26. ;
  27. ; This function initializes floating-point control word to 0x027F (all exceptions
  28. ; masked,double-precision, round-to-nearest) and multimedia-extensions control word
  29. ; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
  30. ; for masked underflow).
  31. ;
  32. InitializeFloatingPointUnits PROC PUBLIC
  33. push ebx
  34. ;
  35. ; Initialize floating point units
  36. ;
  37. finit
  38. fldcw mFpuControlWord
  39. ;
  40. ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
  41. ; whether the processor supports SSE instruction.
  42. ;
  43. mov eax, 1
  44. cpuid
  45. bt edx, 25
  46. jnc Done
  47. ;
  48. ; Set OSFXSR bit 9 in CR4
  49. ;
  50. mov eax, cr4
  51. or eax, BIT9
  52. mov cr4, eax
  53. ;
  54. ; The processor should support SSE instruction and we can use
  55. ; ldmxcsr instruction
  56. ;
  57. ldmxcsr mMmxControlWord
  58. Done:
  59. pop ebx
  60. ret
  61. InitializeFloatingPointUnits ENDP
  62. END