Aesni.c 4.1 KB

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  1. /** @file
  2. AESNI feature.
  3. Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "CpuCommonFeatures.h"
  7. /**
  8. Prepares for the data used by CPU feature detection and initialization.
  9. @param[in] NumberOfProcessors The number of CPUs in the platform.
  10. @return Pointer to a buffer of CPU related configuration data.
  11. @note This service could be called by BSP only.
  12. **/
  13. VOID *
  14. EFIAPI
  15. AesniGetConfigData (
  16. IN UINTN NumberOfProcessors
  17. )
  18. {
  19. UINT64 *ConfigData;
  20. ConfigData = AllocateZeroPool (sizeof (UINT64) * NumberOfProcessors);
  21. ASSERT (ConfigData != NULL);
  22. return ConfigData;
  23. }
  24. /**
  25. Detects if AESNI feature supported on current processor.
  26. @param[in] ProcessorNumber The index of the CPU executing this function.
  27. @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
  28. structure for the CPU executing this function.
  29. @param[in] ConfigData A pointer to the configuration buffer returned
  30. by CPU_FEATURE_GET_CONFIG_DATA. NULL if
  31. CPU_FEATURE_GET_CONFIG_DATA was not provided in
  32. RegisterCpuFeature().
  33. @retval TRUE AESNI feature is supported.
  34. @retval FALSE AESNI feature is not supported.
  35. @note This service could be called by BSP/APs.
  36. **/
  37. BOOLEAN
  38. EFIAPI
  39. AesniSupport (
  40. IN UINTN ProcessorNumber,
  41. IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
  42. IN VOID *ConfigData OPTIONAL
  43. )
  44. {
  45. MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig;
  46. if (CpuInfo->CpuIdVersionInfoEcx.Bits.AESNI == 1) {
  47. MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *)ConfigData;
  48. ASSERT (MsrFeatureConfig != NULL);
  49. MsrFeatureConfig[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);
  50. return TRUE;
  51. }
  52. return FALSE;
  53. }
  54. /**
  55. Initializes AESNI feature to specific state.
  56. @param[in] ProcessorNumber The index of the CPU executing this function.
  57. @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
  58. structure for the CPU executing this function.
  59. @param[in] ConfigData A pointer to the configuration buffer returned
  60. by CPU_FEATURE_GET_CONFIG_DATA. NULL if
  61. CPU_FEATURE_GET_CONFIG_DATA was not provided in
  62. RegisterCpuFeature().
  63. @param[in] State If TRUE, then the AESNI feature must be enabled.
  64. If FALSE, then the AESNI feature must be disabled.
  65. @retval RETURN_SUCCESS AESNI feature is initialized.
  66. @note This service could be called by BSP only.
  67. **/
  68. RETURN_STATUS
  69. EFIAPI
  70. AesniInitialize (
  71. IN UINTN ProcessorNumber,
  72. IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
  73. IN VOID *ConfigData OPTIONAL,
  74. IN BOOLEAN State
  75. )
  76. {
  77. MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig;
  78. //
  79. // SANDY_BRIDGE, SILVERMONT, XEON_5600, XEON_7, and XEON_PHI have the same MSR index,
  80. // Simply use MSR_SANDY_BRIDGE_FEATURE_CONFIG here
  81. //
  82. // The scope of the MSR_SANDY_BRIDGE_FEATURE_CONFIG is Core, only program MSR_FEATURE_CONFIG for thread 0
  83. // of each core. Otherwise, once a thread in the core disabled AES, the other thread will cause GP when
  84. // programming it.
  85. //
  86. if (CpuInfo->ProcessorInfo.Location.Thread == 0) {
  87. MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *)ConfigData;
  88. ASSERT (MsrFeatureConfig != NULL);
  89. if ((MsrFeatureConfig[ProcessorNumber].Bits.AESConfiguration & BIT0) == 0) {
  90. CPU_REGISTER_TABLE_WRITE_FIELD (
  91. ProcessorNumber,
  92. Msr,
  93. MSR_SANDY_BRIDGE_FEATURE_CONFIG,
  94. MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER,
  95. Bits.AESConfiguration,
  96. BIT0 | ((State) ? 0 : BIT1)
  97. );
  98. }
  99. }
  100. return RETURN_SUCCESS;
  101. }