BaseXApicX2ApicLib.c 38 KB

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  1. /** @file
  2. Local APIC Library.
  3. This local APIC library instance supports x2APIC capable processors
  4. which have xAPIC and x2APIC modes.
  5. Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
  6. Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.<BR>
  7. SPDX-License-Identifier: BSD-2-Clause-Patent
  8. **/
  9. #include <Register/Intel/Cpuid.h>
  10. #include <Register/Amd/Cpuid.h>
  11. #include <Register/Intel/Msr.h>
  12. #include <Register/Intel/LocalApic.h>
  13. #include <Library/BaseLib.h>
  14. #include <Library/DebugLib.h>
  15. #include <Library/LocalApicLib.h>
  16. #include <Library/IoLib.h>
  17. #include <Library/TimerLib.h>
  18. #include <Library/PcdLib.h>
  19. #include <Library/UefiCpuLib.h>
  20. //
  21. // Library internal functions
  22. //
  23. /**
  24. Determine if the CPU supports the Local APIC Base Address MSR.
  25. @retval TRUE The CPU supports the Local APIC Base Address MSR.
  26. @retval FALSE The CPU does not support the Local APIC Base Address MSR.
  27. **/
  28. BOOLEAN
  29. LocalApicBaseAddressMsrSupported (
  30. VOID
  31. )
  32. {
  33. UINT32 RegEax;
  34. UINTN FamilyId;
  35. AsmCpuid (1, &RegEax, NULL, NULL, NULL);
  36. FamilyId = BitFieldRead32 (RegEax, 8, 11);
  37. if ((FamilyId == 0x04) || (FamilyId == 0x05)) {
  38. //
  39. // CPUs with a FamilyId of 0x04 or 0x05 do not support the
  40. // Local APIC Base Address MSR
  41. //
  42. return FALSE;
  43. }
  44. return TRUE;
  45. }
  46. /**
  47. Retrieve the base address of local APIC.
  48. @return The base address of local APIC.
  49. **/
  50. UINTN
  51. EFIAPI
  52. GetLocalApicBaseAddress (
  53. VOID
  54. )
  55. {
  56. MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
  57. if (!LocalApicBaseAddressMsrSupported ()) {
  58. //
  59. // If CPU does not support Local APIC Base Address MSR, then retrieve
  60. // Local APIC Base Address from PCD
  61. //
  62. return PcdGet32 (PcdCpuLocalApicBaseAddress);
  63. }
  64. ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
  65. return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) +
  66. (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
  67. }
  68. /**
  69. Set the base address of local APIC.
  70. If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
  71. @param[in] BaseAddress Local APIC base address to be set.
  72. **/
  73. VOID
  74. EFIAPI
  75. SetLocalApicBaseAddress (
  76. IN UINTN BaseAddress
  77. )
  78. {
  79. MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
  80. ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
  81. if (!LocalApicBaseAddressMsrSupported ()) {
  82. //
  83. // Ignore set request of the CPU does not support APIC Base Address MSR
  84. //
  85. return;
  86. }
  87. ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
  88. ApicBaseMsr.Bits.ApicBase = (UINT32)(BaseAddress >> 12);
  89. ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32));
  90. AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
  91. }
  92. /**
  93. Read from a local APIC register.
  94. This function reads from a local APIC register either in xAPIC or x2APIC mode.
  95. It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
  96. accessed using multiple 32-bit loads or stores, so this function only performs
  97. 32-bit read.
  98. @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
  99. It must be 16-byte aligned.
  100. @return 32-bit Value read from the register.
  101. **/
  102. UINT32
  103. EFIAPI
  104. ReadLocalApicReg (
  105. IN UINTN MmioOffset
  106. )
  107. {
  108. UINT32 MsrIndex;
  109. ASSERT ((MmioOffset & 0xf) == 0);
  110. if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
  111. return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset);
  112. } else {
  113. //
  114. // DFR is not supported in x2APIC mode.
  115. //
  116. ASSERT (MmioOffset != XAPIC_ICR_DFR_OFFSET);
  117. //
  118. // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It
  119. // is not supported in this function for simplicity.
  120. //
  121. ASSERT (MmioOffset != XAPIC_ICR_HIGH_OFFSET);
  122. MsrIndex = (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS;
  123. return AsmReadMsr32 (MsrIndex);
  124. }
  125. }
  126. /**
  127. Write to a local APIC register.
  128. This function writes to a local APIC register either in xAPIC or x2APIC mode.
  129. It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
  130. accessed using multiple 32-bit loads or stores, so this function only performs
  131. 32-bit write.
  132. if the register index is invalid or unsupported in current APIC mode, then ASSERT.
  133. @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
  134. It must be 16-byte aligned.
  135. @param Value Value to be written to the register.
  136. **/
  137. VOID
  138. EFIAPI
  139. WriteLocalApicReg (
  140. IN UINTN MmioOffset,
  141. IN UINT32 Value
  142. )
  143. {
  144. UINT32 MsrIndex;
  145. ASSERT ((MmioOffset & 0xf) == 0);
  146. if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
  147. MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value);
  148. } else {
  149. //
  150. // DFR is not supported in x2APIC mode.
  151. //
  152. ASSERT (MmioOffset != XAPIC_ICR_DFR_OFFSET);
  153. //
  154. // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It
  155. // is not supported in this function for simplicity.
  156. //
  157. ASSERT (MmioOffset != XAPIC_ICR_HIGH_OFFSET);
  158. ASSERT (MmioOffset != XAPIC_ICR_LOW_OFFSET);
  159. MsrIndex = (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS;
  160. //
  161. // The serializing semantics of WRMSR are relaxed when writing to the APIC registers.
  162. // Use memory fence here to force the serializing semantics to be consisent with xAPIC mode.
  163. //
  164. MemoryFence ();
  165. AsmWriteMsr32 (MsrIndex, Value);
  166. }
  167. }
  168. /**
  169. Send an IPI by writing to ICR.
  170. This function returns after the IPI has been accepted by the target processor.
  171. @param IcrLow 32-bit value to be written to the low half of ICR.
  172. @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
  173. **/
  174. VOID
  175. SendIpi (
  176. IN UINT32 IcrLow,
  177. IN UINT32 ApicId
  178. )
  179. {
  180. UINT64 MsrValue;
  181. LOCAL_APIC_ICR_LOW IcrLowReg;
  182. UINTN LocalApciBaseAddress;
  183. UINT32 IcrHigh;
  184. BOOLEAN InterruptState;
  185. //
  186. // Legacy APIC or X2APIC?
  187. //
  188. if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
  189. ASSERT (ApicId <= 0xff);
  190. InterruptState = SaveAndDisableInterrupts ();
  191. //
  192. // Get base address of this LAPIC
  193. //
  194. LocalApciBaseAddress = GetLocalApicBaseAddress ();
  195. //
  196. // Save existing contents of ICR high 32 bits
  197. //
  198. IcrHigh = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET);
  199. //
  200. // Wait for DeliveryStatus clear in case a previous IPI
  201. // is still being sent
  202. //
  203. do {
  204. IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);
  205. } while (IcrLowReg.Bits.DeliveryStatus != 0);
  206. //
  207. // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
  208. //
  209. MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
  210. MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET, IcrLow);
  211. //
  212. // Wait for DeliveryStatus clear again
  213. //
  214. do {
  215. IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);
  216. } while (IcrLowReg.Bits.DeliveryStatus != 0);
  217. //
  218. // And restore old contents of ICR high
  219. //
  220. MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh);
  221. SetInterruptState (InterruptState);
  222. } else {
  223. //
  224. // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an
  225. // interrupt in x2APIC mode.
  226. //
  227. MsrValue = LShiftU64 ((UINT64)ApicId, 32) | IcrLow;
  228. AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);
  229. }
  230. }
  231. //
  232. // Library API implementation functions
  233. //
  234. /**
  235. Get the current local APIC mode.
  236. If local APIC is disabled, then ASSERT.
  237. @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
  238. @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
  239. **/
  240. UINTN
  241. EFIAPI
  242. GetApicMode (
  243. VOID
  244. )
  245. {
  246. MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
  247. if (!LocalApicBaseAddressMsrSupported ()) {
  248. //
  249. // If CPU does not support APIC Base Address MSR, then return XAPIC mode
  250. //
  251. return LOCAL_APIC_MODE_XAPIC;
  252. }
  253. ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
  254. //
  255. // Local APIC should have been enabled
  256. //
  257. ASSERT (ApicBaseMsr.Bits.EN != 0);
  258. if (ApicBaseMsr.Bits.EXTD != 0) {
  259. return LOCAL_APIC_MODE_X2APIC;
  260. } else {
  261. return LOCAL_APIC_MODE_XAPIC;
  262. }
  263. }
  264. /**
  265. Set the current local APIC mode.
  266. If the specified local APIC mode is not valid, then ASSERT.
  267. If the specified local APIC mode can't be set as current, then ASSERT.
  268. @param ApicMode APIC mode to be set.
  269. @note This API must not be called from an interrupt handler or SMI handler.
  270. It may result in unpredictable behavior.
  271. **/
  272. VOID
  273. EFIAPI
  274. SetApicMode (
  275. IN UINTN ApicMode
  276. )
  277. {
  278. UINTN CurrentMode;
  279. MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
  280. if (!LocalApicBaseAddressMsrSupported ()) {
  281. //
  282. // Ignore set request if the CPU does not support APIC Base Address MSR
  283. //
  284. return;
  285. }
  286. CurrentMode = GetApicMode ();
  287. if (CurrentMode == LOCAL_APIC_MODE_XAPIC) {
  288. switch (ApicMode) {
  289. case LOCAL_APIC_MODE_XAPIC:
  290. break;
  291. case LOCAL_APIC_MODE_X2APIC:
  292. ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
  293. ApicBaseMsr.Bits.EXTD = 1;
  294. AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
  295. break;
  296. default:
  297. ASSERT (FALSE);
  298. }
  299. } else {
  300. switch (ApicMode) {
  301. case LOCAL_APIC_MODE_XAPIC:
  302. //
  303. // Transition from x2APIC mode to xAPIC mode is a two-step process:
  304. // x2APIC -> Local APIC disabled -> xAPIC
  305. //
  306. ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
  307. ApicBaseMsr.Bits.EXTD = 0;
  308. ApicBaseMsr.Bits.EN = 0;
  309. AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
  310. ApicBaseMsr.Bits.EN = 1;
  311. AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
  312. break;
  313. case LOCAL_APIC_MODE_X2APIC:
  314. break;
  315. default:
  316. ASSERT (FALSE);
  317. }
  318. }
  319. }
  320. /**
  321. Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
  322. In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
  323. In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
  324. the 32-bit local APIC ID is returned as initial APIC ID.
  325. @return 32-bit initial local APIC ID of the executing processor.
  326. **/
  327. UINT32
  328. EFIAPI
  329. GetInitialApicId (
  330. VOID
  331. )
  332. {
  333. UINT32 ApicId;
  334. UINT32 MaxCpuIdIndex;
  335. UINT32 RegEbx;
  336. if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
  337. //
  338. // Get the max index of basic CPUID
  339. //
  340. AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
  341. //
  342. // If CPUID Leaf B is supported,
  343. // And CPUID.0BH:EBX[15:0] reports a non-zero value,
  344. // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
  345. // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
  346. //
  347. if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
  348. AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, &RegEbx, NULL, &ApicId);
  349. if ((RegEbx & (BIT16 - 1)) != 0) {
  350. return ApicId;
  351. }
  352. }
  353. AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
  354. return RegEbx >> 24;
  355. } else {
  356. return GetApicId ();
  357. }
  358. }
  359. /**
  360. Get the local APIC ID of the executing processor.
  361. @return 32-bit local APIC ID of the executing processor.
  362. **/
  363. UINT32
  364. EFIAPI
  365. GetApicId (
  366. VOID
  367. )
  368. {
  369. UINT32 ApicId;
  370. UINT32 InitApicId;
  371. ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
  372. if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
  373. ApicId = ((InitApicId = GetInitialApicId ()) < 0x100) ? (ApicId >> 24) : InitApicId;
  374. }
  375. return ApicId;
  376. }
  377. /**
  378. Get the value of the local APIC version register.
  379. @return the value of the local APIC version register.
  380. **/
  381. UINT32
  382. EFIAPI
  383. GetApicVersion (
  384. VOID
  385. )
  386. {
  387. return ReadLocalApicReg (XAPIC_VERSION_OFFSET);
  388. }
  389. /**
  390. Send a Fixed IPI to a specified target processor.
  391. This function returns after the IPI has been accepted by the target processor.
  392. @param ApicId The local APIC ID of the target processor.
  393. @param Vector The vector number of the interrupt being sent.
  394. **/
  395. VOID
  396. EFIAPI
  397. SendFixedIpi (
  398. IN UINT32 ApicId,
  399. IN UINT8 Vector
  400. )
  401. {
  402. LOCAL_APIC_ICR_LOW IcrLow;
  403. IcrLow.Uint32 = 0;
  404. IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
  405. IcrLow.Bits.Level = 1;
  406. IcrLow.Bits.Vector = Vector;
  407. SendIpi (IcrLow.Uint32, ApicId);
  408. }
  409. /**
  410. Send a Fixed IPI to all processors excluding self.
  411. This function returns after the IPI has been accepted by the target processors.
  412. @param Vector The vector number of the interrupt being sent.
  413. **/
  414. VOID
  415. EFIAPI
  416. SendFixedIpiAllExcludingSelf (
  417. IN UINT8 Vector
  418. )
  419. {
  420. LOCAL_APIC_ICR_LOW IcrLow;
  421. IcrLow.Uint32 = 0;
  422. IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
  423. IcrLow.Bits.Level = 1;
  424. IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
  425. IcrLow.Bits.Vector = Vector;
  426. SendIpi (IcrLow.Uint32, 0);
  427. }
  428. /**
  429. Send a SMI IPI to a specified target processor.
  430. This function returns after the IPI has been accepted by the target processor.
  431. @param ApicId Specify the local APIC ID of the target processor.
  432. **/
  433. VOID
  434. EFIAPI
  435. SendSmiIpi (
  436. IN UINT32 ApicId
  437. )
  438. {
  439. LOCAL_APIC_ICR_LOW IcrLow;
  440. IcrLow.Uint32 = 0;
  441. IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
  442. IcrLow.Bits.Level = 1;
  443. SendIpi (IcrLow.Uint32, ApicId);
  444. }
  445. /**
  446. Send a SMI IPI to all processors excluding self.
  447. This function returns after the IPI has been accepted by the target processors.
  448. **/
  449. VOID
  450. EFIAPI
  451. SendSmiIpiAllExcludingSelf (
  452. VOID
  453. )
  454. {
  455. LOCAL_APIC_ICR_LOW IcrLow;
  456. IcrLow.Uint32 = 0;
  457. IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
  458. IcrLow.Bits.Level = 1;
  459. IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
  460. SendIpi (IcrLow.Uint32, 0);
  461. }
  462. /**
  463. Send an INIT IPI to a specified target processor.
  464. This function returns after the IPI has been accepted by the target processor.
  465. @param ApicId Specify the local APIC ID of the target processor.
  466. **/
  467. VOID
  468. EFIAPI
  469. SendInitIpi (
  470. IN UINT32 ApicId
  471. )
  472. {
  473. LOCAL_APIC_ICR_LOW IcrLow;
  474. IcrLow.Uint32 = 0;
  475. IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
  476. IcrLow.Bits.Level = 1;
  477. SendIpi (IcrLow.Uint32, ApicId);
  478. }
  479. /**
  480. Send an INIT IPI to all processors excluding self.
  481. This function returns after the IPI has been accepted by the target processors.
  482. **/
  483. VOID
  484. EFIAPI
  485. SendInitIpiAllExcludingSelf (
  486. VOID
  487. )
  488. {
  489. LOCAL_APIC_ICR_LOW IcrLow;
  490. IcrLow.Uint32 = 0;
  491. IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
  492. IcrLow.Bits.Level = 1;
  493. IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
  494. SendIpi (IcrLow.Uint32, 0);
  495. }
  496. /**
  497. Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
  498. This function returns after the IPI has been accepted by the target processor.
  499. if StartupRoutine >= 1M, then ASSERT.
  500. if StartupRoutine is not multiple of 4K, then ASSERT.
  501. @param ApicId Specify the local APIC ID of the target processor.
  502. @param StartupRoutine Points to a start-up routine which is below 1M physical
  503. address and 4K aligned.
  504. **/
  505. VOID
  506. EFIAPI
  507. SendInitSipiSipi (
  508. IN UINT32 ApicId,
  509. IN UINT32 StartupRoutine
  510. )
  511. {
  512. LOCAL_APIC_ICR_LOW IcrLow;
  513. ASSERT (StartupRoutine < 0x100000);
  514. ASSERT ((StartupRoutine & 0xfff) == 0);
  515. SendInitIpi (ApicId);
  516. MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
  517. IcrLow.Uint32 = 0;
  518. IcrLow.Bits.Vector = (StartupRoutine >> 12);
  519. IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
  520. IcrLow.Bits.Level = 1;
  521. SendIpi (IcrLow.Uint32, ApicId);
  522. if (!StandardSignatureIsAuthenticAMD ()) {
  523. MicroSecondDelay (200);
  524. SendIpi (IcrLow.Uint32, ApicId);
  525. }
  526. }
  527. /**
  528. Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
  529. This function returns after the IPI has been accepted by the target processors.
  530. if StartupRoutine >= 1M, then ASSERT.
  531. if StartupRoutine is not multiple of 4K, then ASSERT.
  532. @param StartupRoutine Points to a start-up routine which is below 1M physical
  533. address and 4K aligned.
  534. **/
  535. VOID
  536. EFIAPI
  537. SendInitSipiSipiAllExcludingSelf (
  538. IN UINT32 StartupRoutine
  539. )
  540. {
  541. LOCAL_APIC_ICR_LOW IcrLow;
  542. ASSERT (StartupRoutine < 0x100000);
  543. ASSERT ((StartupRoutine & 0xfff) == 0);
  544. SendInitIpiAllExcludingSelf ();
  545. MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
  546. IcrLow.Uint32 = 0;
  547. IcrLow.Bits.Vector = (StartupRoutine >> 12);
  548. IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
  549. IcrLow.Bits.Level = 1;
  550. IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
  551. SendIpi (IcrLow.Uint32, 0);
  552. if (!StandardSignatureIsAuthenticAMD ()) {
  553. MicroSecondDelay (200);
  554. SendIpi (IcrLow.Uint32, 0);
  555. }
  556. }
  557. /**
  558. Initialize the state of the SoftwareEnable bit in the Local APIC
  559. Spurious Interrupt Vector register.
  560. @param Enable If TRUE, then set SoftwareEnable to 1
  561. If FALSE, then set SoftwareEnable to 0.
  562. **/
  563. VOID
  564. EFIAPI
  565. InitializeLocalApicSoftwareEnable (
  566. IN BOOLEAN Enable
  567. )
  568. {
  569. LOCAL_APIC_SVR Svr;
  570. //
  571. // Set local APIC software-enabled bit.
  572. //
  573. Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
  574. if (Enable) {
  575. if (Svr.Bits.SoftwareEnable == 0) {
  576. Svr.Bits.SoftwareEnable = 1;
  577. WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
  578. }
  579. } else {
  580. if (Svr.Bits.SoftwareEnable == 1) {
  581. Svr.Bits.SoftwareEnable = 0;
  582. WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
  583. }
  584. }
  585. }
  586. /**
  587. Programming Virtual Wire Mode.
  588. This function programs the local APIC for virtual wire mode following
  589. the example described in chapter A.3 of the MP 1.4 spec.
  590. IOxAPIC is not involved in this type of virtual wire mode.
  591. **/
  592. VOID
  593. EFIAPI
  594. ProgramVirtualWireMode (
  595. VOID
  596. )
  597. {
  598. LOCAL_APIC_SVR Svr;
  599. LOCAL_APIC_LVT_LINT Lint;
  600. //
  601. // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
  602. //
  603. Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
  604. Svr.Bits.SpuriousVector = 0xf;
  605. Svr.Bits.SoftwareEnable = 1;
  606. WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
  607. //
  608. // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
  609. //
  610. Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
  611. Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
  612. Lint.Bits.InputPinPolarity = 0;
  613. Lint.Bits.TriggerMode = 0;
  614. Lint.Bits.Mask = 0;
  615. WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
  616. //
  617. // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
  618. //
  619. Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
  620. Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
  621. Lint.Bits.InputPinPolarity = 0;
  622. Lint.Bits.TriggerMode = 0;
  623. Lint.Bits.Mask = 0;
  624. WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
  625. }
  626. /**
  627. Disable LINT0 & LINT1 interrupts.
  628. This function sets the mask flag in the LVT LINT0 & LINT1 registers.
  629. **/
  630. VOID
  631. EFIAPI
  632. DisableLvtInterrupts (
  633. VOID
  634. )
  635. {
  636. LOCAL_APIC_LVT_LINT LvtLint;
  637. LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
  638. LvtLint.Bits.Mask = 1;
  639. WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
  640. LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
  641. LvtLint.Bits.Mask = 1;
  642. WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
  643. }
  644. /**
  645. Read the initial count value from the init-count register.
  646. @return The initial count value read from the init-count register.
  647. **/
  648. UINT32
  649. EFIAPI
  650. GetApicTimerInitCount (
  651. VOID
  652. )
  653. {
  654. return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);
  655. }
  656. /**
  657. Read the current count value from the current-count register.
  658. @return The current count value read from the current-count register.
  659. **/
  660. UINT32
  661. EFIAPI
  662. GetApicTimerCurrentCount (
  663. VOID
  664. )
  665. {
  666. return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);
  667. }
  668. /**
  669. Initialize the local APIC timer.
  670. The local APIC timer is initialized and enabled.
  671. @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
  672. If it is 0, then use the current divide value in the DCR.
  673. @param InitCount The initial count value.
  674. @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
  675. @param Vector The timer interrupt vector number.
  676. **/
  677. VOID
  678. EFIAPI
  679. InitializeApicTimer (
  680. IN UINTN DivideValue,
  681. IN UINT32 InitCount,
  682. IN BOOLEAN PeriodicMode,
  683. IN UINT8 Vector
  684. )
  685. {
  686. LOCAL_APIC_DCR Dcr;
  687. LOCAL_APIC_LVT_TIMER LvtTimer;
  688. UINT32 Divisor;
  689. //
  690. // Ensure local APIC is in software-enabled state.
  691. //
  692. InitializeLocalApicSoftwareEnable (TRUE);
  693. //
  694. // Program init-count register.
  695. //
  696. WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);
  697. if (DivideValue != 0) {
  698. ASSERT (DivideValue <= 128);
  699. ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue));
  700. Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
  701. Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
  702. Dcr.Bits.DivideValue1 = (Divisor & 0x3);
  703. Dcr.Bits.DivideValue2 = (Divisor >> 2);
  704. WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
  705. }
  706. //
  707. // Enable APIC timer interrupt with specified timer mode.
  708. //
  709. LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
  710. if (PeriodicMode) {
  711. LvtTimer.Bits.TimerMode = 1;
  712. } else {
  713. LvtTimer.Bits.TimerMode = 0;
  714. }
  715. LvtTimer.Bits.Mask = 0;
  716. LvtTimer.Bits.Vector = Vector;
  717. WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
  718. }
  719. /**
  720. Get the state of the local APIC timer.
  721. This function will ASSERT if the local APIC is not software enabled.
  722. @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
  723. @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
  724. @param Vector Return the timer interrupt vector number.
  725. **/
  726. VOID
  727. EFIAPI
  728. GetApicTimerState (
  729. OUT UINTN *DivideValue OPTIONAL,
  730. OUT BOOLEAN *PeriodicMode OPTIONAL,
  731. OUT UINT8 *Vector OPTIONAL
  732. )
  733. {
  734. UINT32 Divisor;
  735. LOCAL_APIC_DCR Dcr;
  736. LOCAL_APIC_LVT_TIMER LvtTimer;
  737. //
  738. // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
  739. // Vector Register.
  740. // This bit will be 1, if local APIC is software enabled.
  741. //
  742. ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
  743. if (DivideValue != NULL) {
  744. Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
  745. Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
  746. Divisor = (Divisor + 1) & 0x7;
  747. *DivideValue = ((UINTN)1) << Divisor;
  748. }
  749. if ((PeriodicMode != NULL) || (Vector != NULL)) {
  750. LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
  751. if (PeriodicMode != NULL) {
  752. if (LvtTimer.Bits.TimerMode == 1) {
  753. *PeriodicMode = TRUE;
  754. } else {
  755. *PeriodicMode = FALSE;
  756. }
  757. }
  758. if (Vector != NULL) {
  759. *Vector = (UINT8)LvtTimer.Bits.Vector;
  760. }
  761. }
  762. }
  763. /**
  764. Enable the local APIC timer interrupt.
  765. **/
  766. VOID
  767. EFIAPI
  768. EnableApicTimerInterrupt (
  769. VOID
  770. )
  771. {
  772. LOCAL_APIC_LVT_TIMER LvtTimer;
  773. LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
  774. LvtTimer.Bits.Mask = 0;
  775. WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
  776. }
  777. /**
  778. Disable the local APIC timer interrupt.
  779. **/
  780. VOID
  781. EFIAPI
  782. DisableApicTimerInterrupt (
  783. VOID
  784. )
  785. {
  786. LOCAL_APIC_LVT_TIMER LvtTimer;
  787. LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
  788. LvtTimer.Bits.Mask = 1;
  789. WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
  790. }
  791. /**
  792. Get the local APIC timer interrupt state.
  793. @retval TRUE The local APIC timer interrupt is enabled.
  794. @retval FALSE The local APIC timer interrupt is disabled.
  795. **/
  796. BOOLEAN
  797. EFIAPI
  798. GetApicTimerInterruptState (
  799. VOID
  800. )
  801. {
  802. LOCAL_APIC_LVT_TIMER LvtTimer;
  803. LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
  804. return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
  805. }
  806. /**
  807. Send EOI to the local APIC.
  808. **/
  809. VOID
  810. EFIAPI
  811. SendApicEoi (
  812. VOID
  813. )
  814. {
  815. WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);
  816. }
  817. /**
  818. Get the 32-bit address that a device should use to send a Message Signaled
  819. Interrupt (MSI) to the Local APIC of the currently executing processor.
  820. @return 32-bit address used to send an MSI to the Local APIC.
  821. **/
  822. UINT32
  823. EFIAPI
  824. GetApicMsiAddress (
  825. VOID
  826. )
  827. {
  828. LOCAL_APIC_MSI_ADDRESS MsiAddress;
  829. //
  830. // Return address for an MSI interrupt to be delivered only to the APIC ID
  831. // of the currently executing processor.
  832. //
  833. MsiAddress.Uint32 = 0;
  834. MsiAddress.Bits.BaseAddress = 0xFEE;
  835. MsiAddress.Bits.DestinationId = GetApicId ();
  836. return MsiAddress.Uint32;
  837. }
  838. /**
  839. Get the 64-bit data value that a device should use to send a Message Signaled
  840. Interrupt (MSI) to the Local APIC of the currently executing processor.
  841. If Vector is not in range 0x10..0xFE, then ASSERT().
  842. If DeliveryMode is not supported, then ASSERT().
  843. @param Vector The 8-bit interrupt vector associated with the MSI.
  844. Must be in the range 0x10..0xFE
  845. @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
  846. is handled. The only supported values are:
  847. 0: LOCAL_APIC_DELIVERY_MODE_FIXED
  848. 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
  849. 2: LOCAL_APIC_DELIVERY_MODE_SMI
  850. 4: LOCAL_APIC_DELIVERY_MODE_NMI
  851. 5: LOCAL_APIC_DELIVERY_MODE_INIT
  852. 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
  853. @param LevelTriggered TRUE specifies a level triggered interrupt.
  854. FALSE specifies an edge triggered interrupt.
  855. @param AssertionLevel Ignored if LevelTriggered is FALSE.
  856. TRUE specifies a level triggered interrupt that active
  857. when the interrupt line is asserted.
  858. FALSE specifies a level triggered interrupt that active
  859. when the interrupt line is deasserted.
  860. @return 64-bit data value used to send an MSI to the Local APIC.
  861. **/
  862. UINT64
  863. EFIAPI
  864. GetApicMsiValue (
  865. IN UINT8 Vector,
  866. IN UINTN DeliveryMode,
  867. IN BOOLEAN LevelTriggered,
  868. IN BOOLEAN AssertionLevel
  869. )
  870. {
  871. LOCAL_APIC_MSI_DATA MsiData;
  872. ASSERT (Vector >= 0x10 && Vector <= 0xFE);
  873. ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
  874. MsiData.Uint64 = 0;
  875. MsiData.Bits.Vector = Vector;
  876. MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;
  877. if (LevelTriggered) {
  878. MsiData.Bits.TriggerMode = 1;
  879. if (AssertionLevel) {
  880. MsiData.Bits.Level = 1;
  881. }
  882. }
  883. return MsiData.Uint64;
  884. }
  885. /**
  886. Get Package ID/Core ID/Thread ID of a processor.
  887. The algorithm assumes the target system has symmetry across physical
  888. package boundaries with respect to the number of logical processors
  889. per package, number of cores per package.
  890. @param[in] InitialApicId Initial APIC ID of the target logical processor.
  891. @param[out] Package Returns the processor package ID.
  892. @param[out] Core Returns the processor core ID.
  893. @param[out] Thread Returns the processor thread ID.
  894. **/
  895. VOID
  896. EFIAPI
  897. GetProcessorLocationByApicId (
  898. IN UINT32 InitialApicId,
  899. OUT UINT32 *Package OPTIONAL,
  900. OUT UINT32 *Core OPTIONAL,
  901. OUT UINT32 *Thread OPTIONAL
  902. )
  903. {
  904. BOOLEAN TopologyLeafSupported;
  905. CPUID_VERSION_INFO_EBX VersionInfoEbx;
  906. CPUID_VERSION_INFO_EDX VersionInfoEdx;
  907. CPUID_CACHE_PARAMS_EAX CacheParamsEax;
  908. CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
  909. CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
  910. CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
  911. CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
  912. CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
  913. CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
  914. UINT32 MaxStandardCpuIdIndex;
  915. UINT32 MaxExtendedCpuIdIndex;
  916. UINT32 SubIndex;
  917. UINTN LevelType;
  918. UINT32 MaxLogicProcessorsPerPackage;
  919. UINT32 MaxCoresPerPackage;
  920. UINTN ThreadBits;
  921. UINTN CoreBits;
  922. //
  923. // Check if the processor is capable of supporting more than one logical processor.
  924. //
  925. AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
  926. if (VersionInfoEdx.Bits.HTT == 0) {
  927. if (Thread != NULL) {
  928. *Thread = 0;
  929. }
  930. if (Core != NULL) {
  931. *Core = 0;
  932. }
  933. if (Package != NULL) {
  934. *Package = 0;
  935. }
  936. return;
  937. }
  938. //
  939. // Assume three-level mapping of APIC ID: Package|Core|Thread.
  940. //
  941. ThreadBits = 0;
  942. CoreBits = 0;
  943. //
  944. // Get max index of CPUID
  945. //
  946. AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
  947. AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
  948. //
  949. // If the extended topology enumeration leaf is available, it
  950. // is the preferred mechanism for enumerating topology.
  951. //
  952. TopologyLeafSupported = FALSE;
  953. if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
  954. AsmCpuidEx (
  955. CPUID_EXTENDED_TOPOLOGY,
  956. 0,
  957. &ExtendedTopologyEax.Uint32,
  958. &ExtendedTopologyEbx.Uint32,
  959. &ExtendedTopologyEcx.Uint32,
  960. NULL
  961. );
  962. //
  963. // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
  964. // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
  965. // supported on that processor.
  966. //
  967. if (ExtendedTopologyEbx.Uint32 != 0) {
  968. TopologyLeafSupported = TRUE;
  969. //
  970. // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
  971. // the SMT sub-field of x2APIC ID.
  972. //
  973. LevelType = ExtendedTopologyEcx.Bits.LevelType;
  974. ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
  975. ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
  976. //
  977. // Software must not assume any "level type" encoding
  978. // value to be related to any sub-leaf index, except sub-leaf 0.
  979. //
  980. SubIndex = 1;
  981. do {
  982. AsmCpuidEx (
  983. CPUID_EXTENDED_TOPOLOGY,
  984. SubIndex,
  985. &ExtendedTopologyEax.Uint32,
  986. NULL,
  987. &ExtendedTopologyEcx.Uint32,
  988. NULL
  989. );
  990. LevelType = ExtendedTopologyEcx.Bits.LevelType;
  991. if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
  992. CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
  993. break;
  994. }
  995. SubIndex++;
  996. } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
  997. }
  998. }
  999. if (!TopologyLeafSupported) {
  1000. //
  1001. // Get logical processor count
  1002. //
  1003. AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
  1004. MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
  1005. //
  1006. // Assume single-core processor
  1007. //
  1008. MaxCoresPerPackage = 1;
  1009. //
  1010. // Check for topology extensions on AMD processor
  1011. //
  1012. if (StandardSignatureIsAuthenticAMD ()) {
  1013. if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
  1014. AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
  1015. if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
  1016. //
  1017. // Account for max possible thread count to decode ApicId
  1018. //
  1019. AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
  1020. MaxLogicProcessorsPerPackage = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
  1021. //
  1022. // Get cores per processor package
  1023. //
  1024. AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);
  1025. MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
  1026. }
  1027. }
  1028. } else {
  1029. //
  1030. // Extract core count based on CACHE information
  1031. //
  1032. if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
  1033. AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
  1034. if (CacheParamsEax.Uint32 != 0) {
  1035. MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
  1036. }
  1037. }
  1038. }
  1039. ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
  1040. CoreBits = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1);
  1041. }
  1042. if (Thread != NULL) {
  1043. *Thread = InitialApicId & ((1 << ThreadBits) - 1);
  1044. }
  1045. if (Core != NULL) {
  1046. *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
  1047. }
  1048. if (Package != NULL) {
  1049. *Package = (InitialApicId >> (ThreadBits + CoreBits));
  1050. }
  1051. }
  1052. /**
  1053. Get Package ID/Die ID/Tile ID/Module ID/Core ID/Thread ID of a processor.
  1054. The algorithm assumes the target system has symmetry across physical
  1055. package boundaries with respect to the number of threads per core, number of
  1056. cores per module, number of modules per tile, number of tiles per die, number
  1057. of dies per package.
  1058. @param[in] InitialApicId Initial APIC ID of the target logical processor.
  1059. @param[out] Package Returns the processor package ID.
  1060. @param[out] Die Returns the processor die ID.
  1061. @param[out] Tile Returns the processor tile ID.
  1062. @param[out] Module Returns the processor module ID.
  1063. @param[out] Core Returns the processor core ID.
  1064. @param[out] Thread Returns the processor thread ID.
  1065. **/
  1066. VOID
  1067. EFIAPI
  1068. GetProcessorLocation2ByApicId (
  1069. IN UINT32 InitialApicId,
  1070. OUT UINT32 *Package OPTIONAL,
  1071. OUT UINT32 *Die OPTIONAL,
  1072. OUT UINT32 *Tile OPTIONAL,
  1073. OUT UINT32 *Module OPTIONAL,
  1074. OUT UINT32 *Core OPTIONAL,
  1075. OUT UINT32 *Thread OPTIONAL
  1076. )
  1077. {
  1078. CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
  1079. CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
  1080. UINT32 MaxStandardCpuIdIndex;
  1081. UINT32 Index;
  1082. UINTN LevelType;
  1083. UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
  1084. UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
  1085. for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {
  1086. Bits[LevelType] = 0;
  1087. }
  1088. //
  1089. // Get max index of CPUID
  1090. //
  1091. AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
  1092. if (MaxStandardCpuIdIndex < CPUID_V2_EXTENDED_TOPOLOGY) {
  1093. if (Die != NULL) {
  1094. *Die = 0;
  1095. }
  1096. if (Tile != NULL) {
  1097. *Tile = 0;
  1098. }
  1099. if (Module != NULL) {
  1100. *Module = 0;
  1101. }
  1102. GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);
  1103. return;
  1104. }
  1105. //
  1106. // If the V2 extended topology enumeration leaf is available, it
  1107. // is the preferred mechanism for enumerating topology.
  1108. //
  1109. for (Index = 0; ; Index++) {
  1110. AsmCpuidEx (
  1111. CPUID_V2_EXTENDED_TOPOLOGY,
  1112. Index,
  1113. &ExtendedTopologyEax.Uint32,
  1114. NULL,
  1115. &ExtendedTopologyEcx.Uint32,
  1116. NULL
  1117. );
  1118. LevelType = ExtendedTopologyEcx.Bits.LevelType;
  1119. //
  1120. // first level reported should be SMT.
  1121. //
  1122. ASSERT ((Index != 0) || (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT));
  1123. if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
  1124. break;
  1125. }
  1126. ASSERT (LevelType < ARRAY_SIZE (Bits));
  1127. Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;
  1128. }
  1129. for (LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE; LevelType < ARRAY_SIZE (Bits); LevelType++) {
  1130. //
  1131. // If there are more levels between level-1 (low-level) and level-2 (high-level), the unknown levels will be ignored
  1132. // and treated as an extension of the last known level (i.e., level-1 in this case).
  1133. //
  1134. if (Bits[LevelType] == 0) {
  1135. Bits[LevelType] = Bits[LevelType - 1];
  1136. }
  1137. }
  1138. Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;
  1139. Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE] = Die;
  1140. Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE] = Tile;
  1141. Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE] = Module;
  1142. Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE] = Core;
  1143. Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT] = Thread;
  1144. Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;
  1145. for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
  1146. ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1
  1147. ; LevelType++
  1148. )
  1149. {
  1150. if (Location[LevelType] != NULL) {
  1151. //
  1152. // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique
  1153. // topology ID of the next level type.
  1154. //
  1155. *Location[LevelType] = InitialApicId >> Bits[LevelType - 1];
  1156. //
  1157. // Bits[i] - Bits[i-1] holds the number of bits for the next ONE level type.
  1158. //
  1159. *Location[LevelType] &= (1 << (Bits[LevelType] - Bits[LevelType - 1])) - 1;
  1160. }
  1161. }
  1162. }