BaseXApicLib.c 35 KB

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  1. /** @file
  2. Local APIC Library.
  3. This local APIC library instance supports xAPIC mode only.
  4. Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
  5. Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.<BR>
  6. SPDX-License-Identifier: BSD-2-Clause-Patent
  7. **/
  8. #include <Register/Intel/Cpuid.h>
  9. #include <Register/Amd/Cpuid.h>
  10. #include <Register/Intel/Msr.h>
  11. #include <Register/Intel/LocalApic.h>
  12. #include <Library/BaseLib.h>
  13. #include <Library/DebugLib.h>
  14. #include <Library/LocalApicLib.h>
  15. #include <Library/IoLib.h>
  16. #include <Library/TimerLib.h>
  17. #include <Library/PcdLib.h>
  18. #include <Library/UefiCpuLib.h>
  19. //
  20. // Library internal functions
  21. //
  22. /**
  23. Determine if the CPU supports the Local APIC Base Address MSR.
  24. @retval TRUE The CPU supports the Local APIC Base Address MSR.
  25. @retval FALSE The CPU does not support the Local APIC Base Address MSR.
  26. **/
  27. BOOLEAN
  28. LocalApicBaseAddressMsrSupported (
  29. VOID
  30. )
  31. {
  32. UINT32 RegEax;
  33. UINTN FamilyId;
  34. AsmCpuid (1, &RegEax, NULL, NULL, NULL);
  35. FamilyId = BitFieldRead32 (RegEax, 8, 11);
  36. if ((FamilyId == 0x04) || (FamilyId == 0x05)) {
  37. //
  38. // CPUs with a FamilyId of 0x04 or 0x05 do not support the
  39. // Local APIC Base Address MSR
  40. //
  41. return FALSE;
  42. }
  43. return TRUE;
  44. }
  45. /**
  46. Retrieve the base address of local APIC.
  47. @return The base address of local APIC.
  48. **/
  49. UINTN
  50. EFIAPI
  51. GetLocalApicBaseAddress (
  52. VOID
  53. )
  54. {
  55. MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
  56. if (!LocalApicBaseAddressMsrSupported ()) {
  57. //
  58. // If CPU does not support Local APIC Base Address MSR, then retrieve
  59. // Local APIC Base Address from PCD
  60. //
  61. return PcdGet32 (PcdCpuLocalApicBaseAddress);
  62. }
  63. ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
  64. return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) +
  65. (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
  66. }
  67. /**
  68. Set the base address of local APIC.
  69. If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
  70. @param[in] BaseAddress Local APIC base address to be set.
  71. **/
  72. VOID
  73. EFIAPI
  74. SetLocalApicBaseAddress (
  75. IN UINTN BaseAddress
  76. )
  77. {
  78. MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
  79. ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
  80. if (!LocalApicBaseAddressMsrSupported ()) {
  81. //
  82. // Ignore set request if the CPU does not support APIC Base Address MSR
  83. //
  84. return;
  85. }
  86. ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
  87. ApicBaseMsr.Bits.ApicBase = (UINT32)(BaseAddress >> 12);
  88. ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32));
  89. AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
  90. }
  91. /**
  92. Read from a local APIC register.
  93. This function reads from a local APIC register either in xAPIC or x2APIC mode.
  94. It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
  95. accessed using multiple 32-bit loads or stores, so this function only performs
  96. 32-bit read.
  97. @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
  98. It must be 16-byte aligned.
  99. @return 32-bit Value read from the register.
  100. **/
  101. UINT32
  102. EFIAPI
  103. ReadLocalApicReg (
  104. IN UINTN MmioOffset
  105. )
  106. {
  107. ASSERT ((MmioOffset & 0xf) == 0);
  108. ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
  109. return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset);
  110. }
  111. /**
  112. Write to a local APIC register.
  113. This function writes to a local APIC register either in xAPIC or x2APIC mode.
  114. It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
  115. accessed using multiple 32-bit loads or stores, so this function only performs
  116. 32-bit write.
  117. if the register index is invalid or unsupported in current APIC mode, then ASSERT.
  118. @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
  119. It must be 16-byte aligned.
  120. @param Value Value to be written to the register.
  121. **/
  122. VOID
  123. EFIAPI
  124. WriteLocalApicReg (
  125. IN UINTN MmioOffset,
  126. IN UINT32 Value
  127. )
  128. {
  129. ASSERT ((MmioOffset & 0xf) == 0);
  130. ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
  131. MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value);
  132. }
  133. /**
  134. Send an IPI by writing to ICR.
  135. This function returns after the IPI has been accepted by the target processor.
  136. @param IcrLow 32-bit value to be written to the low half of ICR.
  137. @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
  138. **/
  139. VOID
  140. SendIpi (
  141. IN UINT32 IcrLow,
  142. IN UINT32 ApicId
  143. )
  144. {
  145. LOCAL_APIC_ICR_LOW IcrLowReg;
  146. UINT32 IcrHigh;
  147. BOOLEAN InterruptState;
  148. ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
  149. ASSERT (ApicId <= 0xff);
  150. InterruptState = SaveAndDisableInterrupts ();
  151. //
  152. // Save existing contents of ICR high 32 bits
  153. //
  154. IcrHigh = ReadLocalApicReg (XAPIC_ICR_HIGH_OFFSET);
  155. //
  156. // Wait for DeliveryStatus clear in case a previous IPI
  157. // is still being sent
  158. //
  159. do {
  160. IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);
  161. } while (IcrLowReg.Bits.DeliveryStatus != 0);
  162. //
  163. // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
  164. //
  165. WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
  166. WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);
  167. //
  168. // Wait for DeliveryStatus clear again
  169. //
  170. do {
  171. IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);
  172. } while (IcrLowReg.Bits.DeliveryStatus != 0);
  173. //
  174. // And restore old contents of ICR high
  175. //
  176. WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh);
  177. SetInterruptState (InterruptState);
  178. }
  179. //
  180. // Library API implementation functions
  181. //
  182. /**
  183. Get the current local APIC mode.
  184. If local APIC is disabled, then ASSERT.
  185. @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
  186. @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
  187. **/
  188. UINTN
  189. EFIAPI
  190. GetApicMode (
  191. VOID
  192. )
  193. {
  194. DEBUG_CODE_BEGIN ();
  195. {
  196. MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
  197. //
  198. // Check to see if the CPU supports the APIC Base Address MSR
  199. //
  200. if (LocalApicBaseAddressMsrSupported ()) {
  201. ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
  202. //
  203. // Local APIC should have been enabled
  204. //
  205. ASSERT (ApicBaseMsr.Bits.EN != 0);
  206. ASSERT (ApicBaseMsr.Bits.EXTD == 0);
  207. }
  208. }
  209. DEBUG_CODE_END ();
  210. return LOCAL_APIC_MODE_XAPIC;
  211. }
  212. /**
  213. Set the current local APIC mode.
  214. If the specified local APIC mode is not valid, then ASSERT.
  215. If the specified local APIC mode can't be set as current, then ASSERT.
  216. @param ApicMode APIC mode to be set.
  217. @note This API must not be called from an interrupt handler or SMI handler.
  218. It may result in unpredictable behavior.
  219. **/
  220. VOID
  221. EFIAPI
  222. SetApicMode (
  223. IN UINTN ApicMode
  224. )
  225. {
  226. ASSERT (ApicMode == LOCAL_APIC_MODE_XAPIC);
  227. ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
  228. }
  229. /**
  230. Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
  231. In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
  232. In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
  233. the 32-bit local APIC ID is returned as initial APIC ID.
  234. @return 32-bit initial local APIC ID of the executing processor.
  235. **/
  236. UINT32
  237. EFIAPI
  238. GetInitialApicId (
  239. VOID
  240. )
  241. {
  242. UINT32 ApicId;
  243. UINT32 MaxCpuIdIndex;
  244. UINT32 RegEbx;
  245. ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
  246. //
  247. // Get the max index of basic CPUID
  248. //
  249. AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
  250. //
  251. // If CPUID Leaf B is supported,
  252. // And CPUID.0BH:EBX[15:0] reports a non-zero value,
  253. // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
  254. // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
  255. //
  256. if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
  257. AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, &RegEbx, NULL, &ApicId);
  258. if ((RegEbx & (BIT16 - 1)) != 0) {
  259. return ApicId;
  260. }
  261. }
  262. AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
  263. return RegEbx >> 24;
  264. }
  265. /**
  266. Get the local APIC ID of the executing processor.
  267. @return 32-bit local APIC ID of the executing processor.
  268. **/
  269. UINT32
  270. EFIAPI
  271. GetApicId (
  272. VOID
  273. )
  274. {
  275. UINT32 ApicId;
  276. ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
  277. if ((ApicId = GetInitialApicId ()) < 0x100) {
  278. //
  279. // If the initial local APIC ID is less 0x100, read APIC ID from
  280. // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.
  281. //
  282. ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
  283. ApicId >>= 24;
  284. }
  285. return ApicId;
  286. }
  287. /**
  288. Get the value of the local APIC version register.
  289. @return the value of the local APIC version register.
  290. **/
  291. UINT32
  292. EFIAPI
  293. GetApicVersion (
  294. VOID
  295. )
  296. {
  297. return ReadLocalApicReg (XAPIC_VERSION_OFFSET);
  298. }
  299. /**
  300. Send a Fixed IPI to a specified target processor.
  301. This function returns after the IPI has been accepted by the target processor.
  302. @param ApicId The local APIC ID of the target processor.
  303. @param Vector The vector number of the interrupt being sent.
  304. **/
  305. VOID
  306. EFIAPI
  307. SendFixedIpi (
  308. IN UINT32 ApicId,
  309. IN UINT8 Vector
  310. )
  311. {
  312. LOCAL_APIC_ICR_LOW IcrLow;
  313. IcrLow.Uint32 = 0;
  314. IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
  315. IcrLow.Bits.Level = 1;
  316. IcrLow.Bits.Vector = Vector;
  317. SendIpi (IcrLow.Uint32, ApicId);
  318. }
  319. /**
  320. Send a Fixed IPI to all processors excluding self.
  321. This function returns after the IPI has been accepted by the target processors.
  322. @param Vector The vector number of the interrupt being sent.
  323. **/
  324. VOID
  325. EFIAPI
  326. SendFixedIpiAllExcludingSelf (
  327. IN UINT8 Vector
  328. )
  329. {
  330. LOCAL_APIC_ICR_LOW IcrLow;
  331. IcrLow.Uint32 = 0;
  332. IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
  333. IcrLow.Bits.Level = 1;
  334. IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
  335. IcrLow.Bits.Vector = Vector;
  336. SendIpi (IcrLow.Uint32, 0);
  337. }
  338. /**
  339. Send a SMI IPI to a specified target processor.
  340. This function returns after the IPI has been accepted by the target processor.
  341. @param ApicId Specify the local APIC ID of the target processor.
  342. **/
  343. VOID
  344. EFIAPI
  345. SendSmiIpi (
  346. IN UINT32 ApicId
  347. )
  348. {
  349. LOCAL_APIC_ICR_LOW IcrLow;
  350. IcrLow.Uint32 = 0;
  351. IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
  352. IcrLow.Bits.Level = 1;
  353. SendIpi (IcrLow.Uint32, ApicId);
  354. }
  355. /**
  356. Send a SMI IPI to all processors excluding self.
  357. This function returns after the IPI has been accepted by the target processors.
  358. **/
  359. VOID
  360. EFIAPI
  361. SendSmiIpiAllExcludingSelf (
  362. VOID
  363. )
  364. {
  365. LOCAL_APIC_ICR_LOW IcrLow;
  366. IcrLow.Uint32 = 0;
  367. IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
  368. IcrLow.Bits.Level = 1;
  369. IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
  370. SendIpi (IcrLow.Uint32, 0);
  371. }
  372. /**
  373. Send an INIT IPI to a specified target processor.
  374. This function returns after the IPI has been accepted by the target processor.
  375. @param ApicId Specify the local APIC ID of the target processor.
  376. **/
  377. VOID
  378. EFIAPI
  379. SendInitIpi (
  380. IN UINT32 ApicId
  381. )
  382. {
  383. LOCAL_APIC_ICR_LOW IcrLow;
  384. IcrLow.Uint32 = 0;
  385. IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
  386. IcrLow.Bits.Level = 1;
  387. SendIpi (IcrLow.Uint32, ApicId);
  388. }
  389. /**
  390. Send an INIT IPI to all processors excluding self.
  391. This function returns after the IPI has been accepted by the target processors.
  392. **/
  393. VOID
  394. EFIAPI
  395. SendInitIpiAllExcludingSelf (
  396. VOID
  397. )
  398. {
  399. LOCAL_APIC_ICR_LOW IcrLow;
  400. IcrLow.Uint32 = 0;
  401. IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
  402. IcrLow.Bits.Level = 1;
  403. IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
  404. SendIpi (IcrLow.Uint32, 0);
  405. }
  406. /**
  407. Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
  408. This function returns after the IPI has been accepted by the target processor.
  409. if StartupRoutine >= 1M, then ASSERT.
  410. if StartupRoutine is not multiple of 4K, then ASSERT.
  411. @param ApicId Specify the local APIC ID of the target processor.
  412. @param StartupRoutine Points to a start-up routine which is below 1M physical
  413. address and 4K aligned.
  414. **/
  415. VOID
  416. EFIAPI
  417. SendInitSipiSipi (
  418. IN UINT32 ApicId,
  419. IN UINT32 StartupRoutine
  420. )
  421. {
  422. LOCAL_APIC_ICR_LOW IcrLow;
  423. ASSERT (StartupRoutine < 0x100000);
  424. ASSERT ((StartupRoutine & 0xfff) == 0);
  425. SendInitIpi (ApicId);
  426. MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
  427. IcrLow.Uint32 = 0;
  428. IcrLow.Bits.Vector = (StartupRoutine >> 12);
  429. IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
  430. IcrLow.Bits.Level = 1;
  431. SendIpi (IcrLow.Uint32, ApicId);
  432. if (!StandardSignatureIsAuthenticAMD ()) {
  433. MicroSecondDelay (200);
  434. SendIpi (IcrLow.Uint32, ApicId);
  435. }
  436. }
  437. /**
  438. Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
  439. This function returns after the IPI has been accepted by the target processors.
  440. if StartupRoutine >= 1M, then ASSERT.
  441. if StartupRoutine is not multiple of 4K, then ASSERT.
  442. @param StartupRoutine Points to a start-up routine which is below 1M physical
  443. address and 4K aligned.
  444. **/
  445. VOID
  446. EFIAPI
  447. SendInitSipiSipiAllExcludingSelf (
  448. IN UINT32 StartupRoutine
  449. )
  450. {
  451. LOCAL_APIC_ICR_LOW IcrLow;
  452. ASSERT (StartupRoutine < 0x100000);
  453. ASSERT ((StartupRoutine & 0xfff) == 0);
  454. SendInitIpiAllExcludingSelf ();
  455. MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
  456. IcrLow.Uint32 = 0;
  457. IcrLow.Bits.Vector = (StartupRoutine >> 12);
  458. IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
  459. IcrLow.Bits.Level = 1;
  460. IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
  461. SendIpi (IcrLow.Uint32, 0);
  462. if (!StandardSignatureIsAuthenticAMD ()) {
  463. MicroSecondDelay (200);
  464. SendIpi (IcrLow.Uint32, 0);
  465. }
  466. }
  467. /**
  468. Initialize the state of the SoftwareEnable bit in the Local APIC
  469. Spurious Interrupt Vector register.
  470. @param Enable If TRUE, then set SoftwareEnable to 1
  471. If FALSE, then set SoftwareEnable to 0.
  472. **/
  473. VOID
  474. EFIAPI
  475. InitializeLocalApicSoftwareEnable (
  476. IN BOOLEAN Enable
  477. )
  478. {
  479. LOCAL_APIC_SVR Svr;
  480. //
  481. // Set local APIC software-enabled bit.
  482. //
  483. Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
  484. if (Enable) {
  485. if (Svr.Bits.SoftwareEnable == 0) {
  486. Svr.Bits.SoftwareEnable = 1;
  487. WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
  488. }
  489. } else {
  490. if (Svr.Bits.SoftwareEnable == 1) {
  491. Svr.Bits.SoftwareEnable = 0;
  492. WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
  493. }
  494. }
  495. }
  496. /**
  497. Programming Virtual Wire Mode.
  498. This function programs the local APIC for virtual wire mode following
  499. the example described in chapter A.3 of the MP 1.4 spec.
  500. IOxAPIC is not involved in this type of virtual wire mode.
  501. **/
  502. VOID
  503. EFIAPI
  504. ProgramVirtualWireMode (
  505. VOID
  506. )
  507. {
  508. LOCAL_APIC_SVR Svr;
  509. LOCAL_APIC_LVT_LINT Lint;
  510. //
  511. // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
  512. //
  513. Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
  514. Svr.Bits.SpuriousVector = 0xf;
  515. Svr.Bits.SoftwareEnable = 1;
  516. WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
  517. //
  518. // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
  519. //
  520. Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
  521. Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
  522. Lint.Bits.InputPinPolarity = 0;
  523. Lint.Bits.TriggerMode = 0;
  524. Lint.Bits.Mask = 0;
  525. WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
  526. //
  527. // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
  528. //
  529. Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
  530. Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
  531. Lint.Bits.InputPinPolarity = 0;
  532. Lint.Bits.TriggerMode = 0;
  533. Lint.Bits.Mask = 0;
  534. WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
  535. }
  536. /**
  537. Disable LINT0 & LINT1 interrupts.
  538. This function sets the mask flag in the LVT LINT0 & LINT1 registers.
  539. **/
  540. VOID
  541. EFIAPI
  542. DisableLvtInterrupts (
  543. VOID
  544. )
  545. {
  546. LOCAL_APIC_LVT_LINT LvtLint;
  547. LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
  548. LvtLint.Bits.Mask = 1;
  549. WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
  550. LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
  551. LvtLint.Bits.Mask = 1;
  552. WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
  553. }
  554. /**
  555. Read the initial count value from the init-count register.
  556. @return The initial count value read from the init-count register.
  557. **/
  558. UINT32
  559. EFIAPI
  560. GetApicTimerInitCount (
  561. VOID
  562. )
  563. {
  564. return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);
  565. }
  566. /**
  567. Read the current count value from the current-count register.
  568. @return The current count value read from the current-count register.
  569. **/
  570. UINT32
  571. EFIAPI
  572. GetApicTimerCurrentCount (
  573. VOID
  574. )
  575. {
  576. return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);
  577. }
  578. /**
  579. Initialize the local APIC timer.
  580. The local APIC timer is initialized and enabled.
  581. @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
  582. If it is 0, then use the current divide value in the DCR.
  583. @param InitCount The initial count value.
  584. @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
  585. @param Vector The timer interrupt vector number.
  586. **/
  587. VOID
  588. EFIAPI
  589. InitializeApicTimer (
  590. IN UINTN DivideValue,
  591. IN UINT32 InitCount,
  592. IN BOOLEAN PeriodicMode,
  593. IN UINT8 Vector
  594. )
  595. {
  596. LOCAL_APIC_DCR Dcr;
  597. LOCAL_APIC_LVT_TIMER LvtTimer;
  598. UINT32 Divisor;
  599. //
  600. // Ensure local APIC is in software-enabled state.
  601. //
  602. InitializeLocalApicSoftwareEnable (TRUE);
  603. //
  604. // Program init-count register.
  605. //
  606. WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);
  607. if (DivideValue != 0) {
  608. ASSERT (DivideValue <= 128);
  609. ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue));
  610. Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
  611. Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
  612. Dcr.Bits.DivideValue1 = (Divisor & 0x3);
  613. Dcr.Bits.DivideValue2 = (Divisor >> 2);
  614. WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
  615. }
  616. //
  617. // Enable APIC timer interrupt with specified timer mode.
  618. //
  619. LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
  620. if (PeriodicMode) {
  621. LvtTimer.Bits.TimerMode = 1;
  622. } else {
  623. LvtTimer.Bits.TimerMode = 0;
  624. }
  625. LvtTimer.Bits.Mask = 0;
  626. LvtTimer.Bits.Vector = Vector;
  627. WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
  628. }
  629. /**
  630. Get the state of the local APIC timer.
  631. This function will ASSERT if the local APIC is not software enabled.
  632. @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
  633. @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
  634. @param Vector Return the timer interrupt vector number.
  635. **/
  636. VOID
  637. EFIAPI
  638. GetApicTimerState (
  639. OUT UINTN *DivideValue OPTIONAL,
  640. OUT BOOLEAN *PeriodicMode OPTIONAL,
  641. OUT UINT8 *Vector OPTIONAL
  642. )
  643. {
  644. UINT32 Divisor;
  645. LOCAL_APIC_DCR Dcr;
  646. LOCAL_APIC_LVT_TIMER LvtTimer;
  647. //
  648. // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
  649. // Vector Register.
  650. // This bit will be 1, if local APIC is software enabled.
  651. //
  652. ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
  653. if (DivideValue != NULL) {
  654. Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
  655. Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
  656. Divisor = (Divisor + 1) & 0x7;
  657. *DivideValue = ((UINTN)1) << Divisor;
  658. }
  659. if ((PeriodicMode != NULL) || (Vector != NULL)) {
  660. LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
  661. if (PeriodicMode != NULL) {
  662. if (LvtTimer.Bits.TimerMode == 1) {
  663. *PeriodicMode = TRUE;
  664. } else {
  665. *PeriodicMode = FALSE;
  666. }
  667. }
  668. if (Vector != NULL) {
  669. *Vector = (UINT8)LvtTimer.Bits.Vector;
  670. }
  671. }
  672. }
  673. /**
  674. Enable the local APIC timer interrupt.
  675. **/
  676. VOID
  677. EFIAPI
  678. EnableApicTimerInterrupt (
  679. VOID
  680. )
  681. {
  682. LOCAL_APIC_LVT_TIMER LvtTimer;
  683. LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
  684. LvtTimer.Bits.Mask = 0;
  685. WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
  686. }
  687. /**
  688. Disable the local APIC timer interrupt.
  689. **/
  690. VOID
  691. EFIAPI
  692. DisableApicTimerInterrupt (
  693. VOID
  694. )
  695. {
  696. LOCAL_APIC_LVT_TIMER LvtTimer;
  697. LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
  698. LvtTimer.Bits.Mask = 1;
  699. WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
  700. }
  701. /**
  702. Get the local APIC timer interrupt state.
  703. @retval TRUE The local APIC timer interrupt is enabled.
  704. @retval FALSE The local APIC timer interrupt is disabled.
  705. **/
  706. BOOLEAN
  707. EFIAPI
  708. GetApicTimerInterruptState (
  709. VOID
  710. )
  711. {
  712. LOCAL_APIC_LVT_TIMER LvtTimer;
  713. LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
  714. return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
  715. }
  716. /**
  717. Send EOI to the local APIC.
  718. **/
  719. VOID
  720. EFIAPI
  721. SendApicEoi (
  722. VOID
  723. )
  724. {
  725. WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);
  726. }
  727. /**
  728. Get the 32-bit address that a device should use to send a Message Signaled
  729. Interrupt (MSI) to the Local APIC of the currently executing processor.
  730. @return 32-bit address used to send an MSI to the Local APIC.
  731. **/
  732. UINT32
  733. EFIAPI
  734. GetApicMsiAddress (
  735. VOID
  736. )
  737. {
  738. LOCAL_APIC_MSI_ADDRESS MsiAddress;
  739. //
  740. // Return address for an MSI interrupt to be delivered only to the APIC ID
  741. // of the currently executing processor.
  742. //
  743. MsiAddress.Uint32 = 0;
  744. MsiAddress.Bits.BaseAddress = 0xFEE;
  745. MsiAddress.Bits.DestinationId = GetApicId ();
  746. return MsiAddress.Uint32;
  747. }
  748. /**
  749. Get the 64-bit data value that a device should use to send a Message Signaled
  750. Interrupt (MSI) to the Local APIC of the currently executing processor.
  751. If Vector is not in range 0x10..0xFE, then ASSERT().
  752. If DeliveryMode is not supported, then ASSERT().
  753. @param Vector The 8-bit interrupt vector associated with the MSI.
  754. Must be in the range 0x10..0xFE
  755. @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
  756. is handled. The only supported values are:
  757. 0: LOCAL_APIC_DELIVERY_MODE_FIXED
  758. 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
  759. 2: LOCAL_APIC_DELIVERY_MODE_SMI
  760. 4: LOCAL_APIC_DELIVERY_MODE_NMI
  761. 5: LOCAL_APIC_DELIVERY_MODE_INIT
  762. 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
  763. @param LevelTriggered TRUE specifies a level triggered interrupt.
  764. FALSE specifies an edge triggered interrupt.
  765. @param AssertionLevel Ignored if LevelTriggered is FALSE.
  766. TRUE specifies a level triggered interrupt that active
  767. when the interrupt line is asserted.
  768. FALSE specifies a level triggered interrupt that active
  769. when the interrupt line is deasserted.
  770. @return 64-bit data value used to send an MSI to the Local APIC.
  771. **/
  772. UINT64
  773. EFIAPI
  774. GetApicMsiValue (
  775. IN UINT8 Vector,
  776. IN UINTN DeliveryMode,
  777. IN BOOLEAN LevelTriggered,
  778. IN BOOLEAN AssertionLevel
  779. )
  780. {
  781. LOCAL_APIC_MSI_DATA MsiData;
  782. ASSERT (Vector >= 0x10 && Vector <= 0xFE);
  783. ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
  784. MsiData.Uint64 = 0;
  785. MsiData.Bits.Vector = Vector;
  786. MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;
  787. if (LevelTriggered) {
  788. MsiData.Bits.TriggerMode = 1;
  789. if (AssertionLevel) {
  790. MsiData.Bits.Level = 1;
  791. }
  792. }
  793. return MsiData.Uint64;
  794. }
  795. /**
  796. Get Package ID/Core ID/Thread ID of a processor.
  797. The algorithm assumes the target system has symmetry across physical
  798. package boundaries with respect to the number of logical processors
  799. per package, number of cores per package.
  800. @param[in] InitialApicId Initial APIC ID of the target logical processor.
  801. @param[out] Package Returns the processor package ID.
  802. @param[out] Core Returns the processor core ID.
  803. @param[out] Thread Returns the processor thread ID.
  804. **/
  805. VOID
  806. EFIAPI
  807. GetProcessorLocationByApicId (
  808. IN UINT32 InitialApicId,
  809. OUT UINT32 *Package OPTIONAL,
  810. OUT UINT32 *Core OPTIONAL,
  811. OUT UINT32 *Thread OPTIONAL
  812. )
  813. {
  814. BOOLEAN TopologyLeafSupported;
  815. CPUID_VERSION_INFO_EBX VersionInfoEbx;
  816. CPUID_VERSION_INFO_EDX VersionInfoEdx;
  817. CPUID_CACHE_PARAMS_EAX CacheParamsEax;
  818. CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
  819. CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
  820. CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
  821. CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
  822. CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
  823. CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
  824. UINT32 MaxStandardCpuIdIndex;
  825. UINT32 MaxExtendedCpuIdIndex;
  826. UINT32 SubIndex;
  827. UINTN LevelType;
  828. UINT32 MaxLogicProcessorsPerPackage;
  829. UINT32 MaxCoresPerPackage;
  830. UINTN ThreadBits;
  831. UINTN CoreBits;
  832. //
  833. // Check if the processor is capable of supporting more than one logical processor.
  834. //
  835. AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
  836. if (VersionInfoEdx.Bits.HTT == 0) {
  837. if (Thread != NULL) {
  838. *Thread = 0;
  839. }
  840. if (Core != NULL) {
  841. *Core = 0;
  842. }
  843. if (Package != NULL) {
  844. *Package = 0;
  845. }
  846. return;
  847. }
  848. //
  849. // Assume three-level mapping of APIC ID: Package|Core|Thread.
  850. //
  851. ThreadBits = 0;
  852. CoreBits = 0;
  853. //
  854. // Get max index of CPUID
  855. //
  856. AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
  857. AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
  858. //
  859. // If the extended topology enumeration leaf is available, it
  860. // is the preferred mechanism for enumerating topology.
  861. //
  862. TopologyLeafSupported = FALSE;
  863. if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
  864. AsmCpuidEx (
  865. CPUID_EXTENDED_TOPOLOGY,
  866. 0,
  867. &ExtendedTopologyEax.Uint32,
  868. &ExtendedTopologyEbx.Uint32,
  869. &ExtendedTopologyEcx.Uint32,
  870. NULL
  871. );
  872. //
  873. // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
  874. // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
  875. // supported on that processor.
  876. //
  877. if (ExtendedTopologyEbx.Uint32 != 0) {
  878. TopologyLeafSupported = TRUE;
  879. //
  880. // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
  881. // the SMT sub-field of x2APIC ID.
  882. //
  883. LevelType = ExtendedTopologyEcx.Bits.LevelType;
  884. ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
  885. ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
  886. //
  887. // Software must not assume any "level type" encoding
  888. // value to be related to any sub-leaf index, except sub-leaf 0.
  889. //
  890. SubIndex = 1;
  891. do {
  892. AsmCpuidEx (
  893. CPUID_EXTENDED_TOPOLOGY,
  894. SubIndex,
  895. &ExtendedTopologyEax.Uint32,
  896. NULL,
  897. &ExtendedTopologyEcx.Uint32,
  898. NULL
  899. );
  900. LevelType = ExtendedTopologyEcx.Bits.LevelType;
  901. if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
  902. CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
  903. break;
  904. }
  905. SubIndex++;
  906. } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
  907. }
  908. }
  909. if (!TopologyLeafSupported) {
  910. //
  911. // Get logical processor count
  912. //
  913. AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
  914. MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
  915. //
  916. // Assume single-core processor
  917. //
  918. MaxCoresPerPackage = 1;
  919. //
  920. // Check for topology extensions on AMD processor
  921. //
  922. if (StandardSignatureIsAuthenticAMD ()) {
  923. if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
  924. AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
  925. if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
  926. //
  927. // Account for max possible thread count to decode ApicId
  928. //
  929. AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
  930. MaxLogicProcessorsPerPackage = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
  931. //
  932. // Get cores per processor package
  933. //
  934. AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);
  935. MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
  936. }
  937. }
  938. } else {
  939. //
  940. // Extract core count based on CACHE information
  941. //
  942. if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
  943. AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
  944. if (CacheParamsEax.Uint32 != 0) {
  945. MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
  946. }
  947. }
  948. }
  949. ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
  950. CoreBits = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1);
  951. }
  952. if (Thread != NULL) {
  953. *Thread = InitialApicId & ((1 << ThreadBits) - 1);
  954. }
  955. if (Core != NULL) {
  956. *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
  957. }
  958. if (Package != NULL) {
  959. *Package = (InitialApicId >> (ThreadBits + CoreBits));
  960. }
  961. }
  962. /**
  963. Get Package ID/Die ID/Tile ID/Module ID/Core ID/Thread ID of a processor.
  964. The algorithm assumes the target system has symmetry across physical
  965. package boundaries with respect to the number of threads per core, number of
  966. cores per module, number of modules per tile, number of tiles per die, number
  967. of dies per package.
  968. @param[in] InitialApicId Initial APIC ID of the target logical processor.
  969. @param[out] Package Returns the processor package ID.
  970. @param[out] Die Returns the processor die ID.
  971. @param[out] Tile Returns the processor tile ID.
  972. @param[out] Module Returns the processor module ID.
  973. @param[out] Core Returns the processor core ID.
  974. @param[out] Thread Returns the processor thread ID.
  975. **/
  976. VOID
  977. EFIAPI
  978. GetProcessorLocation2ByApicId (
  979. IN UINT32 InitialApicId,
  980. OUT UINT32 *Package OPTIONAL,
  981. OUT UINT32 *Die OPTIONAL,
  982. OUT UINT32 *Tile OPTIONAL,
  983. OUT UINT32 *Module OPTIONAL,
  984. OUT UINT32 *Core OPTIONAL,
  985. OUT UINT32 *Thread OPTIONAL
  986. )
  987. {
  988. CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
  989. CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
  990. UINT32 MaxStandardCpuIdIndex;
  991. UINT32 Index;
  992. UINTN LevelType;
  993. UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
  994. UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
  995. for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {
  996. Bits[LevelType] = 0;
  997. }
  998. //
  999. // Get max index of CPUID
  1000. //
  1001. AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
  1002. if (MaxStandardCpuIdIndex < CPUID_V2_EXTENDED_TOPOLOGY) {
  1003. if (Die != NULL) {
  1004. *Die = 0;
  1005. }
  1006. if (Tile != NULL) {
  1007. *Tile = 0;
  1008. }
  1009. if (Module != NULL) {
  1010. *Module = 0;
  1011. }
  1012. GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);
  1013. return;
  1014. }
  1015. //
  1016. // If the V2 extended topology enumeration leaf is available, it
  1017. // is the preferred mechanism for enumerating topology.
  1018. //
  1019. for (Index = 0; ; Index++) {
  1020. AsmCpuidEx (
  1021. CPUID_V2_EXTENDED_TOPOLOGY,
  1022. Index,
  1023. &ExtendedTopologyEax.Uint32,
  1024. NULL,
  1025. &ExtendedTopologyEcx.Uint32,
  1026. NULL
  1027. );
  1028. LevelType = ExtendedTopologyEcx.Bits.LevelType;
  1029. //
  1030. // first level reported should be SMT.
  1031. //
  1032. ASSERT ((Index != 0) || (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT));
  1033. if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
  1034. break;
  1035. }
  1036. ASSERT (LevelType < ARRAY_SIZE (Bits));
  1037. Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;
  1038. }
  1039. for (LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE; LevelType < ARRAY_SIZE (Bits); LevelType++) {
  1040. //
  1041. // If there are more levels between level-1 (low-level) and level-2 (high-level), the unknown levels will be ignored
  1042. // and treated as an extension of the last known level (i.e., level-1 in this case).
  1043. //
  1044. if (Bits[LevelType] == 0) {
  1045. Bits[LevelType] = Bits[LevelType - 1];
  1046. }
  1047. }
  1048. Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;
  1049. Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE] = Die;
  1050. Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE] = Tile;
  1051. Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE] = Module;
  1052. Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE] = Core;
  1053. Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT] = Thread;
  1054. Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;
  1055. for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
  1056. ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1
  1057. ; LevelType++
  1058. )
  1059. {
  1060. if (Location[LevelType] != NULL) {
  1061. //
  1062. // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique
  1063. // topology ID of the next level type.
  1064. //
  1065. *Location[LevelType] = InitialApicId >> Bits[LevelType - 1];
  1066. //
  1067. // Bits[i] - Bits[i-1] holds the number of bits for the next ONE level type.
  1068. //
  1069. *Location[LevelType] &= (1 << (Bits[LevelType] - Bits[LevelType - 1])) - 1;
  1070. }
  1071. }
  1072. }