CpuIo2Dxe.h 10 KB

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  1. /** @file
  2. Internal include file for the CPU I/O 2 Protocol.
  3. Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef _CPU_IO2_DXE_H_
  7. #define _CPU_IO2_DXE_H_
  8. #include <PiDxe.h>
  9. #include <Protocol/CpuIo2.h>
  10. #include <Library/BaseLib.h>
  11. #include <Library/DebugLib.h>
  12. #include <Library/IoLib.h>
  13. #include <Library/UefiBootServicesTableLib.h>
  14. #define MAX_IO_PORT_ADDRESS 0xFFFF
  15. /**
  16. Reads memory-mapped registers.
  17. The I/O operations are carried out exactly as requested. The caller is responsible
  18. for satisfying any alignment and I/O width restrictions that a PI System on a
  19. platform might require. For example on some platforms, width requests of
  20. EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
  21. be handled by the driver.
  22. If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
  23. or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
  24. each of the Count operations that is performed.
  25. If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
  26. EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
  27. incremented for each of the Count operations that is performed. The read or
  28. write operation is performed Count times on the same Address.
  29. If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
  30. EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
  31. incremented for each of the Count operations that is performed. The read or
  32. write operation is performed Count times from the first element of Buffer.
  33. @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
  34. @param[in] Width Signifies the width of the I/O or Memory operation.
  35. @param[in] Address The base address of the I/O operation.
  36. @param[in] Count The number of I/O operations to perform. The number of
  37. bytes moved is Width size * Count, starting at Address.
  38. @param[out] Buffer For read operations, the destination buffer to store the results.
  39. For write operations, the source buffer from which to write data.
  40. @retval EFI_SUCCESS The data was read from or written to the PI system.
  41. @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
  42. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  43. @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
  44. @retval EFI_UNSUPPORTED The address range specified by Address, Width,
  45. and Count is not valid for this PI system.
  46. **/
  47. EFI_STATUS
  48. EFIAPI
  49. CpuMemoryServiceRead (
  50. IN EFI_CPU_IO2_PROTOCOL *This,
  51. IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
  52. IN UINT64 Address,
  53. IN UINTN Count,
  54. OUT VOID *Buffer
  55. );
  56. /**
  57. Writes memory-mapped registers.
  58. The I/O operations are carried out exactly as requested. The caller is responsible
  59. for satisfying any alignment and I/O width restrictions that a PI System on a
  60. platform might require. For example on some platforms, width requests of
  61. EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
  62. be handled by the driver.
  63. If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
  64. or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
  65. each of the Count operations that is performed.
  66. If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
  67. EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
  68. incremented for each of the Count operations that is performed. The read or
  69. write operation is performed Count times on the same Address.
  70. If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
  71. EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
  72. incremented for each of the Count operations that is performed. The read or
  73. write operation is performed Count times from the first element of Buffer.
  74. @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
  75. @param[in] Width Signifies the width of the I/O or Memory operation.
  76. @param[in] Address The base address of the I/O operation.
  77. @param[in] Count The number of I/O operations to perform. The number of
  78. bytes moved is Width size * Count, starting at Address.
  79. @param[in] Buffer For read operations, the destination buffer to store the results.
  80. For write operations, the source buffer from which to write data.
  81. @retval EFI_SUCCESS The data was read from or written to the PI system.
  82. @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
  83. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  84. @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
  85. @retval EFI_UNSUPPORTED The address range specified by Address, Width,
  86. and Count is not valid for this PI system.
  87. **/
  88. EFI_STATUS
  89. EFIAPI
  90. CpuMemoryServiceWrite (
  91. IN EFI_CPU_IO2_PROTOCOL *This,
  92. IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
  93. IN UINT64 Address,
  94. IN UINTN Count,
  95. IN VOID *Buffer
  96. );
  97. /**
  98. Reads I/O registers.
  99. The I/O operations are carried out exactly as requested. The caller is responsible
  100. for satisfying any alignment and I/O width restrictions that a PI System on a
  101. platform might require. For example on some platforms, width requests of
  102. EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
  103. be handled by the driver.
  104. If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
  105. or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
  106. each of the Count operations that is performed.
  107. If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
  108. EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
  109. incremented for each of the Count operations that is performed. The read or
  110. write operation is performed Count times on the same Address.
  111. If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
  112. EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
  113. incremented for each of the Count operations that is performed. The read or
  114. write operation is performed Count times from the first element of Buffer.
  115. @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
  116. @param[in] Width Signifies the width of the I/O or Memory operation.
  117. @param[in] Address The base address of the I/O operation.
  118. @param[in] Count The number of I/O operations to perform. The number of
  119. bytes moved is Width size * Count, starting at Address.
  120. @param[out] Buffer For read operations, the destination buffer to store the results.
  121. For write operations, the source buffer from which to write data.
  122. @retval EFI_SUCCESS The data was read from or written to the PI system.
  123. @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
  124. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  125. @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
  126. @retval EFI_UNSUPPORTED The address range specified by Address, Width,
  127. and Count is not valid for this PI system.
  128. **/
  129. EFI_STATUS
  130. EFIAPI
  131. CpuIoServiceRead (
  132. IN EFI_CPU_IO2_PROTOCOL *This,
  133. IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
  134. IN UINT64 Address,
  135. IN UINTN Count,
  136. OUT VOID *Buffer
  137. );
  138. /**
  139. Write I/O registers.
  140. The I/O operations are carried out exactly as requested. The caller is responsible
  141. for satisfying any alignment and I/O width restrictions that a PI System on a
  142. platform might require. For example on some platforms, width requests of
  143. EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
  144. be handled by the driver.
  145. If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
  146. or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
  147. each of the Count operations that is performed.
  148. If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
  149. EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
  150. incremented for each of the Count operations that is performed. The read or
  151. write operation is performed Count times on the same Address.
  152. If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
  153. EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
  154. incremented for each of the Count operations that is performed. The read or
  155. write operation is performed Count times from the first element of Buffer.
  156. @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
  157. @param[in] Width Signifies the width of the I/O or Memory operation.
  158. @param[in] Address The base address of the I/O operation.
  159. @param[in] Count The number of I/O operations to perform. The number of
  160. bytes moved is Width size * Count, starting at Address.
  161. @param[in] Buffer For read operations, the destination buffer to store the results.
  162. For write operations, the source buffer from which to write data.
  163. @retval EFI_SUCCESS The data was read from or written to the PI system.
  164. @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
  165. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  166. @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
  167. @retval EFI_UNSUPPORTED The address range specified by Address, Width,
  168. and Count is not valid for this PI system.
  169. **/
  170. EFI_STATUS
  171. EFIAPI
  172. CpuIoServiceWrite (
  173. IN EFI_CPU_IO2_PROTOCOL *This,
  174. IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
  175. IN UINT64 Address,
  176. IN UINTN Count,
  177. IN VOID *Buffer
  178. );
  179. #endif