CpuDxe.c 36 KB

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  1. /** @file
  2. CPU DXE Module to produce CPU ARCH Protocol.
  3. Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "CpuDxe.h"
  7. #include "CpuMp.h"
  8. #include "CpuPageTable.h"
  9. //
  10. // Global Variables
  11. //
  12. BOOLEAN InterruptState = FALSE;
  13. EFI_HANDLE mCpuHandle = NULL;
  14. BOOLEAN mIsFlushingGCD;
  15. BOOLEAN mIsAllocatingPageTable = FALSE;
  16. UINT64 mValidMtrrAddressMask;
  17. UINT64 mValidMtrrBitsMask;
  18. UINT64 mTimerPeriod = 0;
  19. FIXED_MTRR mFixedMtrrTable[] = {
  20. {
  21. MSR_IA32_MTRR_FIX64K_00000,
  22. 0,
  23. 0x10000
  24. },
  25. {
  26. MSR_IA32_MTRR_FIX16K_80000,
  27. 0x80000,
  28. 0x4000
  29. },
  30. {
  31. MSR_IA32_MTRR_FIX16K_A0000,
  32. 0xA0000,
  33. 0x4000
  34. },
  35. {
  36. MSR_IA32_MTRR_FIX4K_C0000,
  37. 0xC0000,
  38. 0x1000
  39. },
  40. {
  41. MSR_IA32_MTRR_FIX4K_C8000,
  42. 0xC8000,
  43. 0x1000
  44. },
  45. {
  46. MSR_IA32_MTRR_FIX4K_D0000,
  47. 0xD0000,
  48. 0x1000
  49. },
  50. {
  51. MSR_IA32_MTRR_FIX4K_D8000,
  52. 0xD8000,
  53. 0x1000
  54. },
  55. {
  56. MSR_IA32_MTRR_FIX4K_E0000,
  57. 0xE0000,
  58. 0x1000
  59. },
  60. {
  61. MSR_IA32_MTRR_FIX4K_E8000,
  62. 0xE8000,
  63. 0x1000
  64. },
  65. {
  66. MSR_IA32_MTRR_FIX4K_F0000,
  67. 0xF0000,
  68. 0x1000
  69. },
  70. {
  71. MSR_IA32_MTRR_FIX4K_F8000,
  72. 0xF8000,
  73. 0x1000
  74. },
  75. };
  76. EFI_CPU_ARCH_PROTOCOL gCpu = {
  77. CpuFlushCpuDataCache,
  78. CpuEnableInterrupt,
  79. CpuDisableInterrupt,
  80. CpuGetInterruptState,
  81. CpuInit,
  82. CpuRegisterInterruptHandler,
  83. CpuGetTimerValue,
  84. CpuSetMemoryAttributes,
  85. 1, // NumberOfTimers
  86. 4 // DmaBufferAlignment
  87. };
  88. //
  89. // CPU Arch Protocol Functions
  90. //
  91. /**
  92. Flush CPU data cache. If the instruction cache is fully coherent
  93. with all DMA operations then function can just return EFI_SUCCESS.
  94. @param This Protocol instance structure
  95. @param Start Physical address to start flushing from.
  96. @param Length Number of bytes to flush. Round up to chipset
  97. granularity.
  98. @param FlushType Specifies the type of flush operation to perform.
  99. @retval EFI_SUCCESS If cache was flushed
  100. @retval EFI_UNSUPPORTED If flush type is not supported.
  101. @retval EFI_DEVICE_ERROR If requested range could not be flushed.
  102. **/
  103. EFI_STATUS
  104. EFIAPI
  105. CpuFlushCpuDataCache (
  106. IN EFI_CPU_ARCH_PROTOCOL *This,
  107. IN EFI_PHYSICAL_ADDRESS Start,
  108. IN UINT64 Length,
  109. IN EFI_CPU_FLUSH_TYPE FlushType
  110. )
  111. {
  112. if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {
  113. AsmWbinvd ();
  114. return EFI_SUCCESS;
  115. } else if (FlushType == EfiCpuFlushTypeInvalidate) {
  116. AsmInvd ();
  117. return EFI_SUCCESS;
  118. } else {
  119. return EFI_UNSUPPORTED;
  120. }
  121. }
  122. /**
  123. Enables CPU interrupts.
  124. @param This Protocol instance structure
  125. @retval EFI_SUCCESS If interrupts were enabled in the CPU
  126. @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
  127. **/
  128. EFI_STATUS
  129. EFIAPI
  130. CpuEnableInterrupt (
  131. IN EFI_CPU_ARCH_PROTOCOL *This
  132. )
  133. {
  134. EnableInterrupts ();
  135. InterruptState = TRUE;
  136. return EFI_SUCCESS;
  137. }
  138. /**
  139. Disables CPU interrupts.
  140. @param This Protocol instance structure
  141. @retval EFI_SUCCESS If interrupts were disabled in the CPU.
  142. @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
  143. **/
  144. EFI_STATUS
  145. EFIAPI
  146. CpuDisableInterrupt (
  147. IN EFI_CPU_ARCH_PROTOCOL *This
  148. )
  149. {
  150. DisableInterrupts ();
  151. InterruptState = FALSE;
  152. return EFI_SUCCESS;
  153. }
  154. /**
  155. Return the state of interrupts.
  156. @param This Protocol instance structure
  157. @param State Pointer to the CPU's current interrupt state
  158. @retval EFI_SUCCESS If interrupts were disabled in the CPU.
  159. @retval EFI_INVALID_PARAMETER State is NULL.
  160. **/
  161. EFI_STATUS
  162. EFIAPI
  163. CpuGetInterruptState (
  164. IN EFI_CPU_ARCH_PROTOCOL *This,
  165. OUT BOOLEAN *State
  166. )
  167. {
  168. if (State == NULL) {
  169. return EFI_INVALID_PARAMETER;
  170. }
  171. *State = InterruptState;
  172. return EFI_SUCCESS;
  173. }
  174. /**
  175. Generates an INIT to the CPU.
  176. @param This Protocol instance structure
  177. @param InitType Type of CPU INIT to perform
  178. @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
  179. seen.
  180. @retval EFI_DEVICE_ERROR If CPU INIT failed.
  181. @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
  182. **/
  183. EFI_STATUS
  184. EFIAPI
  185. CpuInit (
  186. IN EFI_CPU_ARCH_PROTOCOL *This,
  187. IN EFI_CPU_INIT_TYPE InitType
  188. )
  189. {
  190. return EFI_UNSUPPORTED;
  191. }
  192. /**
  193. Registers a function to be called from the CPU interrupt handler.
  194. @param This Protocol instance structure
  195. @param InterruptType Defines which interrupt to hook. IA-32
  196. valid range is 0x00 through 0xFF
  197. @param InterruptHandler A pointer to a function of type
  198. EFI_CPU_INTERRUPT_HANDLER that is called
  199. when a processor interrupt occurs. A null
  200. pointer is an error condition.
  201. @retval EFI_SUCCESS If handler installed or uninstalled.
  202. @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
  203. for InterruptType was previously installed.
  204. @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
  205. InterruptType was not previously installed.
  206. @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
  207. is not supported.
  208. **/
  209. EFI_STATUS
  210. EFIAPI
  211. CpuRegisterInterruptHandler (
  212. IN EFI_CPU_ARCH_PROTOCOL *This,
  213. IN EFI_EXCEPTION_TYPE InterruptType,
  214. IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
  215. )
  216. {
  217. return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
  218. }
  219. /**
  220. Returns a timer value from one of the CPU's internal timers. There is no
  221. inherent time interval between ticks but is a function of the CPU frequency.
  222. @param This - Protocol instance structure.
  223. @param TimerIndex - Specifies which CPU timer is requested.
  224. @param TimerValue - Pointer to the returned timer value.
  225. @param TimerPeriod - A pointer to the amount of time that passes
  226. in femtoseconds (10-15) for each increment
  227. of TimerValue. If TimerValue does not
  228. increment at a predictable rate, then 0 is
  229. returned. The amount of time that has
  230. passed between two calls to GetTimerValue()
  231. can be calculated with the formula
  232. (TimerValue2 - TimerValue1) * TimerPeriod.
  233. This parameter is optional and may be NULL.
  234. @retval EFI_SUCCESS - If the CPU timer count was returned.
  235. @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
  236. @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
  237. @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
  238. **/
  239. EFI_STATUS
  240. EFIAPI
  241. CpuGetTimerValue (
  242. IN EFI_CPU_ARCH_PROTOCOL *This,
  243. IN UINT32 TimerIndex,
  244. OUT UINT64 *TimerValue,
  245. OUT UINT64 *TimerPeriod OPTIONAL
  246. )
  247. {
  248. UINT64 BeginValue;
  249. UINT64 EndValue;
  250. if (TimerValue == NULL) {
  251. return EFI_INVALID_PARAMETER;
  252. }
  253. if (TimerIndex != 0) {
  254. return EFI_INVALID_PARAMETER;
  255. }
  256. *TimerValue = AsmReadTsc ();
  257. if (TimerPeriod != NULL) {
  258. if (mTimerPeriod == 0) {
  259. //
  260. // Read time stamp counter before and after delay of 100 microseconds
  261. //
  262. BeginValue = AsmReadTsc ();
  263. MicroSecondDelay (100);
  264. EndValue = AsmReadTsc ();
  265. //
  266. // Calculate the actual frequency
  267. //
  268. mTimerPeriod = DivU64x64Remainder (
  269. MultU64x32 (
  270. 1000 * 1000 * 1000,
  271. 100
  272. ),
  273. EndValue - BeginValue,
  274. NULL
  275. );
  276. }
  277. *TimerPeriod = mTimerPeriod;
  278. }
  279. return EFI_SUCCESS;
  280. }
  281. /**
  282. A minimal wrapper function that allows MtrrSetAllMtrrs() to be passed to
  283. EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() as Procedure.
  284. @param[in] Buffer Pointer to an MTRR_SETTINGS object, to be passed to
  285. MtrrSetAllMtrrs().
  286. **/
  287. VOID
  288. EFIAPI
  289. SetMtrrsFromBuffer (
  290. IN VOID *Buffer
  291. )
  292. {
  293. MtrrSetAllMtrrs (Buffer);
  294. }
  295. /**
  296. Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.
  297. This function modifies the attributes for the memory region specified by BaseAddress and
  298. Length from their current attributes to the attributes specified by Attributes.
  299. @param This The EFI_CPU_ARCH_PROTOCOL instance.
  300. @param BaseAddress The physical address that is the start address of a memory region.
  301. @param Length The size in bytes of the memory region.
  302. @param Attributes The bit mask of attributes to set for the memory region.
  303. @retval EFI_SUCCESS The attributes were set for the memory region.
  304. @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
  305. BaseAddress and Length cannot be modified.
  306. @retval EFI_INVALID_PARAMETER Length is zero.
  307. Attributes specified an illegal combination of attributes that
  308. cannot be set together.
  309. @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
  310. the memory resource range.
  311. @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
  312. resource range specified by BaseAddress and Length.
  313. The bit mask of attributes is not support for the memory resource
  314. range specified by BaseAddress and Length.
  315. **/
  316. EFI_STATUS
  317. EFIAPI
  318. CpuSetMemoryAttributes (
  319. IN EFI_CPU_ARCH_PROTOCOL *This,
  320. IN EFI_PHYSICAL_ADDRESS BaseAddress,
  321. IN UINT64 Length,
  322. IN UINT64 Attributes
  323. )
  324. {
  325. RETURN_STATUS Status;
  326. MTRR_MEMORY_CACHE_TYPE CacheType;
  327. EFI_STATUS MpStatus;
  328. EFI_MP_SERVICES_PROTOCOL *MpService;
  329. MTRR_SETTINGS MtrrSettings;
  330. UINT64 CacheAttributes;
  331. UINT64 MemoryAttributes;
  332. MTRR_MEMORY_CACHE_TYPE CurrentCacheType;
  333. //
  334. // If this function is called because GCD SetMemorySpaceAttributes () is called
  335. // by RefreshGcdMemoryAttributes (), then we are just synchronizing GCD memory
  336. // map with MTRR values. So there is no need to modify MTRRs, just return immediately
  337. // to avoid unnecessary computing.
  338. //
  339. if (mIsFlushingGCD) {
  340. DEBUG ((DEBUG_VERBOSE, " Flushing GCD\n"));
  341. return EFI_SUCCESS;
  342. }
  343. //
  344. // During memory attributes updating, new pages may be allocated to setup
  345. // smaller granularity of page table. Page allocation action might then cause
  346. // another calling of CpuSetMemoryAttributes() recursively, due to memory
  347. // protection policy configured (such as PcdDxeNxMemoryProtectionPolicy).
  348. // Since this driver will always protect memory used as page table by itself,
  349. // there's no need to apply protection policy requested from memory service.
  350. // So it's safe to just return EFI_SUCCESS if this time of calling is caused
  351. // by page table memory allocation.
  352. //
  353. if (mIsAllocatingPageTable) {
  354. DEBUG ((DEBUG_VERBOSE, " Allocating page table memory\n"));
  355. return EFI_SUCCESS;
  356. }
  357. CacheAttributes = Attributes & EFI_CACHE_ATTRIBUTE_MASK;
  358. MemoryAttributes = Attributes & EFI_MEMORY_ATTRIBUTE_MASK;
  359. if (Attributes != (CacheAttributes | MemoryAttributes)) {
  360. return EFI_INVALID_PARAMETER;
  361. }
  362. if (CacheAttributes != 0) {
  363. if (!IsMtrrSupported ()) {
  364. return EFI_UNSUPPORTED;
  365. }
  366. switch (CacheAttributes) {
  367. case EFI_MEMORY_UC:
  368. CacheType = CacheUncacheable;
  369. break;
  370. case EFI_MEMORY_WC:
  371. CacheType = CacheWriteCombining;
  372. break;
  373. case EFI_MEMORY_WT:
  374. CacheType = CacheWriteThrough;
  375. break;
  376. case EFI_MEMORY_WP:
  377. CacheType = CacheWriteProtected;
  378. break;
  379. case EFI_MEMORY_WB:
  380. CacheType = CacheWriteBack;
  381. break;
  382. default:
  383. return EFI_INVALID_PARAMETER;
  384. }
  385. CurrentCacheType = MtrrGetMemoryAttribute (BaseAddress);
  386. if (CurrentCacheType != CacheType) {
  387. //
  388. // call MTRR library function
  389. //
  390. Status = MtrrSetMemoryAttribute (
  391. BaseAddress,
  392. Length,
  393. CacheType
  394. );
  395. if (!RETURN_ERROR (Status)) {
  396. MpStatus = gBS->LocateProtocol (
  397. &gEfiMpServiceProtocolGuid,
  398. NULL,
  399. (VOID **)&MpService
  400. );
  401. //
  402. // Synchronize the update with all APs
  403. //
  404. if (!EFI_ERROR (MpStatus)) {
  405. MtrrGetAllMtrrs (&MtrrSettings);
  406. MpStatus = MpService->StartupAllAPs (
  407. MpService, // This
  408. SetMtrrsFromBuffer, // Procedure
  409. FALSE, // SingleThread
  410. NULL, // WaitEvent
  411. 0, // TimeoutInMicrosecsond
  412. &MtrrSettings, // ProcedureArgument
  413. NULL // FailedCpuList
  414. );
  415. ASSERT (MpStatus == EFI_SUCCESS || MpStatus == EFI_NOT_STARTED);
  416. }
  417. }
  418. if (EFI_ERROR (Status)) {
  419. return Status;
  420. }
  421. }
  422. }
  423. //
  424. // Set memory attribute by page table
  425. //
  426. return AssignMemoryPageAttributes (NULL, BaseAddress, Length, MemoryAttributes, NULL);
  427. }
  428. /**
  429. Initializes the valid bits mask and valid address mask for MTRRs.
  430. This function initializes the valid bits mask and valid address mask for MTRRs.
  431. **/
  432. VOID
  433. InitializeMtrrMask (
  434. VOID
  435. )
  436. {
  437. UINT32 RegEax;
  438. UINT8 PhysicalAddressBits;
  439. AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
  440. if (RegEax >= 0x80000008) {
  441. AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
  442. PhysicalAddressBits = (UINT8)RegEax;
  443. } else {
  444. PhysicalAddressBits = 36;
  445. }
  446. mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;
  447. mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;
  448. }
  449. /**
  450. Gets GCD Mem Space type from MTRR Type.
  451. This function gets GCD Mem Space type from MTRR Type.
  452. @param MtrrAttributes MTRR memory type
  453. @return GCD Mem Space type
  454. **/
  455. UINT64
  456. GetMemorySpaceAttributeFromMtrrType (
  457. IN UINT8 MtrrAttributes
  458. )
  459. {
  460. switch (MtrrAttributes) {
  461. case MTRR_CACHE_UNCACHEABLE:
  462. return EFI_MEMORY_UC;
  463. case MTRR_CACHE_WRITE_COMBINING:
  464. return EFI_MEMORY_WC;
  465. case MTRR_CACHE_WRITE_THROUGH:
  466. return EFI_MEMORY_WT;
  467. case MTRR_CACHE_WRITE_PROTECTED:
  468. return EFI_MEMORY_WP;
  469. case MTRR_CACHE_WRITE_BACK:
  470. return EFI_MEMORY_WB;
  471. default:
  472. return 0;
  473. }
  474. }
  475. /**
  476. Searches memory descriptors covered by given memory range.
  477. This function searches into the Gcd Memory Space for descriptors
  478. (from StartIndex to EndIndex) that contains the memory range
  479. specified by BaseAddress and Length.
  480. @param MemorySpaceMap Gcd Memory Space Map as array.
  481. @param NumberOfDescriptors Number of descriptors in map.
  482. @param BaseAddress BaseAddress for the requested range.
  483. @param Length Length for the requested range.
  484. @param StartIndex Start index into the Gcd Memory Space Map.
  485. @param EndIndex End index into the Gcd Memory Space Map.
  486. @retval EFI_SUCCESS Search successfully.
  487. @retval EFI_NOT_FOUND The requested descriptors does not exist.
  488. **/
  489. EFI_STATUS
  490. SearchGcdMemorySpaces (
  491. IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
  492. IN UINTN NumberOfDescriptors,
  493. IN EFI_PHYSICAL_ADDRESS BaseAddress,
  494. IN UINT64 Length,
  495. OUT UINTN *StartIndex,
  496. OUT UINTN *EndIndex
  497. )
  498. {
  499. UINTN Index;
  500. *StartIndex = 0;
  501. *EndIndex = 0;
  502. for (Index = 0; Index < NumberOfDescriptors; Index++) {
  503. if ((BaseAddress >= MemorySpaceMap[Index].BaseAddress) &&
  504. (BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))
  505. {
  506. *StartIndex = Index;
  507. }
  508. if ((BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress) &&
  509. (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))
  510. {
  511. *EndIndex = Index;
  512. return EFI_SUCCESS;
  513. }
  514. }
  515. return EFI_NOT_FOUND;
  516. }
  517. /**
  518. Sets the attributes for a specified range in Gcd Memory Space Map.
  519. This function sets the attributes for a specified range in
  520. Gcd Memory Space Map.
  521. @param MemorySpaceMap Gcd Memory Space Map as array
  522. @param NumberOfDescriptors Number of descriptors in map
  523. @param BaseAddress BaseAddress for the range
  524. @param Length Length for the range
  525. @param Attributes Attributes to set
  526. @retval EFI_SUCCESS Memory attributes set successfully
  527. @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space
  528. **/
  529. EFI_STATUS
  530. SetGcdMemorySpaceAttributes (
  531. IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
  532. IN UINTN NumberOfDescriptors,
  533. IN EFI_PHYSICAL_ADDRESS BaseAddress,
  534. IN UINT64 Length,
  535. IN UINT64 Attributes
  536. )
  537. {
  538. EFI_STATUS Status;
  539. UINTN Index;
  540. UINTN StartIndex;
  541. UINTN EndIndex;
  542. EFI_PHYSICAL_ADDRESS RegionStart;
  543. UINT64 RegionLength;
  544. //
  545. // Get all memory descriptors covered by the memory range
  546. //
  547. Status = SearchGcdMemorySpaces (
  548. MemorySpaceMap,
  549. NumberOfDescriptors,
  550. BaseAddress,
  551. Length,
  552. &StartIndex,
  553. &EndIndex
  554. );
  555. if (EFI_ERROR (Status)) {
  556. return Status;
  557. }
  558. //
  559. // Go through all related descriptors and set attributes accordingly
  560. //
  561. for (Index = StartIndex; Index <= EndIndex; Index++) {
  562. if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
  563. continue;
  564. }
  565. //
  566. // Calculate the start and end address of the overlapping range
  567. //
  568. if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {
  569. RegionStart = BaseAddress;
  570. } else {
  571. RegionStart = MemorySpaceMap[Index].BaseAddress;
  572. }
  573. if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
  574. RegionLength = BaseAddress + Length - RegionStart;
  575. } else {
  576. RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
  577. }
  578. //
  579. // Set memory attributes according to MTRR attribute and the original attribute of descriptor
  580. //
  581. gDS->SetMemorySpaceAttributes (
  582. RegionStart,
  583. RegionLength,
  584. (MemorySpaceMap[Index].Attributes & ~EFI_CACHE_ATTRIBUTE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
  585. );
  586. }
  587. return EFI_SUCCESS;
  588. }
  589. /**
  590. Refreshes the GCD Memory Space attributes according to MTRRs.
  591. This function refreshes the GCD Memory Space attributes according to MTRRs.
  592. **/
  593. VOID
  594. RefreshMemoryAttributesFromMtrr (
  595. VOID
  596. )
  597. {
  598. EFI_STATUS Status;
  599. UINTN Index;
  600. UINTN SubIndex;
  601. UINT64 RegValue;
  602. EFI_PHYSICAL_ADDRESS BaseAddress;
  603. UINT64 Length;
  604. UINT64 Attributes;
  605. UINT64 CurrentAttributes;
  606. UINT8 MtrrType;
  607. UINTN NumberOfDescriptors;
  608. EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
  609. UINT64 DefaultAttributes;
  610. VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
  611. MTRR_FIXED_SETTINGS MtrrFixedSettings;
  612. UINT32 FirmwareVariableMtrrCount;
  613. UINT8 DefaultMemoryType;
  614. FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();
  615. ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);
  616. MemorySpaceMap = NULL;
  617. //
  618. // Initialize the valid bits mask and valid address mask for MTRRs
  619. //
  620. InitializeMtrrMask ();
  621. //
  622. // Get the memory attribute of variable MTRRs
  623. //
  624. MtrrGetMemoryAttributeInVariableMtrr (
  625. mValidMtrrBitsMask,
  626. mValidMtrrAddressMask,
  627. VariableMtrr
  628. );
  629. //
  630. // Get the memory space map from GCD
  631. //
  632. Status = gDS->GetMemorySpaceMap (
  633. &NumberOfDescriptors,
  634. &MemorySpaceMap
  635. );
  636. ASSERT_EFI_ERROR (Status);
  637. DefaultMemoryType = (UINT8)MtrrGetDefaultMemoryType ();
  638. DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (DefaultMemoryType);
  639. //
  640. // Set default attributes to all spaces.
  641. //
  642. for (Index = 0; Index < NumberOfDescriptors; Index++) {
  643. if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
  644. continue;
  645. }
  646. gDS->SetMemorySpaceAttributes (
  647. MemorySpaceMap[Index].BaseAddress,
  648. MemorySpaceMap[Index].Length,
  649. (MemorySpaceMap[Index].Attributes & ~EFI_CACHE_ATTRIBUTE_MASK) |
  650. (MemorySpaceMap[Index].Capabilities & DefaultAttributes)
  651. );
  652. }
  653. //
  654. // Go for variable MTRRs with WB attribute
  655. //
  656. for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
  657. if (VariableMtrr[Index].Valid &&
  658. (VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK))
  659. {
  660. SetGcdMemorySpaceAttributes (
  661. MemorySpaceMap,
  662. NumberOfDescriptors,
  663. VariableMtrr[Index].BaseAddress,
  664. VariableMtrr[Index].Length,
  665. EFI_MEMORY_WB
  666. );
  667. }
  668. }
  669. //
  670. // Go for variable MTRRs with the attribute except for WB and UC attributes
  671. //
  672. for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
  673. if (VariableMtrr[Index].Valid &&
  674. (VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK) &&
  675. (VariableMtrr[Index].Type != MTRR_CACHE_UNCACHEABLE))
  676. {
  677. Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8)VariableMtrr[Index].Type);
  678. SetGcdMemorySpaceAttributes (
  679. MemorySpaceMap,
  680. NumberOfDescriptors,
  681. VariableMtrr[Index].BaseAddress,
  682. VariableMtrr[Index].Length,
  683. Attributes
  684. );
  685. }
  686. }
  687. //
  688. // Go for variable MTRRs with UC attribute
  689. //
  690. for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
  691. if (VariableMtrr[Index].Valid &&
  692. (VariableMtrr[Index].Type == MTRR_CACHE_UNCACHEABLE))
  693. {
  694. SetGcdMemorySpaceAttributes (
  695. MemorySpaceMap,
  696. NumberOfDescriptors,
  697. VariableMtrr[Index].BaseAddress,
  698. VariableMtrr[Index].Length,
  699. EFI_MEMORY_UC
  700. );
  701. }
  702. }
  703. //
  704. // Go for fixed MTRRs
  705. //
  706. Attributes = 0;
  707. BaseAddress = 0;
  708. Length = 0;
  709. MtrrGetFixedMtrr (&MtrrFixedSettings);
  710. for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {
  711. RegValue = MtrrFixedSettings.Mtrr[Index];
  712. //
  713. // Check for continuous fixed MTRR sections
  714. //
  715. for (SubIndex = 0; SubIndex < 8; SubIndex++) {
  716. MtrrType = (UINT8)RShiftU64 (RegValue, SubIndex * 8);
  717. CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType);
  718. if (Length == 0) {
  719. //
  720. // A new MTRR attribute begins
  721. //
  722. Attributes = CurrentAttributes;
  723. } else {
  724. //
  725. // If fixed MTRR attribute changed, then set memory attribute for previous attribute
  726. //
  727. if (CurrentAttributes != Attributes) {
  728. SetGcdMemorySpaceAttributes (
  729. MemorySpaceMap,
  730. NumberOfDescriptors,
  731. BaseAddress,
  732. Length,
  733. Attributes
  734. );
  735. BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex;
  736. Length = 0;
  737. Attributes = CurrentAttributes;
  738. }
  739. }
  740. Length += mFixedMtrrTable[Index].Length;
  741. }
  742. }
  743. //
  744. // Handle the last fixed MTRR region
  745. //
  746. SetGcdMemorySpaceAttributes (
  747. MemorySpaceMap,
  748. NumberOfDescriptors,
  749. BaseAddress,
  750. Length,
  751. Attributes
  752. );
  753. //
  754. // Free memory space map allocated by GCD service GetMemorySpaceMap ()
  755. //
  756. if (MemorySpaceMap != NULL) {
  757. FreePool (MemorySpaceMap);
  758. }
  759. }
  760. /**
  761. Check if paging is enabled or not.
  762. **/
  763. BOOLEAN
  764. IsPagingAndPageAddressExtensionsEnabled (
  765. VOID
  766. )
  767. {
  768. IA32_CR0 Cr0;
  769. IA32_CR4 Cr4;
  770. Cr0.UintN = AsmReadCr0 ();
  771. Cr4.UintN = AsmReadCr4 ();
  772. return ((Cr0.Bits.PG != 0) && (Cr4.Bits.PAE != 0));
  773. }
  774. /**
  775. Refreshes the GCD Memory Space attributes according to MTRRs and Paging.
  776. This function refreshes the GCD Memory Space attributes according to MTRRs
  777. and page tables.
  778. **/
  779. VOID
  780. RefreshGcdMemoryAttributes (
  781. VOID
  782. )
  783. {
  784. mIsFlushingGCD = TRUE;
  785. if (IsMtrrSupported ()) {
  786. RefreshMemoryAttributesFromMtrr ();
  787. }
  788. if (IsPagingAndPageAddressExtensionsEnabled ()) {
  789. RefreshGcdMemoryAttributesFromPaging ();
  790. }
  791. mIsFlushingGCD = FALSE;
  792. }
  793. /**
  794. Initialize Interrupt Descriptor Table for interrupt handling.
  795. **/
  796. VOID
  797. InitInterruptDescriptorTable (
  798. VOID
  799. )
  800. {
  801. EFI_STATUS Status;
  802. EFI_VECTOR_HANDOFF_INFO *VectorInfoList;
  803. EFI_VECTOR_HANDOFF_INFO *VectorInfo;
  804. VectorInfo = NULL;
  805. Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **)&VectorInfoList);
  806. if ((Status == EFI_SUCCESS) && (VectorInfoList != NULL)) {
  807. VectorInfo = VectorInfoList;
  808. }
  809. Status = InitializeCpuInterruptHandlers (VectorInfo);
  810. ASSERT_EFI_ERROR (Status);
  811. }
  812. /**
  813. Callback function for idle events.
  814. @param Event Event whose notification function is being invoked.
  815. @param Context The pointer to the notification function's context,
  816. which is implementation-dependent.
  817. **/
  818. VOID
  819. EFIAPI
  820. IdleLoopEventCallback (
  821. IN EFI_EVENT Event,
  822. IN VOID *Context
  823. )
  824. {
  825. CpuSleep ();
  826. }
  827. /**
  828. Ensure the compatibility of a memory space descriptor with the MMIO aperture.
  829. The memory space descriptor can come from the GCD memory space map, or it can
  830. represent a gap between two neighboring memory space descriptors. In the
  831. latter case, the GcdMemoryType field is expected to be
  832. EfiGcdMemoryTypeNonExistent.
  833. If the memory space descriptor already has type
  834. EfiGcdMemoryTypeMemoryMappedIo, and its capabilities are a superset of the
  835. required capabilities, then no action is taken -- it is by definition
  836. compatible with the aperture.
  837. Otherwise, the intersection of the memory space descriptor is calculated with
  838. the aperture. If the intersection is the empty set (no overlap), no action is
  839. taken; the memory space descriptor is compatible with the aperture.
  840. Otherwise, the type of the descriptor is investigated again. If the type is
  841. EfiGcdMemoryTypeNonExistent (representing a gap, or a genuine descriptor with
  842. such a type), then an attempt is made to add the intersection as MMIO space
  843. to the GCD memory space map, with the specified capabilities. This ensures
  844. continuity for the aperture, and the descriptor is deemed compatible with the
  845. aperture.
  846. Otherwise, the memory space descriptor is incompatible with the MMIO
  847. aperture.
  848. @param[in] Base Base address of the aperture.
  849. @param[in] Length Length of the aperture.
  850. @param[in] Capabilities Capabilities required by the aperture.
  851. @param[in] Descriptor The descriptor to ensure compatibility with the
  852. aperture for.
  853. @retval EFI_SUCCESS The descriptor is compatible. The GCD memory
  854. space map may have been updated, for
  855. continuity within the aperture.
  856. @retval EFI_INVALID_PARAMETER The descriptor is incompatible.
  857. @return Error codes from gDS->AddMemorySpace().
  858. **/
  859. EFI_STATUS
  860. IntersectMemoryDescriptor (
  861. IN UINT64 Base,
  862. IN UINT64 Length,
  863. IN UINT64 Capabilities,
  864. IN CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor
  865. )
  866. {
  867. UINT64 IntersectionBase;
  868. UINT64 IntersectionEnd;
  869. EFI_STATUS Status;
  870. if ((Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) &&
  871. ((Descriptor->Capabilities & Capabilities) == Capabilities))
  872. {
  873. return EFI_SUCCESS;
  874. }
  875. IntersectionBase = MAX (Base, Descriptor->BaseAddress);
  876. IntersectionEnd = MIN (
  877. Base + Length,
  878. Descriptor->BaseAddress + Descriptor->Length
  879. );
  880. if (IntersectionBase >= IntersectionEnd) {
  881. //
  882. // The descriptor and the aperture don't overlap.
  883. //
  884. return EFI_SUCCESS;
  885. }
  886. if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
  887. Status = gDS->AddMemorySpace (
  888. EfiGcdMemoryTypeMemoryMappedIo,
  889. IntersectionBase,
  890. IntersectionEnd - IntersectionBase,
  891. Capabilities
  892. );
  893. DEBUG ((
  894. EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
  895. "%a: %a: add [%Lx, %Lx): %r\n",
  896. gEfiCallerBaseName,
  897. __FUNCTION__,
  898. IntersectionBase,
  899. IntersectionEnd,
  900. Status
  901. ));
  902. return Status;
  903. }
  904. DEBUG ((
  905. DEBUG_ERROR,
  906. "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "
  907. "with aperture [%Lx, %Lx) cap %Lx\n",
  908. gEfiCallerBaseName,
  909. __FUNCTION__,
  910. Descriptor->BaseAddress,
  911. Descriptor->BaseAddress + Descriptor->Length,
  912. (UINT32)Descriptor->GcdMemoryType,
  913. Descriptor->Capabilities,
  914. Base,
  915. Base + Length,
  916. Capabilities
  917. ));
  918. return EFI_INVALID_PARAMETER;
  919. }
  920. /**
  921. Add MMIO space to GCD.
  922. The routine checks the GCD database and only adds those which are
  923. not added in the specified range to GCD.
  924. @param Base Base address of the MMIO space.
  925. @param Length Length of the MMIO space.
  926. @param Capabilities Capabilities of the MMIO space.
  927. @retval EFI_SUCCESS The MMIO space was added successfully.
  928. **/
  929. EFI_STATUS
  930. AddMemoryMappedIoSpace (
  931. IN UINT64 Base,
  932. IN UINT64 Length,
  933. IN UINT64 Capabilities
  934. )
  935. {
  936. EFI_STATUS Status;
  937. UINTN Index;
  938. UINTN NumberOfDescriptors;
  939. EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
  940. Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
  941. if (EFI_ERROR (Status)) {
  942. DEBUG ((
  943. DEBUG_ERROR,
  944. "%a: %a: GetMemorySpaceMap(): %r\n",
  945. gEfiCallerBaseName,
  946. __FUNCTION__,
  947. Status
  948. ));
  949. return Status;
  950. }
  951. for (Index = 0; Index < NumberOfDescriptors; Index++) {
  952. Status = IntersectMemoryDescriptor (
  953. Base,
  954. Length,
  955. Capabilities,
  956. &MemorySpaceMap[Index]
  957. );
  958. if (EFI_ERROR (Status)) {
  959. goto FreeMemorySpaceMap;
  960. }
  961. }
  962. DEBUG_CODE_BEGIN ();
  963. //
  964. // Make sure there are adjacent descriptors covering [Base, Base + Length).
  965. // It is possible that they have not been merged; merging can be prevented
  966. // by allocation and different capabilities.
  967. //
  968. UINT64 CheckBase;
  969. EFI_STATUS CheckStatus;
  970. EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;
  971. for (CheckBase = Base;
  972. CheckBase < Base + Length;
  973. CheckBase = Descriptor.BaseAddress + Descriptor.Length)
  974. {
  975. CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);
  976. ASSERT_EFI_ERROR (CheckStatus);
  977. ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);
  978. ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);
  979. }
  980. DEBUG_CODE_END ();
  981. FreeMemorySpaceMap:
  982. FreePool (MemorySpaceMap);
  983. return Status;
  984. }
  985. /**
  986. Add and allocate CPU local APIC memory mapped space.
  987. @param[in]ImageHandle Image handle this driver.
  988. **/
  989. VOID
  990. AddLocalApicMemorySpace (
  991. IN EFI_HANDLE ImageHandle
  992. )
  993. {
  994. EFI_STATUS Status;
  995. EFI_PHYSICAL_ADDRESS BaseAddress;
  996. BaseAddress = (EFI_PHYSICAL_ADDRESS)GetLocalApicBaseAddress ();
  997. Status = AddMemoryMappedIoSpace (BaseAddress, SIZE_4KB, EFI_MEMORY_UC);
  998. ASSERT_EFI_ERROR (Status);
  999. //
  1000. // Try to allocate APIC memory mapped space, does not check return
  1001. // status because it may be allocated by other driver, or DXE Core if
  1002. // this range is built into Memory Allocation HOB.
  1003. //
  1004. Status = gDS->AllocateMemorySpace (
  1005. EfiGcdAllocateAddress,
  1006. EfiGcdMemoryTypeMemoryMappedIo,
  1007. 0,
  1008. SIZE_4KB,
  1009. &BaseAddress,
  1010. ImageHandle,
  1011. NULL
  1012. );
  1013. if (EFI_ERROR (Status)) {
  1014. DEBUG ((
  1015. DEBUG_INFO,
  1016. "%a: %a: AllocateMemorySpace() Status - %r\n",
  1017. gEfiCallerBaseName,
  1018. __FUNCTION__,
  1019. Status
  1020. ));
  1021. }
  1022. }
  1023. /**
  1024. Initialize the state information for the CPU Architectural Protocol.
  1025. @param ImageHandle Image handle this driver.
  1026. @param SystemTable Pointer to the System Table.
  1027. @retval EFI_SUCCESS Thread can be successfully created
  1028. @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
  1029. @retval EFI_DEVICE_ERROR Cannot create the thread
  1030. **/
  1031. EFI_STATUS
  1032. EFIAPI
  1033. InitializeCpu (
  1034. IN EFI_HANDLE ImageHandle,
  1035. IN EFI_SYSTEM_TABLE *SystemTable
  1036. )
  1037. {
  1038. EFI_STATUS Status;
  1039. EFI_EVENT IdleLoopEvent;
  1040. InitializePageTableLib ();
  1041. InitializeFloatingPointUnits ();
  1042. //
  1043. // Make sure interrupts are disabled
  1044. //
  1045. DisableInterrupts ();
  1046. //
  1047. // Init GDT for DXE
  1048. //
  1049. InitGlobalDescriptorTable ();
  1050. //
  1051. // Setup IDT pointer, IDT and interrupt entry points
  1052. //
  1053. InitInterruptDescriptorTable ();
  1054. //
  1055. // Install CPU Architectural Protocol
  1056. //
  1057. Status = gBS->InstallMultipleProtocolInterfaces (
  1058. &mCpuHandle,
  1059. &gEfiCpuArchProtocolGuid,
  1060. &gCpu,
  1061. NULL
  1062. );
  1063. ASSERT_EFI_ERROR (Status);
  1064. //
  1065. // Refresh GCD memory space map according to MTRR value.
  1066. //
  1067. RefreshGcdMemoryAttributes ();
  1068. //
  1069. // Add and allocate local APIC memory mapped space
  1070. //
  1071. AddLocalApicMemorySpace (ImageHandle);
  1072. //
  1073. // Setup a callback for idle events
  1074. //
  1075. Status = gBS->CreateEventEx (
  1076. EVT_NOTIFY_SIGNAL,
  1077. TPL_NOTIFY,
  1078. IdleLoopEventCallback,
  1079. NULL,
  1080. &gIdleLoopEventGuid,
  1081. &IdleLoopEvent
  1082. );
  1083. ASSERT_EFI_ERROR (Status);
  1084. InitializeMpSupport ();
  1085. return Status;
  1086. }