Cpuid.c 69 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719
  1. /** @file
  2. UEFI Application to display CPUID leaf information.
  3. Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <Uefi.h>
  7. #include <Library/BaseLib.h>
  8. #include <Library/UefiLib.h>
  9. #include <Register/Intel/Cpuid.h>
  10. ///
  11. /// Macro used to display the value of a bit field in a register returned by CPUID.
  12. ///
  13. #define PRINT_BIT_FIELD(Variable, FieldName) \
  14. Print (L"%5a%42a: %x\n", #Variable, #FieldName, Variable.Bits.FieldName);
  15. ///
  16. /// Macro used to display the value of a register returned by CPUID.
  17. ///
  18. #define PRINT_VALUE(Variable, Description) \
  19. Print (L"%5a%42a: %x\n", #Variable, #Description, Variable);
  20. ///
  21. /// Structure for cache description lookup table
  22. ///
  23. typedef struct {
  24. UINT8 CacheDescriptor;
  25. CHAR8 *Type;
  26. CHAR8 *Description;
  27. } CPUID_CACHE_INFO_DESCRIPTION;
  28. ///
  29. /// Cache description lookup table
  30. ///
  31. CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[] = {
  32. { 0x00, "General", "Null descriptor, this byte contains no information" },
  33. { 0x01, "TLB", "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries" },
  34. { 0x02, "TLB", "Instruction TLB: 4 MByte pages, fully associative, 2 entries" },
  35. { 0x03, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 64 entries" },
  36. { 0x04, "TLB", "Data TLB: 4 MByte pages, 4-way set associative, 8 entries" },
  37. { 0x05, "TLB", "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries" },
  38. { 0x06, "Cache", "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size" },
  39. { 0x08, "Cache", "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size" },
  40. { 0x09, "Cache", "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size" },
  41. { 0x0A, "Cache", "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size" },
  42. { 0x0B, "TLB", "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries" },
  43. { 0x0C, "Cache", "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size" },
  44. { 0x0D, "Cache", "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size" },
  45. { 0x0E, "Cache", "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size" },
  46. { 0x1D, "Cache", "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size" },
  47. { 0x21, "Cache", "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size" },
  48. { 0x22, "Cache", "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector" },
  49. { 0x23, "Cache", "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },
  50. { 0x24, "Cache", "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size" },
  51. { 0x25, "Cache", "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },
  52. { 0x29, "Cache", "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },
  53. { 0x2C, "Cache", "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size" },
  54. { 0x30, "Cache", "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size" },
  55. { 0x40, "Cache", "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" },
  56. { 0x41, "Cache", "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size" },
  57. { 0x42, "Cache", "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size" },
  58. { 0x43, "Cache", "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size" },
  59. { 0x44, "Cache", "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size" },
  60. { 0x45, "Cache", "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size" },
  61. { 0x46, "Cache", "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size" },
  62. { 0x47, "Cache", "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size" },
  63. { 0x48, "Cache", "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size" },
  64. { 0x49, "Cache", "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H). 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },
  65. { 0x4A, "Cache", "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size" },
  66. { 0x4B, "Cache", "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size" },
  67. { 0x4C, "Cache", "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size" },
  68. { 0x4D, "Cache", "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size" },
  69. { 0x4E, "Cache", "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size" },
  70. { 0x4F, "TLB", "Instruction TLB: 4 KByte pages, 32 entries" },
  71. { 0x50, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries" },
  72. { 0x51, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries" },
  73. { 0x52, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries" },
  74. { 0x55, "TLB", "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries" },
  75. { 0x56, "TLB", "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" },
  76. { 0x57, "TLB", "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" },
  77. { 0x59, "TLB", "Data TLB0: 4 KByte pages, fully associative, 16 entries" },
  78. { 0x5A, "TLB", "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" },
  79. { 0x5B, "TLB", "Data TLB: 4 KByte and 4 MByte pages, 64 entries" },
  80. { 0x5C, "TLB", "Data TLB: 4 KByte and 4 MByte pages,128 entries" },
  81. { 0x5D, "TLB", "Data TLB: 4 KByte and 4 MByte pages,256 entries" },
  82. { 0x60, "Cache", "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" },
  83. { 0x61, "TLB", "Instruction TLB: 4 KByte pages, fully associative, 48 entries" },
  84. { 0x63, "TLB", "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" },
  85. { 0x64, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" },
  86. { 0x66, "Cache", "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" },
  87. { 0x67, "Cache", "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" },
  88. { 0x68, "Cache", "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" },
  89. { 0x6A, "Cache", "uTLB: 4 KByte pages, 8-way set associative, 64 entries" },
  90. { 0x6B, "Cache", "DTLB: 4 KByte pages, 8-way set associative, 256 entries" },
  91. { 0x6C, "Cache", "DTLB: 2M/4M pages, 8-way set associative, 128 entries" },
  92. { 0x6D, "Cache", "DTLB: 1 GByte pages, fully associative, 16 entries" },
  93. { 0x70, "Cache", "Trace cache: 12 K-uop, 8-way set associative" },
  94. { 0x71, "Cache", "Trace cache: 16 K-uop, 8-way set associative" },
  95. { 0x72, "Cache", "Trace cache: 32 K-uop, 8-way set associative" },
  96. { 0x76, "TLB", "Instruction TLB: 2M/4M pages, fully associative, 8 entries" },
  97. { 0x78, "Cache", "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size" },
  98. { 0x79, "Cache", "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
  99. { 0x7A, "Cache", "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
  100. { 0x7B, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
  101. { 0x7C, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
  102. { 0x7D, "Cache", "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size" },
  103. { 0x7F, "Cache", "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size" },
  104. { 0x80, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size" },
  105. { 0x82, "Cache", "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size" },
  106. { 0x83, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size" },
  107. { 0x84, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size" },
  108. { 0x85, "Cache", "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size" },
  109. { 0x86, "Cache", "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },
  110. { 0x87, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },
  111. { 0xA0, "DTLB", "DTLB: 4k pages, fully associative, 32 entries" },
  112. { 0xB0, "TLB", "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries" },
  113. { 0xB1, "TLB", "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" },
  114. { 0xB2, "TLB", "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries" },
  115. { 0xB3, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 128 entries" },
  116. { 0xB4, "TLB", "Data TLB1: 4 KByte pages, 4-way associative, 256 entries" },
  117. { 0xB5, "TLB", "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries" },
  118. { 0xB6, "TLB", "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries" },
  119. { 0xBA, "TLB", "Data TLB1: 4 KByte pages, 4-way associative, 64 entries" },
  120. { 0xC0, "TLB", "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries" },
  121. { 0xC1, "STLB", "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" },
  122. { 0xC2, "DTLB", "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" },
  123. { 0xC3, "STLB", "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." },
  124. { 0xC4, "DTLB", "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" },
  125. { 0xCA, "STLB", "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" },
  126. { 0xD0, "Cache", "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },
  127. { 0xD1, "Cache", "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" },
  128. { 0xD2, "Cache", "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size" },
  129. { 0xD6, "Cache", "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },
  130. { 0xD7, "Cache", "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size" },
  131. { 0xD8, "Cache", "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size" },
  132. { 0xDC, "Cache", "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size" },
  133. { 0xDD, "Cache", "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size" },
  134. { 0xDE, "Cache", "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size" },
  135. { 0xE2, "Cache", "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size" },
  136. { 0xE3, "Cache", "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },
  137. { 0xE4, "Cache", "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size" },
  138. { 0xEA, "Cache", "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size" },
  139. { 0xEB, "Cache", "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size" },
  140. { 0xEC, "Cache", "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size" },
  141. { 0xF0, "Prefetch", "64-Byte prefetching" },
  142. { 0xF1, "Prefetch", "128-Byte prefetching" },
  143. { 0xFE, "General", "CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address translation parameters." },
  144. { 0xFF, "General", "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters" }
  145. };
  146. ///
  147. /// The maximum supported CPUID leaf index starting from leaf 0x00000000.
  148. ///
  149. UINT32 gMaximumBasicFunction = CPUID_SIGNATURE;
  150. ///
  151. /// The maximum supported CPUID leaf index starting from leaf 0x80000000.
  152. ///
  153. UINT32 gMaximumExtendedFunction = CPUID_EXTENDED_FUNCTION;
  154. /**
  155. Display CPUID_SIGNATURE leaf.
  156. **/
  157. VOID
  158. CpuidSignature (
  159. VOID
  160. )
  161. {
  162. UINT32 Eax;
  163. UINT32 Ebx;
  164. UINT32 Ecx;
  165. UINT32 Edx;
  166. CHAR8 Signature[13];
  167. AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
  168. Print (L"CPUID_SIGNATURE (Leaf %08x)\n", CPUID_SIGNATURE);
  169. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx);
  170. PRINT_VALUE (Eax, MaximumLeaf);
  171. *(UINT32 *)(Signature + 0) = Ebx;
  172. *(UINT32 *)(Signature + 4) = Edx;
  173. *(UINT32 *)(Signature + 8) = Ecx;
  174. Signature[12] = 0;
  175. Print (L" Signature = %a\n", Signature);
  176. gMaximumBasicFunction = Eax;
  177. }
  178. /**
  179. Display CPUID_VERSION_INFO leaf.
  180. **/
  181. VOID
  182. CpuidVersionInfo (
  183. VOID
  184. )
  185. {
  186. CPUID_VERSION_INFO_EAX Eax;
  187. CPUID_VERSION_INFO_EBX Ebx;
  188. CPUID_VERSION_INFO_ECX Ecx;
  189. CPUID_VERSION_INFO_EDX Edx;
  190. UINT32 DisplayFamily;
  191. UINT32 DisplayModel;
  192. if (CPUID_VERSION_INFO > gMaximumBasicFunction) {
  193. return;
  194. }
  195. AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
  196. Print (L"CPUID_VERSION_INFO (Leaf %08x)\n", CPUID_VERSION_INFO);
  197. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
  198. DisplayFamily = Eax.Bits.FamilyId;
  199. if (Eax.Bits.FamilyId == 0x0F) {
  200. DisplayFamily |= (Eax.Bits.ExtendedFamilyId << 4);
  201. }
  202. DisplayModel = Eax.Bits.Model;
  203. if ((Eax.Bits.FamilyId == 0x06) || (Eax.Bits.FamilyId == 0x0f)) {
  204. DisplayModel |= (Eax.Bits.ExtendedModelId << 4);
  205. }
  206. Print (L" Family = %x Model = %x Stepping = %x\n", DisplayFamily, DisplayModel, Eax.Bits.SteppingId);
  207. PRINT_BIT_FIELD (Eax, SteppingId);
  208. PRINT_BIT_FIELD (Eax, Model);
  209. PRINT_BIT_FIELD (Eax, FamilyId);
  210. PRINT_BIT_FIELD (Eax, ProcessorType);
  211. PRINT_BIT_FIELD (Eax, ExtendedModelId);
  212. PRINT_BIT_FIELD (Eax, ExtendedFamilyId);
  213. PRINT_BIT_FIELD (Ebx, BrandIndex);
  214. PRINT_BIT_FIELD (Ebx, CacheLineSize);
  215. PRINT_BIT_FIELD (Ebx, MaximumAddressableIdsForLogicalProcessors);
  216. PRINT_BIT_FIELD (Ebx, InitialLocalApicId);
  217. PRINT_BIT_FIELD (Ecx, SSE3);
  218. PRINT_BIT_FIELD (Ecx, PCLMULQDQ);
  219. PRINT_BIT_FIELD (Ecx, DTES64);
  220. PRINT_BIT_FIELD (Ecx, MONITOR);
  221. PRINT_BIT_FIELD (Ecx, DS_CPL);
  222. PRINT_BIT_FIELD (Ecx, VMX);
  223. PRINT_BIT_FIELD (Ecx, SMX);
  224. PRINT_BIT_FIELD (Ecx, TM2);
  225. PRINT_BIT_FIELD (Ecx, SSSE3);
  226. PRINT_BIT_FIELD (Ecx, CNXT_ID);
  227. PRINT_BIT_FIELD (Ecx, SDBG);
  228. PRINT_BIT_FIELD (Ecx, FMA);
  229. PRINT_BIT_FIELD (Ecx, CMPXCHG16B);
  230. PRINT_BIT_FIELD (Ecx, xTPR_Update_Control);
  231. PRINT_BIT_FIELD (Ecx, PDCM);
  232. PRINT_BIT_FIELD (Ecx, PCID);
  233. PRINT_BIT_FIELD (Ecx, DCA);
  234. PRINT_BIT_FIELD (Ecx, SSE4_1);
  235. PRINT_BIT_FIELD (Ecx, SSE4_2);
  236. PRINT_BIT_FIELD (Ecx, x2APIC);
  237. PRINT_BIT_FIELD (Ecx, MOVBE);
  238. PRINT_BIT_FIELD (Ecx, POPCNT);
  239. PRINT_BIT_FIELD (Ecx, TSC_Deadline);
  240. PRINT_BIT_FIELD (Ecx, AESNI);
  241. PRINT_BIT_FIELD (Ecx, XSAVE);
  242. PRINT_BIT_FIELD (Ecx, OSXSAVE);
  243. PRINT_BIT_FIELD (Ecx, AVX);
  244. PRINT_BIT_FIELD (Ecx, F16C);
  245. PRINT_BIT_FIELD (Ecx, RDRAND);
  246. PRINT_BIT_FIELD (Edx, FPU);
  247. PRINT_BIT_FIELD (Edx, VME);
  248. PRINT_BIT_FIELD (Edx, DE);
  249. PRINT_BIT_FIELD (Edx, PSE);
  250. PRINT_BIT_FIELD (Edx, TSC);
  251. PRINT_BIT_FIELD (Edx, MSR);
  252. PRINT_BIT_FIELD (Edx, PAE);
  253. PRINT_BIT_FIELD (Edx, MCE);
  254. PRINT_BIT_FIELD (Edx, CX8);
  255. PRINT_BIT_FIELD (Edx, APIC);
  256. PRINT_BIT_FIELD (Edx, SEP);
  257. PRINT_BIT_FIELD (Edx, MTRR);
  258. PRINT_BIT_FIELD (Edx, PGE);
  259. PRINT_BIT_FIELD (Edx, MCA);
  260. PRINT_BIT_FIELD (Edx, CMOV);
  261. PRINT_BIT_FIELD (Edx, PAT);
  262. PRINT_BIT_FIELD (Edx, PSE_36);
  263. PRINT_BIT_FIELD (Edx, PSN);
  264. PRINT_BIT_FIELD (Edx, CLFSH);
  265. PRINT_BIT_FIELD (Edx, DS);
  266. PRINT_BIT_FIELD (Edx, ACPI);
  267. PRINT_BIT_FIELD (Edx, MMX);
  268. PRINT_BIT_FIELD (Edx, FXSR);
  269. PRINT_BIT_FIELD (Edx, SSE);
  270. PRINT_BIT_FIELD (Edx, SSE2);
  271. PRINT_BIT_FIELD (Edx, SS);
  272. PRINT_BIT_FIELD (Edx, HTT);
  273. PRINT_BIT_FIELD (Edx, TM);
  274. PRINT_BIT_FIELD (Edx, PBE);
  275. }
  276. /**
  277. Lookup a cache description string from the mCpuidCacheInfoDescription table.
  278. @param[in] CacheDescriptor Cache descriptor value from CPUID_CACHE_INFO.
  279. **/
  280. CPUID_CACHE_INFO_DESCRIPTION *
  281. LookupCacheDescription (
  282. UINT8 CacheDescriptor
  283. )
  284. {
  285. UINTN NumDescriptors;
  286. UINTN Descriptor;
  287. if (CacheDescriptor == 0x00) {
  288. return NULL;
  289. }
  290. NumDescriptors = sizeof (mCpuidCacheInfoDescription)/sizeof (mCpuidCacheInfoDescription[0]);
  291. for (Descriptor = 0; Descriptor < NumDescriptors; Descriptor++) {
  292. if (CacheDescriptor == mCpuidCacheInfoDescription[Descriptor].CacheDescriptor) {
  293. return &mCpuidCacheInfoDescription[Descriptor];
  294. }
  295. }
  296. return NULL;
  297. }
  298. /**
  299. Display CPUID_CACHE_INFO leaf for each supported cache descriptor.
  300. **/
  301. VOID
  302. CpuidCacheInfo (
  303. VOID
  304. )
  305. {
  306. CPUID_CACHE_INFO_CACHE_TLB Eax;
  307. CPUID_CACHE_INFO_CACHE_TLB Ebx;
  308. CPUID_CACHE_INFO_CACHE_TLB Ecx;
  309. CPUID_CACHE_INFO_CACHE_TLB Edx;
  310. UINTN Index;
  311. CPUID_CACHE_INFO_DESCRIPTION *CacheDescription;
  312. if (CPUID_CACHE_INFO > gMaximumBasicFunction) {
  313. return;
  314. }
  315. AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
  316. Print (L"CPUID_CACHE_INFO (Leaf %08x)\n", CPUID_CACHE_INFO);
  317. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
  318. if (Eax.Bits.NotValid == 0) {
  319. //
  320. // Process Eax.CacheDescriptor[1..3]. Ignore Eax.CacheDescriptor[0]
  321. //
  322. for (Index = 1; Index < 4; Index++) {
  323. CacheDescription = LookupCacheDescription (Eax.CacheDescriptor[Index]);
  324. if (CacheDescription != NULL) {
  325. Print (
  326. L" %-8a %a\n",
  327. CacheDescription->Type,
  328. CacheDescription->Description
  329. );
  330. }
  331. }
  332. }
  333. if (Ebx.Bits.NotValid == 0) {
  334. //
  335. // Process Ebx.CacheDescriptor[0..3]
  336. //
  337. for (Index = 0; Index < 4; Index++) {
  338. CacheDescription = LookupCacheDescription (Ebx.CacheDescriptor[Index]);
  339. if (CacheDescription != NULL) {
  340. Print (
  341. L" %-8a %a\n",
  342. CacheDescription->Type,
  343. CacheDescription->Description
  344. );
  345. }
  346. }
  347. }
  348. if (Ecx.Bits.NotValid == 0) {
  349. //
  350. // Process Ecx.CacheDescriptor[0..3]
  351. //
  352. for (Index = 0; Index < 4; Index++) {
  353. CacheDescription = LookupCacheDescription (Ecx.CacheDescriptor[Index]);
  354. if (CacheDescription != NULL) {
  355. Print (
  356. L" %-8a %a\n",
  357. CacheDescription->Type,
  358. CacheDescription->Description
  359. );
  360. }
  361. }
  362. }
  363. if (Edx.Bits.NotValid == 0) {
  364. //
  365. // Process Edx.CacheDescriptor[0..3]
  366. //
  367. for (Index = 0; Index < 4; Index++) {
  368. CacheDescription = LookupCacheDescription (Edx.CacheDescriptor[Index]);
  369. if (CacheDescription != NULL) {
  370. Print (
  371. L" %-8a %a\n",
  372. CacheDescription->Type,
  373. CacheDescription->Description
  374. );
  375. }
  376. }
  377. }
  378. }
  379. /**
  380. Display CPUID_SERIAL_NUMBER leaf if it is supported.
  381. **/
  382. VOID
  383. CpuidSerialNumber (
  384. VOID
  385. )
  386. {
  387. CPUID_VERSION_INFO_EDX VersionInfoEdx;
  388. UINT32 Ecx;
  389. UINT32 Edx;
  390. Print (L"CPUID_SERIAL_NUMBER (Leaf %08x)\n", CPUID_SERIAL_NUMBER);
  391. if (CPUID_SERIAL_NUMBER > gMaximumBasicFunction) {
  392. return;
  393. }
  394. AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
  395. if (VersionInfoEdx.Bits.PSN == 0) {
  396. Print (L" Not Supported\n");
  397. return;
  398. }
  399. AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);
  400. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, 0, Ecx, Edx);
  401. Print (L" Processor Serial Number = %08x%08x%08x\n", 0, Edx, Ecx);
  402. }
  403. /**
  404. Display CPUID_CACHE_PARAMS for all supported sub-leafs.
  405. **/
  406. VOID
  407. CpuidCacheParams (
  408. VOID
  409. )
  410. {
  411. UINT32 CacheLevel;
  412. CPUID_CACHE_PARAMS_EAX Eax;
  413. CPUID_CACHE_PARAMS_EBX Ebx;
  414. UINT32 Ecx;
  415. CPUID_CACHE_PARAMS_EDX Edx;
  416. if (CPUID_CACHE_PARAMS > gMaximumBasicFunction) {
  417. return;
  418. }
  419. CacheLevel = 0;
  420. do {
  421. AsmCpuidEx (
  422. CPUID_CACHE_PARAMS,
  423. CacheLevel,
  424. &Eax.Uint32,
  425. &Ebx.Uint32,
  426. &Ecx,
  427. &Edx.Uint32
  428. );
  429. if (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL) {
  430. Print (L"CPUID_CACHE_PARAMS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_CACHE_PARAMS, CacheLevel);
  431. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx, Edx.Uint32);
  432. PRINT_BIT_FIELD (Eax, CacheType);
  433. PRINT_BIT_FIELD (Eax, CacheLevel);
  434. PRINT_BIT_FIELD (Eax, SelfInitializingCache);
  435. PRINT_BIT_FIELD (Eax, FullyAssociativeCache);
  436. PRINT_BIT_FIELD (Eax, MaximumAddressableIdsForLogicalProcessors);
  437. PRINT_BIT_FIELD (Eax, MaximumAddressableIdsForProcessorCores);
  438. PRINT_BIT_FIELD (Ebx, LineSize);
  439. PRINT_BIT_FIELD (Ebx, LinePartitions);
  440. PRINT_BIT_FIELD (Ebx, Ways);
  441. PRINT_VALUE (Ecx, NumberOfSets);
  442. PRINT_BIT_FIELD (Edx, Invalidate);
  443. PRINT_BIT_FIELD (Edx, CacheInclusiveness);
  444. PRINT_BIT_FIELD (Edx, ComplexCacheIndexing);
  445. }
  446. CacheLevel++;
  447. } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
  448. }
  449. /**
  450. Display CPUID_MONITOR_MWAIT leaf.
  451. **/
  452. VOID
  453. CpuidMonitorMwait (
  454. VOID
  455. )
  456. {
  457. CPUID_MONITOR_MWAIT_EAX Eax;
  458. CPUID_MONITOR_MWAIT_EBX Ebx;
  459. CPUID_MONITOR_MWAIT_ECX Ecx;
  460. CPUID_MONITOR_MWAIT_EDX Edx;
  461. if (CPUID_MONITOR_MWAIT > gMaximumBasicFunction) {
  462. return;
  463. }
  464. AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
  465. Print (L"CPUID_MONITOR_MWAIT (Leaf %08x)\n", CPUID_MONITOR_MWAIT);
  466. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
  467. PRINT_BIT_FIELD (Eax, SmallestMonitorLineSize);
  468. PRINT_BIT_FIELD (Ebx, LargestMonitorLineSize);
  469. PRINT_BIT_FIELD (Ecx, ExtensionsSupported);
  470. PRINT_BIT_FIELD (Ecx, InterruptAsBreak);
  471. PRINT_BIT_FIELD (Edx, C0States);
  472. PRINT_BIT_FIELD (Edx, C1States);
  473. PRINT_BIT_FIELD (Edx, C2States);
  474. PRINT_BIT_FIELD (Edx, C3States);
  475. PRINT_BIT_FIELD (Edx, C4States);
  476. PRINT_BIT_FIELD (Edx, C5States);
  477. PRINT_BIT_FIELD (Edx, C6States);
  478. PRINT_BIT_FIELD (Edx, C7States);
  479. }
  480. /**
  481. Display CPUID_THERMAL_POWER_MANAGEMENT leaf.
  482. **/
  483. VOID
  484. CpuidThermalPowerManagement (
  485. VOID
  486. )
  487. {
  488. CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;
  489. CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;
  490. CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;
  491. if (CPUID_THERMAL_POWER_MANAGEMENT > gMaximumBasicFunction) {
  492. return;
  493. }
  494. AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
  495. Print (L"CPUID_THERMAL_POWER_MANAGEMENT (Leaf %08x)\n", CPUID_THERMAL_POWER_MANAGEMENT);
  496. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, 0);
  497. PRINT_BIT_FIELD (Eax, DigitalTemperatureSensor);
  498. PRINT_BIT_FIELD (Eax, TurboBoostTechnology);
  499. PRINT_BIT_FIELD (Eax, ARAT);
  500. PRINT_BIT_FIELD (Eax, PLN);
  501. PRINT_BIT_FIELD (Eax, ECMD);
  502. PRINT_BIT_FIELD (Eax, PTM);
  503. PRINT_BIT_FIELD (Eax, HWP);
  504. PRINT_BIT_FIELD (Eax, HWP_Notification);
  505. PRINT_BIT_FIELD (Eax, HWP_Activity_Window);
  506. PRINT_BIT_FIELD (Eax, HWP_Energy_Performance_Preference);
  507. PRINT_BIT_FIELD (Eax, HWP_Package_Level_Request);
  508. PRINT_BIT_FIELD (Eax, HDC);
  509. PRINT_BIT_FIELD (Eax, TurboBoostMaxTechnology30);
  510. PRINT_BIT_FIELD (Eax, HWPCapabilities);
  511. PRINT_BIT_FIELD (Eax, HWPPECIOverride);
  512. PRINT_BIT_FIELD (Eax, FlexibleHWP);
  513. PRINT_BIT_FIELD (Eax, FastAccessMode);
  514. PRINT_BIT_FIELD (Eax, IgnoringIdleLogicalProcessorHWPRequest);
  515. PRINT_BIT_FIELD (Ebx, InterruptThresholds);
  516. PRINT_BIT_FIELD (Ecx, HardwareCoordinationFeedback);
  517. PRINT_BIT_FIELD (Ecx, PerformanceEnergyBias);
  518. }
  519. /**
  520. Display CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS for all supported sub-leafs.
  521. **/
  522. VOID
  523. CpuidStructuredExtendedFeatureFlags (
  524. VOID
  525. )
  526. {
  527. UINT32 Eax;
  528. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
  529. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;
  530. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX Edx;
  531. UINT32 SubLeaf;
  532. if (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS > gMaximumBasicFunction) {
  533. return;
  534. }
  535. AsmCpuidEx (
  536. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
  537. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
  538. &Eax,
  539. NULL,
  540. NULL,
  541. NULL
  542. );
  543. for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {
  544. AsmCpuidEx (
  545. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
  546. SubLeaf,
  547. NULL,
  548. &Ebx.Uint32,
  549. &Ecx.Uint32,
  550. &Edx.Uint32
  551. );
  552. if ((Ebx.Uint32 != 0) || (Ecx.Uint32 != 0) || (Edx.Uint32 != 0)) {
  553. Print (L"CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, SubLeaf);
  554. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
  555. PRINT_BIT_FIELD (Ebx, FSGSBASE);
  556. PRINT_BIT_FIELD (Ebx, IA32_TSC_ADJUST);
  557. PRINT_BIT_FIELD (Ebx, SGX);
  558. PRINT_BIT_FIELD (Ebx, BMI1);
  559. PRINT_BIT_FIELD (Ebx, HLE);
  560. PRINT_BIT_FIELD (Ebx, AVX2);
  561. PRINT_BIT_FIELD (Ebx, FDP_EXCPTN_ONLY);
  562. PRINT_BIT_FIELD (Ebx, SMEP);
  563. PRINT_BIT_FIELD (Ebx, BMI2);
  564. PRINT_BIT_FIELD (Ebx, EnhancedRepMovsbStosb);
  565. PRINT_BIT_FIELD (Ebx, INVPCID);
  566. PRINT_BIT_FIELD (Ebx, RTM);
  567. PRINT_BIT_FIELD (Ebx, RDT_M);
  568. PRINT_BIT_FIELD (Ebx, DeprecateFpuCsDs);
  569. PRINT_BIT_FIELD (Ebx, MPX);
  570. PRINT_BIT_FIELD (Ebx, RDT_A);
  571. PRINT_BIT_FIELD (Ebx, AVX512F);
  572. PRINT_BIT_FIELD (Ebx, AVX512DQ);
  573. PRINT_BIT_FIELD (Ebx, RDSEED);
  574. PRINT_BIT_FIELD (Ebx, ADX);
  575. PRINT_BIT_FIELD (Ebx, SMAP);
  576. PRINT_BIT_FIELD (Ebx, AVX512_IFMA);
  577. PRINT_BIT_FIELD (Ebx, CLFLUSHOPT);
  578. PRINT_BIT_FIELD (Ebx, CLWB);
  579. PRINT_BIT_FIELD (Ebx, IntelProcessorTrace);
  580. PRINT_BIT_FIELD (Ebx, AVX512PF);
  581. PRINT_BIT_FIELD (Ebx, AVX512ER);
  582. PRINT_BIT_FIELD (Ebx, AVX512CD);
  583. PRINT_BIT_FIELD (Ebx, SHA);
  584. PRINT_BIT_FIELD (Ebx, AVX512BW);
  585. PRINT_BIT_FIELD (Ebx, AVX512VL);
  586. PRINT_BIT_FIELD (Ecx, PREFETCHWT1);
  587. PRINT_BIT_FIELD (Ecx, AVX512_VBMI);
  588. PRINT_BIT_FIELD (Ecx, UMIP);
  589. PRINT_BIT_FIELD (Ecx, PKU);
  590. PRINT_BIT_FIELD (Ecx, OSPKE);
  591. PRINT_BIT_FIELD (Ecx, AVX512_VPOPCNTDQ);
  592. PRINT_BIT_FIELD (Ecx, MAWAU);
  593. PRINT_BIT_FIELD (Ecx, RDPID);
  594. PRINT_BIT_FIELD (Ecx, SGX_LC);
  595. PRINT_BIT_FIELD (Edx, AVX512_4VNNIW);
  596. PRINT_BIT_FIELD (Edx, AVX512_4FMAPS);
  597. PRINT_BIT_FIELD (Edx, EnumeratesSupportForIBRSAndIBPB);
  598. PRINT_BIT_FIELD (Edx, EnumeratesSupportForSTIBP);
  599. PRINT_BIT_FIELD (Edx, EnumeratesSupportForL1D_FLUSH);
  600. PRINT_BIT_FIELD (Edx, EnumeratesSupportForCapability);
  601. PRINT_BIT_FIELD (Edx, EnumeratesSupportForSSBD);
  602. }
  603. }
  604. }
  605. /**
  606. Display CPUID_DIRECT_CACHE_ACCESS_INFO leaf.
  607. **/
  608. VOID
  609. CpuidDirectCacheAccessInfo (
  610. VOID
  611. )
  612. {
  613. UINT32 Eax;
  614. if (CPUID_DIRECT_CACHE_ACCESS_INFO > gMaximumBasicFunction) {
  615. return;
  616. }
  617. AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);
  618. Print (L"CPUID_DIRECT_CACHE_ACCESS_INFO (Leaf %08x)\n", CPUID_DIRECT_CACHE_ACCESS_INFO);
  619. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, 0, 0);
  620. }
  621. /**
  622. Display CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING leaf.
  623. **/
  624. VOID
  625. CpuidArchitecturalPerformanceMonitoring (
  626. VOID
  627. )
  628. {
  629. CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;
  630. CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;
  631. CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;
  632. if (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING > gMaximumBasicFunction) {
  633. return;
  634. }
  635. AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);
  636. Print (L"CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (Leaf %08x)\n", CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING);
  637. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, Edx.Uint32);
  638. PRINT_BIT_FIELD (Eax, ArchPerfMonVerID);
  639. PRINT_BIT_FIELD (Eax, PerformanceMonitorCounters);
  640. PRINT_BIT_FIELD (Eax, PerformanceMonitorCounterWidth);
  641. PRINT_BIT_FIELD (Eax, EbxBitVectorLength);
  642. PRINT_BIT_FIELD (Ebx, UnhaltedCoreCycles);
  643. PRINT_BIT_FIELD (Ebx, InstructionsRetired);
  644. PRINT_BIT_FIELD (Ebx, UnhaltedReferenceCycles);
  645. PRINT_BIT_FIELD (Ebx, LastLevelCacheReferences);
  646. PRINT_BIT_FIELD (Ebx, LastLevelCacheMisses);
  647. PRINT_BIT_FIELD (Ebx, BranchInstructionsRetired);
  648. PRINT_BIT_FIELD (Ebx, AllBranchMispredictRetired);
  649. PRINT_BIT_FIELD (Edx, FixedFunctionPerformanceCounters);
  650. PRINT_BIT_FIELD (Edx, FixedFunctionPerformanceCounterWidth);
  651. PRINT_BIT_FIELD (Edx, AnyThreadDeprecation);
  652. }
  653. /**
  654. Display CPUID_EXTENDED_TOPOLOGY leafs for all supported levels.
  655. @param[in] LeafFunction Leaf function index for CPUID_EXTENDED_TOPOLOGY.
  656. **/
  657. VOID
  658. CpuidExtendedTopology (
  659. UINT32 LeafFunction
  660. )
  661. {
  662. CPUID_EXTENDED_TOPOLOGY_EAX Eax;
  663. CPUID_EXTENDED_TOPOLOGY_EBX Ebx;
  664. CPUID_EXTENDED_TOPOLOGY_ECX Ecx;
  665. UINT32 Edx;
  666. UINT32 LevelNumber;
  667. if (LeafFunction > gMaximumBasicFunction) {
  668. return;
  669. }
  670. if ((LeafFunction != CPUID_EXTENDED_TOPOLOGY) && (LeafFunction != CPUID_V2_EXTENDED_TOPOLOGY)) {
  671. return;
  672. }
  673. LevelNumber = 0;
  674. for (LevelNumber = 0; ; LevelNumber++) {
  675. AsmCpuidEx (
  676. LeafFunction,
  677. LevelNumber,
  678. &Eax.Uint32,
  679. &Ebx.Uint32,
  680. &Ecx.Uint32,
  681. &Edx
  682. );
  683. if (Ecx.Bits.LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
  684. break;
  685. }
  686. Print (
  687. L"%a (Leaf %08x, Sub-Leaf %08x)\n",
  688. LeafFunction == CPUID_EXTENDED_TOPOLOGY ? "CPUID_EXTENDED_TOPOLOGY" : "CPUID_V2_EXTENDED_TOPOLOGY",
  689. LeafFunction,
  690. LevelNumber
  691. );
  692. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx);
  693. PRINT_BIT_FIELD (Eax, ApicIdShift);
  694. PRINT_BIT_FIELD (Ebx, LogicalProcessors);
  695. PRINT_BIT_FIELD (Ecx, LevelNumber);
  696. PRINT_BIT_FIELD (Ecx, LevelType);
  697. PRINT_VALUE (Edx, x2APIC_ID);
  698. }
  699. }
  700. /**
  701. Display CPUID_EXTENDED_STATE sub-leaf.
  702. **/
  703. VOID
  704. CpuidExtendedStateSubLeaf (
  705. VOID
  706. )
  707. {
  708. CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;
  709. UINT32 Ebx;
  710. CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;
  711. UINT32 Edx;
  712. AsmCpuidEx (
  713. CPUID_EXTENDED_STATE,
  714. CPUID_EXTENDED_STATE_SUB_LEAF,
  715. &Eax.Uint32,
  716. &Ebx,
  717. &Ecx.Uint32,
  718. &Edx
  719. );
  720. Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF);
  721. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx);
  722. PRINT_BIT_FIELD (Eax, XSAVEOPT);
  723. PRINT_BIT_FIELD (Eax, XSAVEC);
  724. PRINT_BIT_FIELD (Eax, XGETBV);
  725. PRINT_BIT_FIELD (Eax, XSAVES);
  726. PRINT_VALUE (Ebx, EnabledSaveStateSize_XCR0_IA32_XSS);
  727. PRINT_BIT_FIELD (Ecx, XCR0);
  728. PRINT_BIT_FIELD (Ecx, HWPState);
  729. PRINT_BIT_FIELD (Ecx, PT);
  730. PRINT_BIT_FIELD (Ecx, XCR0_1);
  731. PRINT_VALUE (Edx, IA32_XSS_Supported_32_63);
  732. }
  733. /**
  734. Display CPUID_EXTENDED_STATE size and offset information sub-leaf.
  735. **/
  736. VOID
  737. CpuidExtendedStateSizeOffset (
  738. VOID
  739. )
  740. {
  741. UINT32 Eax;
  742. UINT32 Ebx;
  743. CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;
  744. UINT32 Edx;
  745. UINT32 SubLeaf;
  746. for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {
  747. AsmCpuidEx (
  748. CPUID_EXTENDED_STATE,
  749. SubLeaf,
  750. &Eax,
  751. &Ebx,
  752. &Ecx.Uint32,
  753. &Edx
  754. );
  755. if (Edx != 0) {
  756. Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, SubLeaf);
  757. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx.Uint32, Edx);
  758. PRINT_VALUE (Eax, FeatureSaveStateSize);
  759. PRINT_VALUE (Ebx, FeatureSaveStateOffset);
  760. PRINT_BIT_FIELD (Ecx, XSS);
  761. PRINT_BIT_FIELD (Ecx, Compacted);
  762. }
  763. }
  764. }
  765. /**
  766. Display CPUID_EXTENDED_STATE main leaf and sub-leafs.
  767. **/
  768. VOID
  769. CpuidExtendedStateMainLeaf (
  770. VOID
  771. )
  772. {
  773. CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;
  774. UINT32 Ebx;
  775. UINT32 Ecx;
  776. UINT32 Edx;
  777. if (CPUID_EXTENDED_STATE > gMaximumBasicFunction) {
  778. return;
  779. }
  780. AsmCpuidEx (
  781. CPUID_EXTENDED_STATE,
  782. CPUID_EXTENDED_STATE_MAIN_LEAF,
  783. &Eax.Uint32,
  784. &Ebx,
  785. &Ecx,
  786. &Edx
  787. );
  788. Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF);
  789. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx, Edx);
  790. PRINT_BIT_FIELD (Eax, x87);
  791. PRINT_BIT_FIELD (Eax, SSE);
  792. PRINT_BIT_FIELD (Eax, AVX);
  793. PRINT_BIT_FIELD (Eax, MPX);
  794. PRINT_BIT_FIELD (Eax, AVX_512);
  795. PRINT_BIT_FIELD (Eax, IA32_XSS);
  796. PRINT_BIT_FIELD (Eax, PKRU);
  797. PRINT_BIT_FIELD (Eax, IA32_XSS_2);
  798. PRINT_VALUE (Ebx, EnabledSaveStateSize);
  799. PRINT_VALUE (Ecx, SupportedSaveStateSize);
  800. PRINT_VALUE (Edx, XCR0_Supported_32_63);
  801. CpuidExtendedStateSubLeaf ();
  802. CpuidExtendedStateSizeOffset ();
  803. }
  804. /**
  805. Display CPUID_INTEL_RDT_MONITORING enumeration sub-leaf.
  806. **/
  807. VOID
  808. CpuidIntelRdtMonitoringEnumerationSubLeaf (
  809. VOID
  810. )
  811. {
  812. UINT32 Ebx;
  813. CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
  814. if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {
  815. return;
  816. }
  817. AsmCpuidEx (
  818. CPUID_INTEL_RDT_MONITORING,
  819. CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,
  820. NULL,
  821. &Ebx,
  822. NULL,
  823. &Edx.Uint32
  824. );
  825. Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF);
  826. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, 0, Edx.Uint32);
  827. PRINT_VALUE (Ebx, Maximum_RMID_Range);
  828. PRINT_BIT_FIELD (Edx, L3CacheRDT_M);
  829. }
  830. /**
  831. Display CPUID_INTEL_RDT_MONITORING L3 cache capability sub-leaf.
  832. **/
  833. VOID
  834. CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf (
  835. VOID
  836. )
  837. {
  838. UINT32 Ebx;
  839. UINT32 Ecx;
  840. CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;
  841. if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {
  842. return;
  843. }
  844. AsmCpuidEx (
  845. CPUID_INTEL_RDT_MONITORING,
  846. CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,
  847. NULL,
  848. &Ebx,
  849. &Ecx,
  850. &Edx.Uint32
  851. );
  852. Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF);
  853. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32);
  854. PRINT_VALUE (Ebx, OccupancyConversionFactor);
  855. PRINT_VALUE (Ecx, Maximum_RMID_Range);
  856. PRINT_BIT_FIELD (Edx, L3CacheOccupancyMonitoring);
  857. PRINT_BIT_FIELD (Edx, L3CacheTotalBandwidthMonitoring);
  858. PRINT_BIT_FIELD (Edx, L3CacheLocalBandwidthMonitoring);
  859. }
  860. /**
  861. Display CPUID_INTEL_RDT_ALLOCATION memory bandwidth allocation technology enumeration
  862. sub-leaf.
  863. **/
  864. VOID
  865. CpuidIntelRdtAllocationMemoryBandwidthSubLeaf (
  866. VOID
  867. )
  868. {
  869. CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX Eax;
  870. UINT32 Ebx;
  871. CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX Ecx;
  872. CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx;
  873. AsmCpuidEx (
  874. CPUID_INTEL_RDT_ALLOCATION,
  875. CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,
  876. &Eax.Uint32,
  877. &Ebx,
  878. &Ecx.Uint32,
  879. &Edx.Uint32
  880. );
  881. Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF);
  882. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);
  883. PRINT_BIT_FIELD (Eax, MaximumMBAThrottling);
  884. PRINT_VALUE (Ebx, AllocationUnitBitMap);
  885. PRINT_BIT_FIELD (Ecx, Liner);
  886. PRINT_BIT_FIELD (Edx, HighestCosNumber);
  887. }
  888. /**
  889. Display CPUID_INTEL_RDT_ALLOCATION L3 cache allocation technology enumeration
  890. sub-leaf.
  891. **/
  892. VOID
  893. CpuidIntelRdtAllocationL3CacheSubLeaf (
  894. VOID
  895. )
  896. {
  897. CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;
  898. UINT32 Ebx;
  899. CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;
  900. CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;
  901. AsmCpuidEx (
  902. CPUID_INTEL_RDT_ALLOCATION,
  903. CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,
  904. &Eax.Uint32,
  905. &Ebx,
  906. &Ecx.Uint32,
  907. &Edx.Uint32
  908. );
  909. Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF);
  910. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);
  911. PRINT_BIT_FIELD (Eax, CapacityLength);
  912. PRINT_VALUE (Ebx, AllocationUnitBitMap);
  913. PRINT_BIT_FIELD (Ecx, CodeDataPrioritization);
  914. PRINT_BIT_FIELD (Edx, HighestCosNumber);
  915. }
  916. /**
  917. Display CPUID_INTEL_RDT_ALLOCATION L2 cache allocation technology enumeration
  918. sub-leaf.
  919. **/
  920. VOID
  921. CpuidIntelRdtAllocationL2CacheSubLeaf (
  922. VOID
  923. )
  924. {
  925. CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;
  926. UINT32 Ebx;
  927. CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;
  928. AsmCpuidEx (
  929. CPUID_INTEL_RDT_ALLOCATION,
  930. CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,
  931. &Eax.Uint32,
  932. &Ebx,
  933. NULL,
  934. &Edx.Uint32
  935. );
  936. Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF);
  937. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);
  938. PRINT_BIT_FIELD (Eax, CapacityLength);
  939. PRINT_VALUE (Ebx, AllocationUnitBitMap);
  940. PRINT_BIT_FIELD (Edx, HighestCosNumber);
  941. }
  942. /**
  943. Display CPUID_INTEL_RDT_ALLOCATION main leaf and sub-leaves.
  944. **/
  945. VOID
  946. CpuidIntelRdtAllocationMainLeaf (
  947. VOID
  948. )
  949. {
  950. CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;
  951. if (CPUID_INTEL_RDT_ALLOCATION > gMaximumBasicFunction) {
  952. return;
  953. }
  954. AsmCpuidEx (
  955. CPUID_INTEL_RDT_ALLOCATION,
  956. CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,
  957. NULL,
  958. &Ebx.Uint32,
  959. NULL,
  960. NULL
  961. );
  962. Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF);
  963. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx.Uint32, 0, 0);
  964. PRINT_BIT_FIELD (Ebx, L3CacheAllocation);
  965. PRINT_BIT_FIELD (Ebx, L2CacheAllocation);
  966. PRINT_BIT_FIELD (Ebx, MemoryBandwidth);
  967. CpuidIntelRdtAllocationMemoryBandwidthSubLeaf ();
  968. CpuidIntelRdtAllocationL3CacheSubLeaf ();
  969. CpuidIntelRdtAllocationL2CacheSubLeaf ();
  970. }
  971. /**
  972. Display Sub-Leaf 0 Enumeration of Intel SGX Capabilities.
  973. **/
  974. VOID
  975. CpuidEnumerationOfIntelSgxCapabilities0SubLeaf (
  976. VOID
  977. )
  978. {
  979. CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;
  980. UINT32 Ebx;
  981. CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;
  982. AsmCpuidEx (
  983. CPUID_INTEL_SGX,
  984. CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,
  985. &Eax.Uint32,
  986. &Ebx,
  987. NULL,
  988. &Edx.Uint32
  989. );
  990. Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF);
  991. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);
  992. PRINT_BIT_FIELD (Eax, SGX1);
  993. PRINT_BIT_FIELD (Eax, SGX2);
  994. PRINT_BIT_FIELD (Eax, ENCLV);
  995. PRINT_BIT_FIELD (Eax, ENCLS);
  996. PRINT_BIT_FIELD (Edx, MaxEnclaveSize_Not64);
  997. PRINT_BIT_FIELD (Edx, MaxEnclaveSize_64);
  998. }
  999. /**
  1000. Display Sub-Leaf 1 Enumeration of Intel SGX Capabilities.
  1001. **/
  1002. VOID
  1003. CpuidEnumerationOfIntelSgxCapabilities1SubLeaf (
  1004. VOID
  1005. )
  1006. {
  1007. UINT32 Eax;
  1008. UINT32 Ebx;
  1009. UINT32 Ecx;
  1010. UINT32 Edx;
  1011. AsmCpuidEx (
  1012. CPUID_INTEL_SGX,
  1013. CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,
  1014. &Eax,
  1015. &Ebx,
  1016. &Ecx,
  1017. &Edx
  1018. );
  1019. Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF);
  1020. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx);
  1021. }
  1022. /**
  1023. Display Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.
  1024. **/
  1025. VOID
  1026. CpuidEnumerationOfIntelSgxResourcesSubLeaf (
  1027. VOID
  1028. )
  1029. {
  1030. CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;
  1031. CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;
  1032. CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;
  1033. CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;
  1034. UINT32 SubLeaf;
  1035. SubLeaf = CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF;
  1036. do {
  1037. AsmCpuidEx (
  1038. CPUID_INTEL_SGX,
  1039. SubLeaf,
  1040. &Eax.Uint32,
  1041. &Ebx.Uint32,
  1042. &Ecx.Uint32,
  1043. &Edx.Uint32
  1044. );
  1045. if (Eax.Bits.SubLeafType == 0x1) {
  1046. Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, SubLeaf);
  1047. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
  1048. PRINT_BIT_FIELD (Eax, SubLeafType);
  1049. PRINT_BIT_FIELD (Eax, LowAddressOfEpcSection);
  1050. PRINT_BIT_FIELD (Ebx, HighAddressOfEpcSection);
  1051. PRINT_BIT_FIELD (Ecx, EpcSection);
  1052. PRINT_BIT_FIELD (Ecx, LowSizeOfEpcSection);
  1053. PRINT_BIT_FIELD (Edx, HighSizeOfEpcSection);
  1054. }
  1055. SubLeaf++;
  1056. } while (Eax.Bits.SubLeafType == 0x1);
  1057. }
  1058. /**
  1059. Display Intel SGX Resource Enumeration.
  1060. **/
  1061. VOID
  1062. CpuidEnumerationOfIntelSgx (
  1063. VOID
  1064. )
  1065. {
  1066. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
  1067. if (CPUID_INTEL_SGX > gMaximumBasicFunction) {
  1068. return;
  1069. }
  1070. AsmCpuidEx (
  1071. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
  1072. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
  1073. NULL,
  1074. &Ebx.Uint32,
  1075. NULL,
  1076. NULL
  1077. );
  1078. if (Ebx.Bits.SGX != 1) {
  1079. //
  1080. // Only if CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor has support
  1081. // for Intel SGX.
  1082. //
  1083. return;
  1084. }
  1085. CpuidEnumerationOfIntelSgxCapabilities0SubLeaf ();
  1086. CpuidEnumerationOfIntelSgxCapabilities1SubLeaf ();
  1087. CpuidEnumerationOfIntelSgxResourcesSubLeaf ();
  1088. }
  1089. /**
  1090. Display CPUID_INTEL_PROCESSOR_TRACE sub-leafs.
  1091. @param[in] MaximumSubLeaf Maximum sub-leaf index for CPUID_INTEL_PROCESSOR_TRACE.
  1092. **/
  1093. VOID
  1094. CpuidIntelProcessorTraceSubLeaf (
  1095. UINT32 MaximumSubLeaf
  1096. )
  1097. {
  1098. UINT32 SubLeaf;
  1099. CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;
  1100. CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;
  1101. for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {
  1102. AsmCpuidEx (
  1103. CPUID_INTEL_PROCESSOR_TRACE,
  1104. SubLeaf,
  1105. &Eax.Uint32,
  1106. &Ebx.Uint32,
  1107. NULL,
  1108. NULL
  1109. );
  1110. Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, SubLeaf);
  1111. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, 0);
  1112. PRINT_BIT_FIELD (Eax, ConfigurableAddressRanges);
  1113. PRINT_BIT_FIELD (Eax, MtcPeriodEncodings);
  1114. PRINT_BIT_FIELD (Ebx, CycleThresholdEncodings);
  1115. PRINT_BIT_FIELD (Ebx, PsbFrequencyEncodings);
  1116. }
  1117. }
  1118. /**
  1119. Display CPUID_INTEL_PROCESSOR_TRACE main leaf and sub-leafs.
  1120. **/
  1121. VOID
  1122. CpuidIntelProcessorTraceMainLeaf (
  1123. VOID
  1124. )
  1125. {
  1126. UINT32 Eax;
  1127. CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;
  1128. CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
  1129. if (CPUID_INTEL_PROCESSOR_TRACE > gMaximumBasicFunction) {
  1130. return;
  1131. }
  1132. AsmCpuidEx (
  1133. CPUID_INTEL_PROCESSOR_TRACE,
  1134. CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
  1135. &Eax,
  1136. &Ebx.Uint32,
  1137. &Ecx.Uint32,
  1138. NULL
  1139. );
  1140. Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF);
  1141. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0);
  1142. PRINT_VALUE (Eax, MaximumSubLeaf);
  1143. PRINT_BIT_FIELD (Ebx, Cr3Filter);
  1144. PRINT_BIT_FIELD (Ebx, ConfigurablePsb);
  1145. PRINT_BIT_FIELD (Ebx, IpTraceStopFiltering);
  1146. PRINT_BIT_FIELD (Ebx, Mtc);
  1147. PRINT_BIT_FIELD (Ebx, PTWrite);
  1148. PRINT_BIT_FIELD (Ebx, PowerEventTrace);
  1149. PRINT_BIT_FIELD (Ecx, RTIT);
  1150. PRINT_BIT_FIELD (Ecx, ToPA);
  1151. PRINT_BIT_FIELD (Ecx, SingleRangeOutput);
  1152. PRINT_BIT_FIELD (Ecx, TraceTransportSubsystem);
  1153. PRINT_BIT_FIELD (Ecx, LIP);
  1154. CpuidIntelProcessorTraceSubLeaf (Eax);
  1155. }
  1156. /**
  1157. Display CPUID_TIME_STAMP_COUNTER leaf.
  1158. **/
  1159. VOID
  1160. CpuidTimeStampCounter (
  1161. VOID
  1162. )
  1163. {
  1164. UINT32 Eax;
  1165. UINT32 Ebx;
  1166. UINT32 Ecx;
  1167. if (CPUID_TIME_STAMP_COUNTER > gMaximumBasicFunction) {
  1168. return;
  1169. }
  1170. AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);
  1171. Print (L"CPUID_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_TIME_STAMP_COUNTER);
  1172. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, 0);
  1173. }
  1174. /**
  1175. Display CPUID_PROCESSOR_FREQUENCY leaf.
  1176. **/
  1177. VOID
  1178. CpuidProcessorFrequency (
  1179. VOID
  1180. )
  1181. {
  1182. CPUID_PROCESSOR_FREQUENCY_EAX Eax;
  1183. CPUID_PROCESSOR_FREQUENCY_EBX Ebx;
  1184. CPUID_PROCESSOR_FREQUENCY_ECX Ecx;
  1185. if (CPUID_PROCESSOR_FREQUENCY > gMaximumBasicFunction) {
  1186. return;
  1187. }
  1188. AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
  1189. Print (L"CPUID_PROCESSOR_FREQUENCY (Leaf %08x)\n", CPUID_PROCESSOR_FREQUENCY);
  1190. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, 0);
  1191. PRINT_BIT_FIELD (Eax, ProcessorBaseFrequency);
  1192. PRINT_BIT_FIELD (Ebx, MaximumFrequency);
  1193. PRINT_BIT_FIELD (Ecx, BusFrequency);
  1194. }
  1195. /**
  1196. Display CPUID_SOC_VENDOR sub-leafs that contain the SoC Vendor Brand String.
  1197. Also display these sub-leafs as a single SoC Vendor Brand String.
  1198. **/
  1199. VOID
  1200. CpuidSocVendorBrandString (
  1201. VOID
  1202. )
  1203. {
  1204. CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
  1205. CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
  1206. CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
  1207. CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
  1208. //
  1209. // Array to store brand string from 3 brand string leafs with
  1210. // 4 32-bit brand string values per leaf and an extra value to
  1211. // null terminate the string.
  1212. //
  1213. UINT32 BrandString[3 * 4 + 1];
  1214. AsmCpuidEx (
  1215. CPUID_SOC_VENDOR,
  1216. CPUID_SOC_VENDOR_BRAND_STRING1,
  1217. &Eax.Uint32,
  1218. &Ebx.Uint32,
  1219. &Ecx.Uint32,
  1220. &Edx.Uint32
  1221. );
  1222. Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1);
  1223. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
  1224. BrandString[0] = Eax.Uint32;
  1225. BrandString[1] = Ebx.Uint32;
  1226. BrandString[2] = Ecx.Uint32;
  1227. BrandString[3] = Edx.Uint32;
  1228. AsmCpuidEx (
  1229. CPUID_SOC_VENDOR,
  1230. CPUID_SOC_VENDOR_BRAND_STRING2,
  1231. &Eax.Uint32,
  1232. &Ebx.Uint32,
  1233. &Ecx.Uint32,
  1234. &Edx.Uint32
  1235. );
  1236. Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2);
  1237. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
  1238. BrandString[4] = Eax.Uint32;
  1239. BrandString[5] = Ebx.Uint32;
  1240. BrandString[6] = Ecx.Uint32;
  1241. BrandString[7] = Edx.Uint32;
  1242. AsmCpuidEx (
  1243. CPUID_SOC_VENDOR,
  1244. CPUID_SOC_VENDOR_BRAND_STRING3,
  1245. &Eax.Uint32,
  1246. &Ebx.Uint32,
  1247. &Ecx.Uint32,
  1248. &Edx.Uint32
  1249. );
  1250. Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3);
  1251. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
  1252. BrandString[8] = Eax.Uint32;
  1253. BrandString[9] = Ebx.Uint32;
  1254. BrandString[10] = Ecx.Uint32;
  1255. BrandString[11] = Edx.Uint32;
  1256. BrandString[12] = 0;
  1257. Print (L"Vendor Brand String = %a\n", (CHAR8 *)BrandString);
  1258. }
  1259. /**
  1260. Display CPUID_SOC_VENDOR main leaf and sub-leafs.
  1261. **/
  1262. VOID
  1263. CpuidSocVendor (
  1264. VOID
  1265. )
  1266. {
  1267. UINT32 Eax;
  1268. CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;
  1269. UINT32 Ecx;
  1270. UINT32 Edx;
  1271. if (CPUID_SOC_VENDOR > gMaximumBasicFunction) {
  1272. return;
  1273. }
  1274. AsmCpuidEx (
  1275. CPUID_SOC_VENDOR,
  1276. CPUID_SOC_VENDOR_MAIN_LEAF,
  1277. &Eax,
  1278. &Ebx.Uint32,
  1279. &Ecx,
  1280. &Edx
  1281. );
  1282. Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF);
  1283. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx);
  1284. if (Eax < 3) {
  1285. Print (L" Not Supported\n");
  1286. return;
  1287. }
  1288. PRINT_VALUE (Eax, MaxSOCID_Index);
  1289. PRINT_BIT_FIELD (Ebx, SocVendorId);
  1290. PRINT_BIT_FIELD (Ebx, IsVendorScheme);
  1291. PRINT_VALUE (Ecx, ProjectID);
  1292. PRINT_VALUE (Edx, SteppingID);
  1293. CpuidSocVendorBrandString ();
  1294. }
  1295. /**
  1296. Display CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS main leaf and sub-leafs.
  1297. **/
  1298. VOID
  1299. CpuidDeterministicAddressTranslationParameters (
  1300. VOID
  1301. )
  1302. {
  1303. UINT32 Eax;
  1304. CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX Ebx;
  1305. UINT32 Ecx;
  1306. CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX Edx;
  1307. if (CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS > gMaximumBasicFunction) {
  1308. return;
  1309. }
  1310. AsmCpuidEx (
  1311. CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS,
  1312. CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF,
  1313. &Eax,
  1314. &Ebx.Uint32,
  1315. &Ecx,
  1316. &Edx.Uint32
  1317. );
  1318. Print (L"CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF);
  1319. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx.Uint32);
  1320. PRINT_VALUE (Eax, MaxID_Index);
  1321. PRINT_BIT_FIELD (Ebx, Page4K);
  1322. PRINT_BIT_FIELD (Ebx, Page2M);
  1323. PRINT_BIT_FIELD (Ebx, Page4M);
  1324. PRINT_BIT_FIELD (Ebx, Page1G);
  1325. PRINT_BIT_FIELD (Ebx, Partitioning);
  1326. PRINT_BIT_FIELD (Ebx, Way);
  1327. PRINT_VALUE (Ecx, NumberOfSets);
  1328. PRINT_BIT_FIELD (Edx, TranslationCacheType);
  1329. PRINT_BIT_FIELD (Edx, TranslationCacheLevel);
  1330. PRINT_BIT_FIELD (Edx, FullyAssociative);
  1331. PRINT_BIT_FIELD (Edx, MaximumNum);
  1332. }
  1333. /**
  1334. Display CPUID_EXTENDED_FUNCTION leaf.
  1335. **/
  1336. VOID
  1337. CpuidExtendedFunction (
  1338. VOID
  1339. )
  1340. {
  1341. UINT32 Eax;
  1342. AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
  1343. Print (L"CPUID_EXTENDED_FUNCTION (Leaf %08x)\n", CPUID_EXTENDED_FUNCTION);
  1344. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, 0, 0);
  1345. PRINT_VALUE (Eax, MaximumExtendedFunction);
  1346. gMaximumExtendedFunction = Eax;
  1347. }
  1348. /**
  1349. Display CPUID_EXTENDED_CPU_SIG leaf.
  1350. **/
  1351. VOID
  1352. CpuidExtendedCpuSig (
  1353. VOID
  1354. )
  1355. {
  1356. UINT32 Eax;
  1357. CPUID_EXTENDED_CPU_SIG_ECX Ecx;
  1358. CPUID_EXTENDED_CPU_SIG_EDX Edx;
  1359. if (CPUID_EXTENDED_CPU_SIG > gMaximumExtendedFunction) {
  1360. return;
  1361. }
  1362. AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);
  1363. Print (L"CPUID_EXTENDED_CPU_SIG (Leaf %08x)\n", CPUID_EXTENDED_CPU_SIG);
  1364. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, Ecx.Uint32, Edx.Uint32);
  1365. PRINT_BIT_FIELD (Ecx, LAHF_SAHF);
  1366. PRINT_BIT_FIELD (Ecx, LZCNT);
  1367. PRINT_BIT_FIELD (Ecx, PREFETCHW);
  1368. PRINT_BIT_FIELD (Edx, SYSCALL_SYSRET);
  1369. PRINT_BIT_FIELD (Edx, NX);
  1370. PRINT_BIT_FIELD (Edx, Page1GB);
  1371. PRINT_BIT_FIELD (Edx, RDTSCP);
  1372. PRINT_BIT_FIELD (Edx, LM);
  1373. }
  1374. /**
  1375. Display CPUID_BRAND_STRING1, CPUID_BRAND_STRING2 and CPUID_BRAND_STRING3
  1376. leafs. Also display these three leafs as a single brand string.
  1377. **/
  1378. VOID
  1379. CpuidProcessorBrandString (
  1380. VOID
  1381. )
  1382. {
  1383. CPUID_BRAND_STRING_DATA Eax;
  1384. CPUID_BRAND_STRING_DATA Ebx;
  1385. CPUID_BRAND_STRING_DATA Ecx;
  1386. CPUID_BRAND_STRING_DATA Edx;
  1387. //
  1388. // Array to store brand string from 3 brand string leafs with
  1389. // 4 32-bit brand string values per leaf and an extra value to
  1390. // null terminate the string.
  1391. //
  1392. UINT32 BrandString[3 * 4 + 1];
  1393. if (CPUID_BRAND_STRING1 <= gMaximumExtendedFunction) {
  1394. AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
  1395. Print (L"CPUID_BRAND_STRING1 (Leaf %08x)\n", CPUID_BRAND_STRING1);
  1396. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
  1397. BrandString[0] = Eax.Uint32;
  1398. BrandString[1] = Ebx.Uint32;
  1399. BrandString[2] = Ecx.Uint32;
  1400. BrandString[3] = Edx.Uint32;
  1401. }
  1402. if (CPUID_BRAND_STRING2 <= gMaximumExtendedFunction) {
  1403. AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
  1404. Print (L"CPUID_BRAND_STRING2 (Leaf %08x)\n", CPUID_BRAND_STRING2);
  1405. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
  1406. BrandString[4] = Eax.Uint32;
  1407. BrandString[5] = Ebx.Uint32;
  1408. BrandString[6] = Ecx.Uint32;
  1409. BrandString[7] = Edx.Uint32;
  1410. }
  1411. if (CPUID_BRAND_STRING3 <= gMaximumExtendedFunction) {
  1412. AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
  1413. Print (L"CPUID_BRAND_STRING3 (Leaf %08x)\n", CPUID_BRAND_STRING3);
  1414. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
  1415. BrandString[8] = Eax.Uint32;
  1416. BrandString[9] = Ebx.Uint32;
  1417. BrandString[10] = Ecx.Uint32;
  1418. BrandString[11] = Edx.Uint32;
  1419. }
  1420. BrandString[12] = 0;
  1421. Print (L"Brand String = %a\n", (CHAR8 *)BrandString);
  1422. }
  1423. /**
  1424. Display CPUID_EXTENDED_CACHE_INFO leaf.
  1425. **/
  1426. VOID
  1427. CpuidExtendedCacheInfo (
  1428. VOID
  1429. )
  1430. {
  1431. CPUID_EXTENDED_CACHE_INFO_ECX Ecx;
  1432. if (CPUID_EXTENDED_CACHE_INFO > gMaximumExtendedFunction) {
  1433. return;
  1434. }
  1435. AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);
  1436. Print (L"CPUID_EXTENDED_CACHE_INFO (Leaf %08x)\n", CPUID_EXTENDED_CACHE_INFO);
  1437. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, 0, Ecx.Uint32, 0);
  1438. PRINT_BIT_FIELD (Ecx, CacheLineSize);
  1439. PRINT_BIT_FIELD (Ecx, L2Associativity);
  1440. PRINT_BIT_FIELD (Ecx, CacheSize);
  1441. }
  1442. /**
  1443. Display CPUID_EXTENDED_TIME_STAMP_COUNTER leaf.
  1444. **/
  1445. VOID
  1446. CpuidExtendedTimeStampCounter (
  1447. VOID
  1448. )
  1449. {
  1450. CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;
  1451. if (CPUID_EXTENDED_TIME_STAMP_COUNTER > gMaximumExtendedFunction) {
  1452. return;
  1453. }
  1454. AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);
  1455. Print (L"CPUID_EXTENDED_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_EXTENDED_TIME_STAMP_COUNTER);
  1456. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, 0, 0, Edx.Uint32);
  1457. PRINT_BIT_FIELD (Edx, InvariantTsc);
  1458. }
  1459. /**
  1460. Display CPUID_VIR_PHY_ADDRESS_SIZE leaf.
  1461. **/
  1462. VOID
  1463. CpuidVirPhyAddressSize (
  1464. VOID
  1465. )
  1466. {
  1467. CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;
  1468. if (CPUID_VIR_PHY_ADDRESS_SIZE > gMaximumExtendedFunction) {
  1469. return;
  1470. }
  1471. AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);
  1472. Print (L"CPUID_VIR_PHY_ADDRESS_SIZE (Leaf %08x)\n", CPUID_VIR_PHY_ADDRESS_SIZE);
  1473. Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, 0, 0, 0);
  1474. PRINT_BIT_FIELD (Eax, PhysicalAddressBits);
  1475. PRINT_BIT_FIELD (Eax, LinearAddressBits);
  1476. }
  1477. /**
  1478. The user Entry Point for Application. The user code starts with this function
  1479. as the real entry point for the application.
  1480. @param[in] ImageHandle The firmware allocated handle for the EFI image.
  1481. @param[in] SystemTable A pointer to the EFI System Table.
  1482. @retval EFI_SUCCESS The entry point is executed successfully.
  1483. @retval other Some error occurs when executing this entry point.
  1484. **/
  1485. EFI_STATUS
  1486. EFIAPI
  1487. UefiMain (
  1488. IN EFI_HANDLE ImageHandle,
  1489. IN EFI_SYSTEM_TABLE *SystemTable
  1490. )
  1491. {
  1492. Print (L"UEFI CPUID Version 0.5\n");
  1493. CpuidSignature ();
  1494. CpuidVersionInfo ();
  1495. CpuidCacheInfo ();
  1496. CpuidSerialNumber ();
  1497. CpuidCacheParams ();
  1498. CpuidMonitorMwait ();
  1499. CpuidThermalPowerManagement ();
  1500. CpuidStructuredExtendedFeatureFlags ();
  1501. CpuidDirectCacheAccessInfo ();
  1502. CpuidArchitecturalPerformanceMonitoring ();
  1503. CpuidExtendedTopology (CPUID_EXTENDED_TOPOLOGY);
  1504. CpuidExtendedStateMainLeaf ();
  1505. CpuidIntelRdtMonitoringEnumerationSubLeaf ();
  1506. CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf ();
  1507. CpuidIntelRdtAllocationMainLeaf ();
  1508. CpuidEnumerationOfIntelSgx ();
  1509. CpuidIntelProcessorTraceMainLeaf ();
  1510. CpuidTimeStampCounter ();
  1511. CpuidProcessorFrequency ();
  1512. CpuidSocVendor ();
  1513. CpuidDeterministicAddressTranslationParameters ();
  1514. CpuidExtendedTopology (CPUID_V2_EXTENDED_TOPOLOGY);
  1515. CpuidExtendedFunction ();
  1516. CpuidExtendedCpuSig ();
  1517. CpuidProcessorBrandString ();
  1518. CpuidExtendedCacheInfo ();
  1519. CpuidExtendedTimeStampCounter ();
  1520. CpuidVirPhyAddressSize ();
  1521. return EFI_SUCCESS;
  1522. }