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@@ -58,17 +58,19 @@ CEntryPoint (
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IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
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)
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{
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- // Data Cache enabled on Primary core when MMU is enabled.
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- ArmDisableDataCache ();
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- // Invalidate instruction cache
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- ArmInvalidateInstructionCache ();
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- // Enable Instruction Caches on all cores.
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- ArmEnableInstructionCache ();
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-
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- InvalidateDataCacheRange (
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- (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),
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- PcdGet32 (PcdCPUCorePrimaryStackSize)
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- );
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+ if (!ArmMmuEnabled ()) {
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+ // Data Cache enabled on Primary core when MMU is enabled.
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+ ArmDisableDataCache ();
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+ // Invalidate instruction cache
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+ ArmInvalidateInstructionCache ();
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+ // Enable Instruction Caches on all cores.
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+ ArmEnableInstructionCache ();
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+
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+ InvalidateDataCacheRange (
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+ (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),
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+ PcdGet32 (PcdCPUCorePrimaryStackSize)
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+ );
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+ }
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//
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// Note: Doesn't have to Enable CPU interface in non-secure world,
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