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@@ -16,6 +16,7 @@ Module Name:
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#include <IndustryStandard/E820.h>
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#include <IndustryStandard/I440FxPiix4.h>
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#include <IndustryStandard/Q35MchIch9.h>
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+#include <IndustryStandard/CloudHv.h>
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#include <PiPei.h>
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#include <Register/Intel/SmramSaveStateMap.h>
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@@ -159,6 +160,12 @@ QemuUc32BaseInitialization (
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return;
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}
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+ if (mHostBridgeDevId == CLOUDHV_DEVICE_ID) {
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+ Uc32Size = CLOUDHV_MMIO_HOLE_SIZE;
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+ mQemuUc32Base = CLOUDHV_MMIO_HOLE_ADDRESS;
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+ return;
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+ }
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+
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ASSERT (mHostBridgeDevId == INTEL_82441_DEVICE_ID);
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//
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// On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one
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@@ -819,7 +826,7 @@ QemuInitializeRam (
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// practically any alignment, and we may not have enough variable MTRRs to
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// cover it exactly.
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//
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- if (IsMtrrSupported ()) {
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+ if (IsMtrrSupported () && (mHostBridgeDevId != CLOUDHV_DEVICE_ID)) {
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MtrrGetAllMtrrs (&MtrrSettings);
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//
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