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@@ -37,21 +37,9 @@ Module Name:
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#include <Library/MtrrLib.h>
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#include <Library/QemuFwCfgLib.h>
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#include <Library/QemuFwCfgSimpleParserLib.h>
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-#include <Library/PlatformInitLib.h>
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#include "Platform.h"
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-UINT8 mPhysMemAddressWidth;
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-
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-STATIC UINT32 mS3AcpiReservedMemoryBase;
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-STATIC UINT32 mS3AcpiReservedMemorySize;
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-
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-STATIC UINT16 mQ35TsegMbytes;
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-
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-BOOLEAN mQ35SmramAtDefaultSmbase;
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-
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-UINT32 mQemuUc32Base;
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-
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VOID
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Q35TsegMbytesInitialization (
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VOID
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@@ -60,7 +48,7 @@ Q35TsegMbytesInitialization (
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UINT16 ExtendedTsegMbytes;
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RETURN_STATUS PcdStatus;
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- ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);
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+ ASSERT (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);
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//
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// Check if QEMU offers an extended TSEG.
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@@ -81,7 +69,7 @@ Q35TsegMbytesInitialization (
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PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);
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ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));
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if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {
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- mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);
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+ mPlatformInfoHob.Q35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);
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return;
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}
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@@ -93,7 +81,7 @@ Q35TsegMbytesInitialization (
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));
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PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);
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ASSERT_RETURN_ERROR (PcdStatus);
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- mQ35TsegMbytes = ExtendedTsegMbytes;
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+ mPlatformInfoHob.Q35TsegMbytes = ExtendedTsegMbytes;
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}
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VOID
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@@ -103,9 +91,9 @@ Q35SmramAtDefaultSmbaseInitialization (
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{
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RETURN_STATUS PcdStatus;
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- ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);
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+ ASSERT (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);
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- mQ35SmramAtDefaultSmbase = FALSE;
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+ mPlatformInfoHob.Q35SmramAtDefaultSmbase = FALSE;
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if (FeaturePcdGet (PcdCsmEnable)) {
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DEBUG ((
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DEBUG_INFO,
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@@ -118,37 +106,36 @@ Q35SmramAtDefaultSmbaseInitialization (
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CtlReg = DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL);
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PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY);
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- CtlRegVal = PciRead8 (CtlReg);
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- mQ35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal ==
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- MCH_DEFAULT_SMBASE_IN_RAM);
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+ CtlRegVal = PciRead8 (CtlReg);
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+ mPlatformInfoHob.Q35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal ==
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+ MCH_DEFAULT_SMBASE_IN_RAM);
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DEBUG ((
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DEBUG_INFO,
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"%a: SMRAM at default SMBASE %a\n",
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__FUNCTION__,
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- mQ35SmramAtDefaultSmbase ? "found" : "not found"
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+ mPlatformInfoHob.Q35SmramAtDefaultSmbase ? "found" : "not found"
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));
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}
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PcdStatus = PcdSetBoolS (
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PcdQ35SmramAtDefaultSmbase,
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- mQ35SmramAtDefaultSmbase
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+ mPlatformInfoHob.Q35SmramAtDefaultSmbase
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);
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ASSERT_RETURN_ERROR (PcdStatus);
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}
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VOID
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QemuUc32BaseInitialization (
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- VOID
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+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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)
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{
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UINT32 LowerMemorySize;
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- UINT32 Uc32Size;
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- if (mHostBridgeDevId == 0xffff /* microvm */) {
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+ if (PlatformInfoHob->HostBridgeDevId == 0xffff /* microvm */) {
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return;
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}
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- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
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+ if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
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//
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// On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,
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// starts at PcdPciExpressBaseAddress. The platform DSC is responsible for
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@@ -157,40 +144,40 @@ QemuUc32BaseInitialization (
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// variable MTRRs (preferably 1 or 2).
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//
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ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32);
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- mQemuUc32Base = (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress);
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+ PlatformInfoHob->Uc32Base = (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress);
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return;
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}
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- if (mHostBridgeDevId == CLOUDHV_DEVICE_ID) {
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- Uc32Size = CLOUDHV_MMIO_HOLE_SIZE;
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- mQemuUc32Base = CLOUDHV_MMIO_HOLE_ADDRESS;
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+ if (PlatformInfoHob->HostBridgeDevId == CLOUDHV_DEVICE_ID) {
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+ PlatformInfoHob->Uc32Size = CLOUDHV_MMIO_HOLE_SIZE;
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+ PlatformInfoHob->Uc32Base = CLOUDHV_MMIO_HOLE_ADDRESS;
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return;
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}
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- ASSERT (mHostBridgeDevId == INTEL_82441_DEVICE_ID);
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+ ASSERT (PlatformInfoHob->HostBridgeDevId == INTEL_82441_DEVICE_ID);
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//
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// On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one
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// variable MTRR suffices by truncating the size to a whole power of two,
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// while keeping the end affixed to 4GB. This will round the base up.
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//
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- LowerMemorySize = GetSystemMemorySizeBelow4gb ();
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- Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));
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- mQemuUc32Base = (UINT32)(SIZE_4GB - Uc32Size);
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+ LowerMemorySize = GetSystemMemorySizeBelow4gb (PlatformInfoHob);
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+ PlatformInfoHob->Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));
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+ PlatformInfoHob->Uc32Base = (UINT32)(SIZE_4GB - PlatformInfoHob->Uc32Size);
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//
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// Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB.
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// Therefore mQemuUc32Base is at least 2GB.
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//
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- ASSERT (mQemuUc32Base >= BASE_2GB);
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+ ASSERT (PlatformInfoHob->Uc32Base >= BASE_2GB);
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- if (mQemuUc32Base != LowerMemorySize) {
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+ if (PlatformInfoHob->Uc32Base != LowerMemorySize) {
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DEBUG ((
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DEBUG_VERBOSE,
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"%a: rounded UC32 base from 0x%x up to 0x%x, for "
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"an UC32 size of 0x%x\n",
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__FUNCTION__,
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LowerMemorySize,
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- mQemuUc32Base,
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- Uc32Size
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+ PlatformInfoHob->Uc32Base,
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+ PlatformInfoHob->Uc32Size
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));
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}
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}
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@@ -385,7 +372,7 @@ GetHighestSystemMemoryAddressFromPvhMemmap (
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UINT32
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GetSystemMemorySizeBelow4gb (
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- VOID
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+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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)
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{
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EFI_STATUS Status;
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@@ -393,7 +380,7 @@ GetSystemMemorySizeBelow4gb (
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UINT8 Cmos0x34;
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UINT8 Cmos0x35;
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- if (mHostBridgeDevId == CLOUDHV_DEVICE_ID) {
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+ if (PlatformInfoHob->HostBridgeDevId == CLOUDHV_DEVICE_ID) {
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// Get the information from PVH memmap
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return (UINT32)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE);
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}
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@@ -448,11 +435,10 @@ GetSystemMemorySizeAbove4gb (
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STATIC
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UINT64
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GetFirstNonAddress (
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- VOID
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+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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)
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{
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UINT64 FirstNonAddress;
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- UINT64 Pci64Base, Pci64Size;
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UINT32 FwCfgPciMmio64Mb;
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EFI_STATUS Status;
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FIRMWARE_CONFIG_ITEM FwCfgItem;
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@@ -493,7 +479,7 @@ GetFirstNonAddress (
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// Otherwise, in order to calculate the highest address plus one, we must
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// consider the 64-bit PCI host aperture too. Fetch the default size.
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//
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- Pci64Size = PcdGet64 (PcdPciMmio64Size);
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+ PlatformInfoHob->PcdPciMmio64Size = PcdGet64 (PcdPciMmio64Size);
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//
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// See if the user specified the number of megabytes for the 64-bit PCI host
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@@ -513,7 +499,7 @@ GetFirstNonAddress (
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break;
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case EFI_SUCCESS:
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if (FwCfgPciMmio64Mb <= 0x1000000) {
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- Pci64Size = LShiftU64 (FwCfgPciMmio64Mb, 20);
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+ PlatformInfoHob->PcdPciMmio64Size = LShiftU64 (FwCfgPciMmio64Mb, 20);
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break;
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}
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@@ -529,8 +515,8 @@ GetFirstNonAddress (
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break;
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}
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- if (Pci64Size == 0) {
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- if (mBootMode != BOOT_ON_S3_RESUME) {
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+ if (PlatformInfoHob->PcdPciMmio64Size == 0) {
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+ if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {
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DEBUG ((
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DEBUG_INFO,
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"%a: disabling 64-bit PCI host aperture\n",
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@@ -577,8 +563,8 @@ GetFirstNonAddress (
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// SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so
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// that the host can map it with 1GB hugepages. Follow suit.
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//
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- Pci64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);
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- Pci64Size = ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB);
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+ PlatformInfoHob->PcdPciMmio64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);
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+ PlatformInfoHob->PcdPciMmio64Size = ALIGN_VALUE (PlatformInfoHob->PcdPciMmio64Size, (UINT64)SIZE_1GB);
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//
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// The 64-bit PCI host aperture should also be "naturally" aligned. The
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@@ -586,32 +572,32 @@ GetFirstNonAddress (
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// next smaller or equal power of two. That is, align the aperture by the
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// largest BAR size that can fit into it.
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//
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- Pci64Base = ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size));
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+ PlatformInfoHob->PcdPciMmio64Base = ALIGN_VALUE (PlatformInfoHob->PcdPciMmio64Base, GetPowerOfTwo64 (PlatformInfoHob->PcdPciMmio64Size));
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- if (mBootMode != BOOT_ON_S3_RESUME) {
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+ if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {
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//
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// The core PciHostBridgeDxe driver will automatically add this range to
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// the GCD memory space map through our PciHostBridgeLib instance; here we
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// only need to set the PCDs.
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//
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- PcdStatus = PcdSet64S (PcdPciMmio64Base, Pci64Base);
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+ PcdStatus = PcdSet64S (PcdPciMmio64Base, PlatformInfoHob->PcdPciMmio64Base);
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ASSERT_RETURN_ERROR (PcdStatus);
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- PcdStatus = PcdSet64S (PcdPciMmio64Size, Pci64Size);
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+ PcdStatus = PcdSet64S (PcdPciMmio64Size, PlatformInfoHob->PcdPciMmio64Size);
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ASSERT_RETURN_ERROR (PcdStatus);
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DEBUG ((
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DEBUG_INFO,
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"%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",
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__FUNCTION__,
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- Pci64Base,
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- Pci64Size
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+ PlatformInfoHob->PcdPciMmio64Base,
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+ PlatformInfoHob->PcdPciMmio64Size
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));
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}
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//
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// The useful address space ends with the 64-bit PCI host aperture.
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//
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- FirstNonAddress = Pci64Base + Pci64Size;
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+ FirstNonAddress = PlatformInfoHob->PcdPciMmio64Base + PlatformInfoHob->PcdPciMmio64Size;
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return FirstNonAddress;
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}
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@@ -620,10 +606,11 @@ GetFirstNonAddress (
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**/
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VOID
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AddressWidthInitialization (
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- VOID
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+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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)
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{
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UINT64 FirstNonAddress;
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+ UINT8 PhysMemAddressWidth;
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//
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// As guest-physical memory size grows, the permanent PEI RAM requirements
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@@ -631,15 +618,15 @@ AddressWidthInitialization (
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// The DXL IPL keys off of the physical address bits advertized in the CPU
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// HOB. To conserve memory, we calculate the minimum address width here.
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//
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- FirstNonAddress = GetFirstNonAddress ();
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- mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);
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+ FirstNonAddress = GetFirstNonAddress (PlatformInfoHob);
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+ PhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);
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//
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// If FirstNonAddress is not an integral power of two, then we need an
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// additional bit.
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//
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if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {
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- ++mPhysMemAddressWidth;
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+ ++PhysMemAddressWidth;
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}
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//
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@@ -648,11 +635,14 @@ AddressWidthInitialization (
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// X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We
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// can simply assert that here, since 48 bits are good enough for 256 TB.
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//
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- if (mPhysMemAddressWidth <= 36) {
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- mPhysMemAddressWidth = 36;
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+ if (PhysMemAddressWidth <= 36) {
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+ PhysMemAddressWidth = 36;
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}
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- ASSERT (mPhysMemAddressWidth <= 48);
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+ ASSERT (PhysMemAddressWidth <= 48);
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+
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+ PlatformInfoHob->FirstNonAddress = FirstNonAddress;
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+ PlatformInfoHob->PhysMemAddressWidth = PhysMemAddressWidth;
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}
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/**
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@@ -698,12 +688,12 @@ GetPeiMemoryCap (
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}
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}
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- if (mPhysMemAddressWidth <= 39) {
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+ if (mPlatformInfoHob.PhysMemAddressWidth <= 39) {
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Pml4Entries = 1;
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- PdpEntries = 1 << (mPhysMemAddressWidth - 30);
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+ PdpEntries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 30);
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ASSERT (PdpEntries <= 0x200);
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} else {
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- Pml4Entries = 1 << (mPhysMemAddressWidth - 39);
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+ Pml4Entries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 39);
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ASSERT (Pml4Entries <= 0x200);
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PdpEntries = 512;
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}
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@@ -736,38 +726,46 @@ PublishPeiMemory (
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UINT64 MemorySize;
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UINT32 LowerMemorySize;
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UINT32 PeiMemoryCap;
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+ UINT32 S3AcpiReservedMemoryBase;
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+ UINT32 S3AcpiReservedMemorySize;
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- LowerMemorySize = GetSystemMemorySizeBelow4gb ();
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- if (FeaturePcdGet (PcdSmmSmramRequire)) {
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+ LowerMemorySize = GetSystemMemorySizeBelow4gb (&mPlatformInfoHob);
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+ if (mPlatformInfoHob.SmmSmramRequire) {
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//
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// TSEG is chipped from the end of low RAM
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//
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- LowerMemorySize -= mQ35TsegMbytes * SIZE_1MB;
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+ LowerMemorySize -= mPlatformInfoHob.Q35TsegMbytes * SIZE_1MB;
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}
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+ S3AcpiReservedMemoryBase = 0;
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+ S3AcpiReservedMemorySize = 0;
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+
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//
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// If S3 is supported, then the S3 permanent PEI memory is placed next,
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// downwards. Its size is primarily dictated by CpuMpPei. The formula below
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// is an approximation.
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//
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- if (mS3Supported) {
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- mS3AcpiReservedMemorySize = SIZE_512KB +
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- mMaxCpuCount *
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- PcdGet32 (PcdCpuApStackSize);
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- mS3AcpiReservedMemoryBase = LowerMemorySize - mS3AcpiReservedMemorySize;
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- LowerMemorySize = mS3AcpiReservedMemoryBase;
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+ if (mPlatformInfoHob.S3Supported) {
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+ S3AcpiReservedMemorySize = SIZE_512KB +
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+ mPlatformInfoHob.PcdCpuMaxLogicalProcessorNumber *
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+ PcdGet32 (PcdCpuApStackSize);
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+ S3AcpiReservedMemoryBase = LowerMemorySize - S3AcpiReservedMemorySize;
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+ LowerMemorySize = S3AcpiReservedMemoryBase;
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}
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- if (mBootMode == BOOT_ON_S3_RESUME) {
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- MemoryBase = mS3AcpiReservedMemoryBase;
|
|
|
- MemorySize = mS3AcpiReservedMemorySize;
|
|
|
+ mPlatformInfoHob.S3AcpiReservedMemoryBase = S3AcpiReservedMemoryBase;
|
|
|
+ mPlatformInfoHob.S3AcpiReservedMemorySize = S3AcpiReservedMemorySize;
|
|
|
+
|
|
|
+ if (mPlatformInfoHob.BootMode == BOOT_ON_S3_RESUME) {
|
|
|
+ MemoryBase = S3AcpiReservedMemoryBase;
|
|
|
+ MemorySize = S3AcpiReservedMemorySize;
|
|
|
} else {
|
|
|
PeiMemoryCap = GetPeiMemoryCap ();
|
|
|
DEBUG ((
|
|
|
DEBUG_INFO,
|
|
|
"%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
|
|
|
__FUNCTION__,
|
|
|
- mPhysMemAddressWidth,
|
|
|
+ mPlatformInfoHob.PhysMemAddressWidth,
|
|
|
PeiMemoryCap >> 10
|
|
|
));
|
|
|
|
|
@@ -781,7 +779,7 @@ PublishPeiMemory (
|
|
|
// allocation HOB, and other allocations served from the permanent PEI RAM
|
|
|
// shouldn't overlap with that HOB.
|
|
|
//
|
|
|
- MemoryBase = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?
|
|
|
+ MemoryBase = mPlatformInfoHob.S3Supported && mPlatformInfoHob.SmmSmramRequire ?
|
|
|
PcdGet32 (PcdOvmfDecompressionScratchEnd) :
|
|
|
PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);
|
|
|
MemorySize = LowerMemorySize - MemoryBase;
|
|
@@ -796,7 +794,7 @@ PublishPeiMemory (
|
|
|
// normal boot permanent PEI RAM. Regarding the S3 boot path, the S3
|
|
|
// permanent PEI RAM is located even higher.
|
|
|
//
|
|
|
- if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {
|
|
|
+ if (mPlatformInfoHob.SmmSmramRequire && mPlatformInfoHob.Q35SmramAtDefaultSmbase) {
|
|
|
ASSERT (SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE <= MemoryBase);
|
|
|
}
|
|
|
|
|
@@ -812,10 +810,10 @@ PublishPeiMemory (
|
|
|
STATIC
|
|
|
VOID
|
|
|
QemuInitializeRamBelow1gb (
|
|
|
- VOID
|
|
|
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
|
|
|
)
|
|
|
{
|
|
|
- if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {
|
|
|
+ if (PlatformInfoHob->SmmSmramRequire && PlatformInfoHob->Q35SmramAtDefaultSmbase) {
|
|
|
PlatformAddMemoryRangeHob (0, SMM_DEFAULT_SMBASE);
|
|
|
PlatformAddReservedMemoryBaseSizeHob (
|
|
|
SMM_DEFAULT_SMBASE,
|
|
@@ -842,7 +840,7 @@ QemuInitializeRamBelow1gb (
|
|
|
STATIC
|
|
|
VOID
|
|
|
QemuInitializeRam (
|
|
|
- VOID
|
|
|
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
|
|
|
)
|
|
|
{
|
|
|
UINT64 LowerMemorySize;
|
|
@@ -855,9 +853,9 @@ QemuInitializeRam (
|
|
|
//
|
|
|
// Determine total memory size available
|
|
|
//
|
|
|
- LowerMemorySize = GetSystemMemorySizeBelow4gb ();
|
|
|
+ LowerMemorySize = GetSystemMemorySizeBelow4gb (PlatformInfoHob);
|
|
|
|
|
|
- if (mBootMode == BOOT_ON_S3_RESUME) {
|
|
|
+ if (PlatformInfoHob->BootMode == BOOT_ON_S3_RESUME) {
|
|
|
//
|
|
|
// Create the following memory HOB as an exception on the S3 boot path.
|
|
|
//
|
|
@@ -878,17 +876,17 @@ QemuInitializeRam (
|
|
|
// allocation HOBs, and to honor preexistent memory allocation HOBs when
|
|
|
// looking for an area to borrow.
|
|
|
//
|
|
|
- QemuInitializeRamBelow1gb ();
|
|
|
+ QemuInitializeRamBelow1gb (PlatformInfoHob);
|
|
|
} else {
|
|
|
//
|
|
|
// Create memory HOBs
|
|
|
//
|
|
|
- QemuInitializeRamBelow1gb ();
|
|
|
+ QemuInitializeRamBelow1gb (PlatformInfoHob);
|
|
|
|
|
|
- if (FeaturePcdGet (PcdSmmSmramRequire)) {
|
|
|
+ if (PlatformInfoHob->SmmSmramRequire) {
|
|
|
UINT32 TsegSize;
|
|
|
|
|
|
- TsegSize = mQ35TsegMbytes * SIZE_1MB;
|
|
|
+ TsegSize = PlatformInfoHob->Q35TsegMbytes * SIZE_1MB;
|
|
|
PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);
|
|
|
PlatformAddReservedMemoryBaseSizeHob (
|
|
|
LowerMemorySize - TsegSize,
|
|
@@ -924,7 +922,7 @@ QemuInitializeRam (
|
|
|
// practically any alignment, and we may not have enough variable MTRRs to
|
|
|
// cover it exactly.
|
|
|
//
|
|
|
- if (IsMtrrSupported () && (mHostBridgeDevId != CLOUDHV_DEVICE_ID)) {
|
|
|
+ if (IsMtrrSupported () && (PlatformInfoHob->HostBridgeDevId != CLOUDHV_DEVICE_ID)) {
|
|
|
MtrrGetAllMtrrs (&MtrrSettings);
|
|
|
|
|
|
//
|
|
@@ -957,8 +955,8 @@ QemuInitializeRam (
|
|
|
// MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable.
|
|
|
//
|
|
|
Status = MtrrSetMemoryAttribute (
|
|
|
- mQemuUc32Base,
|
|
|
- SIZE_4GB - mQemuUc32Base,
|
|
|
+ PlatformInfoHob->Uc32Base,
|
|
|
+ SIZE_4GB - PlatformInfoHob->Uc32Base,
|
|
|
CacheUncacheable
|
|
|
);
|
|
|
ASSERT_EFI_ERROR (Status);
|
|
@@ -971,20 +969,20 @@ QemuInitializeRam (
|
|
|
**/
|
|
|
VOID
|
|
|
InitializeRamRegions (
|
|
|
- VOID
|
|
|
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
|
|
|
)
|
|
|
{
|
|
|
- QemuInitializeRam ();
|
|
|
+ QemuInitializeRam (PlatformInfoHob);
|
|
|
|
|
|
SevInitializeRam ();
|
|
|
|
|
|
- if (mS3Supported && (mBootMode != BOOT_ON_S3_RESUME)) {
|
|
|
+ if (PlatformInfoHob->S3Supported && (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME)) {
|
|
|
//
|
|
|
// This is the memory range that will be used for PEI on S3 resume
|
|
|
//
|
|
|
BuildMemoryAllocationHob (
|
|
|
- mS3AcpiReservedMemoryBase,
|
|
|
- mS3AcpiReservedMemorySize,
|
|
|
+ PlatformInfoHob->S3AcpiReservedMemoryBase,
|
|
|
+ PlatformInfoHob->S3AcpiReservedMemorySize,
|
|
|
EfiACPIMemoryNVS
|
|
|
);
|
|
|
|
|
@@ -1021,7 +1019,7 @@ InitializeRamRegions (
|
|
|
EfiACPIMemoryNVS
|
|
|
);
|
|
|
|
|
|
- if (MemEncryptSevEsIsEnabled ()) {
|
|
|
+ if (PlatformInfoHob->SevEsIsEnabled) {
|
|
|
//
|
|
|
// If SEV-ES is enabled, reserve the GHCB-related memory area. This
|
|
|
// includes the extra page table used to break down the 2MB page
|
|
@@ -1051,8 +1049,8 @@ InitializeRamRegions (
|
|
|
#endif
|
|
|
}
|
|
|
|
|
|
- if (mBootMode != BOOT_ON_S3_RESUME) {
|
|
|
- if (!FeaturePcdGet (PcdSmmSmramRequire)) {
|
|
|
+ if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {
|
|
|
+ if (!PlatformInfoHob->SmmSmramRequire) {
|
|
|
//
|
|
|
// Reserve the lock box storage area
|
|
|
//
|
|
@@ -1070,20 +1068,20 @@ InitializeRamRegions (
|
|
|
BuildMemoryAllocationHob (
|
|
|
(EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),
|
|
|
(UINT64)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize),
|
|
|
- mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
|
|
|
+ PlatformInfoHob->S3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
|
|
|
);
|
|
|
}
|
|
|
|
|
|
- if (FeaturePcdGet (PcdSmmSmramRequire)) {
|
|
|
+ if (PlatformInfoHob->SmmSmramRequire) {
|
|
|
UINT32 TsegSize;
|
|
|
|
|
|
//
|
|
|
// Make sure the TSEG area that we reported as a reserved memory resource
|
|
|
// cannot be used for reserved memory allocations.
|
|
|
//
|
|
|
- TsegSize = mQ35TsegMbytes * SIZE_1MB;
|
|
|
+ TsegSize = PlatformInfoHob->Q35TsegMbytes * SIZE_1MB;
|
|
|
BuildMemoryAllocationHob (
|
|
|
- GetSystemMemorySizeBelow4gb () - TsegSize,
|
|
|
+ GetSystemMemorySizeBelow4gb (PlatformInfoHob) - TsegSize,
|
|
|
TsegSize,
|
|
|
EfiReservedMemoryType
|
|
|
);
|
|
@@ -1091,7 +1089,7 @@ InitializeRamRegions (
|
|
|
// Similarly, allocate away the (already reserved) SMRAM at the default
|
|
|
// SMBASE, if it exists.
|
|
|
//
|
|
|
- if (mQ35SmramAtDefaultSmbase) {
|
|
|
+ if (PlatformInfoHob->Q35SmramAtDefaultSmbase) {
|
|
|
BuildMemoryAllocationHob (
|
|
|
SMM_DEFAULT_SMBASE,
|
|
|
MCH_DEFAULT_SMBASE_SIZE,
|
|
@@ -1115,7 +1113,7 @@ InitializeRamRegions (
|
|
|
BuildMemoryAllocationHob (
|
|
|
(EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaBase),
|
|
|
(UINT64)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaSize),
|
|
|
- mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
|
|
|
+ PlatformInfoHob->S3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
|
|
|
);
|
|
|
}
|
|
|
|