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@@ -1,7 +1,7 @@
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/** @file
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Common header file for CPU Exception Handler Library.
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- Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>
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+ Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@@ -49,6 +49,73 @@
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#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE)
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+#define CPU_EXCEPTION_INIT_DATA_REV 1
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+
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+typedef union {
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+ struct {
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+ //
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+ // Revision number of this structure.
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+ //
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+ UINT32 Revision;
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+ //
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+ // The address of top of known good stack reserved for *ALL* exceptions
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+ // listed in field StackSwitchExceptions.
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+ //
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+ UINTN KnownGoodStackTop;
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+ //
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+ // The size of known good stack for *ONE* exception only.
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+ //
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+ UINTN KnownGoodStackSize;
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+ //
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+ // Buffer of exception vector list for stack switch.
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+ //
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+ UINT8 *StackSwitchExceptions;
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+ //
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+ // Number of exception vectors in StackSwitchExceptions.
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+ //
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+ UINTN StackSwitchExceptionNumber;
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+ //
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+ // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR.
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+ // Normally there's no need to change IDT table size.
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+ //
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+ VOID *IdtTable;
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+ //
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+ // Size of buffer for IdtTable.
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+ //
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+ UINTN IdtTableSize;
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+ //
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+ // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR.
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+ //
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+ VOID *GdtTable;
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+ //
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+ // Size of buffer for GdtTable.
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+ //
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+ UINTN GdtTableSize;
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+ //
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+ // Pointer to start address of descriptor of exception task gate in the
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+ // GDT table. It must be type of IA32_TSS_DESCRIPTOR.
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+ //
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+ VOID *ExceptionTssDesc;
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+ //
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+ // Size of buffer for ExceptionTssDesc.
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+ //
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+ UINTN ExceptionTssDescSize;
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+ //
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+ // Buffer of task-state segment for exceptions. It must be type of
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+ // IA32_TASK_STATE_SEGMENT.
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+ //
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+ VOID *ExceptionTss;
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+ //
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+ // Size of buffer for ExceptionTss.
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+ //
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+ UINTN ExceptionTssSize;
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+ //
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+ // Flag to indicate if default handlers should be initialized or not.
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+ //
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+ BOOLEAN InitDefaultHandlers;
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+ } Ia32, X64;
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+} CPU_EXCEPTION_INIT_DATA;
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+
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//
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// Record exception handler information
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//
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