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@@ -62,7 +62,7 @@
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gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038
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# Stack for CPU Cores in Secure Mode
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- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005
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+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT64|0x00000005
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006
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@@ -188,13 +188,13 @@
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[PcdsFixedAtBuild.ARM]
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# Stack for CPU Cores in Secure Monitor Mode
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- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
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+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008
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[PcdsFixedAtBuild.AARCH64]
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# The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.
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# The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize
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# and PcdCPUCoreSecSecondaryStackSize
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- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
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+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008
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