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+/** @file
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+ The Smm Base HOB is used to store the information of:
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+ * The relocated SmBase address in array for each processor.
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+
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+ The default Smbase for the x86 processor is 0x30000. When SMI happens, processor
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+ runs the SMI handler at Smbase+0x8000. Also, the SMM save state area is within
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+ Smbase+0x10000. Since it's the start address to store the processor save state
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+ and code for the SMI entry point, those info are tiled within an SMRAM allocated
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+ or reserved buffer. This tile size shall be enough to cover 3 parts:
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+ 1. Processor SMRAM Save State Map starts at Smbase + 0xfc00
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+ 2. Extra processor specific context start starts at Smbase + 0xfb00
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+ 3. SMI entry point starts at Smbase + 0x8000.
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+ Besides, This size should be rounded up to nearest power of 2. The Smm Base HOB
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+ producer should be responsible for reserving enough size.
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+
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+ One of the SMM initialization from processor perspective is to relocate and program
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+ the new Smbase (in TSEG range) for each processor thread. When the Smbase relocation
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+ happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB in HOB database
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+ which tells the PiSmmCpuDxeSmm driver (which runs at a later phase) about the new
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+ Smbase for each processor. PiSmmCpuDxeSmm driver installs the SMI handler at the
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+ SMM_BASE_HOB.Smbase[Index]+0x8000 for processor index. When the HOB doesn't exist,
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+ PiSmmCpuDxeSmm driver shall relocate and program the new Smbase itself.
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+
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+ Note:
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+ 1. Smbase relocation process needs to program the vender specific hardware
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+ interface to set Smbase, it might be in the thread scope. It's doable to
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+ program the hardware interface using DXE MP service protocol in PiSmmCpuDxeSmm
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+ entry point. But, considering the standalone MM environment where the CpuMm
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+ driver runs in a isolated environment and it cannot invoke any DXE or PEI MP
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+ service, we recommend to put the hardware interface programming in a separate
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+ PEI module instead of in the PiSmmCpuDxeSmm driver.
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+
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+ 2. There is the hard requirement that SMI Entry Size <= 0x1000, data Size <=
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+ 0x1000 in PiSmmCpuDxeSmm. So, this require the allocated or reserved buffer in
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+ SMRAM should be >= 0x2000.
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+
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+ Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
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+ SPDX-License-Identifier: BSD-2-Clause-Patent
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+
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+**/
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+
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+#ifndef SMM_BASE_HOB_H_
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+#define SMM_BASE_HOB_H_
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+
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+#define SMM_BASE_HOB_DATA_GUID \
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+ { \
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+ 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73} \
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+ }
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+
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+#pragma pack(1)
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+typedef struct {
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+ ///
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+ /// ProcessorIndex tells which processor range this specific HOB instance described.
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+ /// If ProcessorIndex is set to 0, it indicats the HOB describes the processor from
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+ /// 0 to NumberOfProcessors - 1. The HOB list may contains multiple this HOB
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+ /// instances. Each HOB instances describe the information for processor from
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+ /// ProcessorIndex to ProcessorIndex + NumberOfProcessors - 1. The instance order in
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+ /// the HOB list is random so consumer can not assume the ProcessorIndex of first
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+ /// instance is 0.
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+ ///
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+ UINT32 ProcessorIndex;
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+ ///
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+ /// Describes the Number of all max supported processors.
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+ ///
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+ UINT32 NumberOfProcessors;
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+ ///
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+ /// Pointer to SmBase address for each processor.
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+ ///
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+ UINT64 SmBase[];
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+} SMM_BASE_HOB_DATA;
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+#pragma pack()
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+
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+extern EFI_GUID gSmmBaseHobGuid;
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+
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+#endif
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